Marvell
Jobs
25 open positions · Direct from career page
25 open roles at Marvell, indexed directly from their ATS — not reposted from LinkedIn, Indeed, or Glassdoor. Advertised salaries average $160k/year. 8% of roles are remote-friendly. Upload your resume to see which roles you'd likely pass their ATS screening.
Open Roles
25
Avg Salary
$160k
Remote-Friendly
8%
Sectors at Marvell
25 of 25 positions Updated daily
Senior Principal Engineer, Architecture ASIC / System
Toronto, Canada Remote Senior May 30
Senior Compensation Business Partner
Santa Clara, CA Onsite Senior Jun 5
Silicon Validation Manager
Santa Clara, CA Onsite Manager Jun 2
Senior Compensation Business Partner
Santa Clara, CA Onsite Senior Jun 5
Senior Principal Engineer, Architecture ASIC / System
Toronto, Canada Remote Senior May 30
Global Compensation Program and Tools Manager
Santa Clara, CA Onsite Manager Jun 5
Principal Engineer, ASIC/VLSI Synthesis and Design
San Diego, CA Lead May 27
Senior Staff Engineer, ASIC/VLSI Synthesis and Design
San Diego, CA Senior May 27
Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis
San Diego, CA Lead May 27
Senior Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis
San Diego, CA Senior May 27
Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis
San Diego, CA Staff May 27
Staff Engineer, ASIC/VLSI Synthesis and Design
San Diego, CA Staff May 27
Senior Staff Engineer, ASIC/VLSI Synthesis and Design
San Diego, CA Senior May 28
Senior Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis
San Diego, CA Senior May 28
Staff Engineer, ASIC/VLSI Synthesis and Design
San Diego, CA Staff May 28
Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis
San Diego, CA Staff May 28
Principal Engineer, ASIC/VLSI Synthesis and Design
San Diego, CA Lead May 28
Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis
San Diego, CA Lead May 28
Custom Cloud/AI Data Center Lead Architect
Santa Clara, CA May 21
Analog Design Engineer, Principal
Pavia, Italy on-site Principal May 6
Analog Layout Senior Staff Engineer
Pavia, Italy Senior Apr 25
Principal Validation Lead
Santa Clara, CA No Lead May 16
Rack Level Integration Engineer
Santa Clara, CA No Mid May 9
Director, AI Governance & Enablement
Santa Clara, CA No Director Apr 21
Staff DFT Engineer
Santa Clara, CA No Staff Apr 24