Marvell
Semiconductor
StaffEngineer,ASICDesign/Implementation-LEC/STA/PowerAnalysis
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“Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis at Marvell. Skills: ASIC Design, STA, Timing Constraints, Power Analysis. Develop and validate timing constraints. Collaborate with Architecture, RTL, DFT, and Analog teams”
What You'll Achieve.
meeting performance, power and area goals
Industry & Context.
Excellent problem-solving skills; ability to analyze and debug complex issues
access to technology and/or software subject to U. S. export control laws and regulations, eligible to access export-controlled information, may be required to obtain export licensing approval, may be subject to an export license review process prior to employment
What They're Looking For.
Must Have
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience, Minimum of 1 year of industry experience in ASIC timing and STA, understanding of ASIC design flows, from RTL to GDSII, Knowledge and hands-on experience with STA methodologies and implementation, Proficiency in using STA tools, Proficiency in scripting languages (e.g., Tcl, Perl), Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5, understanding of timing constraint development for hierarchical designs, timing ECO creation and final timing signoff, Proven track record of delivering successful designs on time and meeting performance, power and area goals, Excellent problem-solving skills, attention to detail, ability to analyze and debug complex issues, communication and collaboration skills to work effectively within cross-functional teams
Nice to Have
experience with deep technology nodes such as 5nm/4nm, Familiarity with physical design and timing optimization techniques and strategies to achieve deterministic timing closure
What You'll Do.
Develop and validate timing constraints
Collaborate with Architecture
Own and contribute to STA tasks
Perform static timing analysis (STA)
Define and implement timing signoff methodologies
Resolve or find workarounds for tool issues
Conduct post-route timing checks
Automate STA related processes/flow
Create QoR dashboards
Ensure compliance with timing signoff checklists
Document best practices
How You'll Work.
Team & Collaboration
Collaborate with Architecture, RTL, DFT, and Analog teams; work effectively within cross-functional teams
Communication Scope
communication skills; collaboration skills
Full Job Description
**About Marvell** Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. **Your Team, Your Impact** As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOC) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system interconnect bandwidth, memory bandwidth, and memory capacity. Marvell's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bo
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