Marvell
semiconductor
PrincipalValidationLead
Neural analysis suggests this role is
optimal for Lead candidates.
“Principal Validation Lead at Marvell. Skills: CXL 3.x, HBM, DDR, PCIe, high-speed SerDes, ASIC/SoC validation, silicon bring-up, lab validation, lab automation, data analysis, cross-functional debug. Define overall validation strategy and test plans for ASIC/SoC devices with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces, covering functionality, performance, power, margining, and interoperability. Lead silicon bring-up and lab validation, including platform bring-up (boards, power, cl”
What You'll Achieve.
affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow; improve coverage, throughput, and reproducibility; translate findings into design and validation recommendations; build a strong, scalable lab validation team and best practices
Industry & Context.
debug; root-cause investigations; cross-functional debug; issue closure
This position may require access to technology and/or software subject to U. S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U. S. Department of Commerce and/or the U. S. Department of State. Except for U. S. citizens, lawful permanent residents, or protected individuals as defined by 8 U. S. C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
What They're Looking For.
Must Have
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, 8+ years of industry experience in silicon or system validation, including hands-on lab work, expertise in at least two of the following: CXL (2.0/3.x), PCIe (Gen4/Gen5/Gen6), DDR (DDR4/DDR5), HBM (HBM2/2E/3), high-speed SerDes, Proven experience leading bring-up and validation of complex ASIC/SoC products from first silicon through production, Deep hands-on experience with lab equipment (oscilloscopes, protocol analyzers, logic analyzers, BERTs, power supplies, etc. ) and high-speed measurement techniques, scripting and lab automation skills (e.g. , Python, TCL, shell, MATLAB) for test control and data analysis, Demonstrated ability to drive cross-functional debug and closure, with clear communication of complex technical issues
Nice to Have
Master’s degree in Electrical Engineering, Computer Engineering, or related field, Experience leading small validation teams or acting as technical lead on multi‑site projects, Familiarity with DFT features (scan, BIST, JTAG) and their use in bring-up and debug, Experience with signal integrity/power integrity concepts and working with SI/PI or board design teams
What You'll Do.
Define overall validation strategy and test plans for ASIC/SoC devices with CXL 3.x
and high-speed SerDes interfaces
covering functionality
Lead silicon bring-up and lab validation
including platform bring-up (boards
resets) and interface‑level validation for CXL/PCIe/DDR/HBM/SerDes
Provide technical direction to other validation engineers
including test plan reviews
and prioritization of tasks and issues
Configure and operate advanced lab equipment
Drive development of lab automation and data analysis infrastructure
Analyze large data sets to characterize high-speed links and memory interfaces
Lead root-cause investigations across silicon
Own documentation of validation methodologies
Mentor and coach junior validation engineers
How You'll Work.
Team & Collaboration
coordination across design, DFT, firmware, and product/test engineering; Provide technical direction to other validation engineers; coordinate cross-functional issue closure with design, DFT, firmware, and product/test engineering; working with SI/PI or board design teams
Communication Scope
clear communication of complex technical issues; communicate status, risks, and mitigation plans to project leadership
Process & Methodology
Define overall validation strategy, test planning, prioritization of tasks and issues, communicate status, risks, and mitigation plans to project leadership
Full Job Description
**About Marvell** Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. **Your Team, Your Impact** The Principal Validation Engineer (Lead) will own the lab validation strategy and execution for advanced ASIC/SoC products integrating CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes. This role combines hands-on silicon bring-up and debug with technical leadership of validation activities, including test planning, methodology, and coordination across design, DFT, firmware, and product/test engineering. **What You Can Expect** * Define overall validation strategy and test plans for ASIC/SoC devices with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces, covering functionality, performance, power, margining, and interoperability. * Lead silicon bring-up and lab validation, including platform bring-up (boards, power, clocks, resets) and interface‑level validation for CXL/PCIe/DDR/HBM/SerDes. * Provide technical direction to other validation engineers, including test plan reviews, debug guidance, and prioritization of tasks and issues. * Configure and operate advanced lab equipment: high‑bandwidth oscilloscopes and probes, logic analyzers, PCIe/CXL protocol analyzers, BERTs, pattern generators, power supplies, electronic loads, and environmental chambers. * Drive development of lab automation and data analysis infrastructure (Python, TCL, shell, MATLAB or similar) to improve coverage, throughput, and reproducibility. * Analyze large data sets to characterize high-speed links and memory
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