Marvell
semiconductor
StaffDFTEngineer
Neural analysis suggests this role is
optimal for Staff candidates.
“Staff DFT Engineer at Marvell. Skills: Scan DFT implementation, Scan Streaming Network (SSN), IJTAG (IEEE 1687), ATPG pattern generation, coverage analysis, DRC closure, DFT signoff. Lead hands-on scan DFT implementation. Scan insertion and stitching”
What You'll Achieve.
scan quality; coverage closure; DFT signoff; scan coverage improvement and closure; pattern efficiency; test quality
Industry & Context.
problem-solving skills; Debug and resolve scan-related DRCs, connectivity issues, and control signal problems; Debug and resolve scan-related DRCs, connectivity issues, and control signal problems
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
What They're Looking For.
Must Have
8 + years of hands-on experience in DFT scan implementation, expertise with Siemens Tessent, including: Scan insertion and verification, ATPG pattern generation and coverage analysis, IJTAG (IEEE 1687) and SSN implementation, understanding of: Scan Streaming Network (SSN), IEEE 1149. x, IEEE 1500, and IEEE 1687 standards, Proven ability to resolve scan DFT DRCs and drive coverage closure, TCL scripting skills for automation and flow customization, Experience developing and validating scan and test-mode timing constraints, Full DFT lifecycle experience, from RTL/netlist through silicon debug, debugging, ownership, and problem-solving skills, Excellent verbal and written communication skills
Nice to Have
Experience with scan compression and advanced scan architectures, Post-silicon experience, including: Pattern bring-up and debug, Silicon characterization and yield learning, Experience mentoring junior engineers or owning DFT scan signoff
What You'll Do.
Lead hands-on scan DFT implementation
Scan insertion and stitching
Scan Streaming Network (SSN) implementation
IJTAG (IEEE 1687) insertion and connectivity
Perform scan DFT verification
Debug and resolve scan-related DRCs
and control signal problems
and debug SpyGlass DFT/RTL checks
and debug ATPG scan patterns
Analyze ATPG results and drive scan coverage improvement and closure
Develop and validate DFT-related timing constraints
Create and maintain TCL scripts for scan insertion
and coverage analysis
Optimize scan implementations for pattern efficiency and test quality
Support hierarchical scan integration at both block and SoC levels
Support pre-silicon DFT signoff and post-silicon pattern bring-up and debug
Assist with ATE pattern conversion and scan debug activities
How You'll Work.
Team & Collaboration
partnering with design teams to resolve violations; Collaborate closely with RTL and Physical Design teams to resolve scan-related issues
Communication Scope
Excellent verbal and written communication skills
Process & Methodology
ownership
Full Job Description
**About Marvell** Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. **Your Team, Your Impact** CAI Req ID:268 **What You Can Expect** We are looking for a **Senior****Staff DFT Engineer** with **hands-on experience** in scan-based DFT implementation, including **Scan Streaming Network (SSN)** and **IJTAG (IEEE 1687)**. This role focuses on **end-to-end scan execution** , from insertion and verification through DRC closure, coverage improvement, and final DFT signoff. The ideal candidate will own **scan quality, coverage closure, and DFT signoff** for complex SoC designs. **_ESSENTIAL DUTIES AND RESPONSIBILITIES_** * Lead hands-on **scan DFT implementation** , including: * Scan insertion and stitching * Scan Streaming Network (SSN) implementation * IJTAG (IEEE 1687) insertion and connectivity * Perform **scan DFT verification** , debug, and DFT DRC closure * Debug and resolve scan-related **DRCs, connectivity issues, and control signal problems** * Run, analyze, and debug **SpyGlass DFT/RTL checks** , partnering with design teams to resolve violations * Generate, simulate, and debug **ATPG scan patterns** * Analyze ATPG results and drive **scan coverage improvement and closure** * Develop and validate **DFT-related timing constraints** (scan, shift, capture, and test modes) * Create and maintain **TCL scripts** for scan insertion, ATPG setup, and coverage analysis * Optimize scan implementations for **pattern efficiency and test quality** * Support **hierarchical scan integration** a
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