Marvell
semiconductor
AnalogDesignEngineer,Principal
Neural analysis suggests this role is
optimal for Principal candidates.
“Analog Design Engineer, Principal at Marvell. Skills: Analog Design, High-speed optical transceivers, IC design. Designing circuits used for high-speed optical transceivers. Analyze block specifications and select appropriate topologies”
Industry & Context.
solving technical challenges
Access to technology and/or software subject to U. S. export control laws and regulations, including the Export Administration Regulations (EAR), Eligible to access export-controlled information as defined under applicable law, May be required to obtain export licensing approval from the U. S. Department of Commerce and/or the U. S. Department of State, May be subject to an export license review process prior to employment
What They're Looking For.
Must Have
Master’s degree in Electrical Engineering (preferably with a specialization in Microelectronics) or a related field, with 10+ years of relevant work experience OR PhD in Electrical Engineering (preferably with a specialization in microelectronics) or a related field, with 7+ years of relevant work experience, Proven experience in independently designing ICs, from architecture definition to lab characterization, with full macro/IP ownership, Solid proficiency in analog design, preferably in the multi-GHz range, Extensive experience in performing or supervising analog custom layout, Proficiency in both spoken and written Italian and English (minimum B2 level)
Nice to Have
Direct project experience in at least one of the following is a plus: Multi-Gbps electrical SerDes or electro-optical transceivers OR advanced CMOS nodes, including FinFET technologies
What You'll Do.
Designing circuits used for high-speed optical transceivers
Analyze block specifications and select appropriate topologies
Design analog blocks at the transistor level
Supervise layout activities
and conduct post-layout verifications
Model blocks and validate models
Take responsibility for designing entire analog macros or IPs
How You'll Work.
Team & Collaboration
Collaborate with the team on next-gen high-speed optical transceivers; Collaborate with other teams to enhance existing solutions; Participate in cross-functional meetings and interact with other functions
Communication Scope
communication; presentation
Full Job Description
**About Marvell** Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. **Your Team, Your Impact** The Central Engineering - Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro, and datacenter. We address the bandwidth, capacity, and power issues faced by cloud computing, mega data centers that power the social media giant platforms. Our innovative approaches have resulted in the company’s products being first to market in many of the key areas, developing the most advanced chips and subsystem solutions to address the ever-increasing demand for higher data rates driven by video-on-demand, gaming, and other real-time data streams. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity. As a member of a dynamic CE-OPHY team, the candidate will be responsible for designing circuits used for high-speed optical transceivers. The member will have an opportunity to work on a deep submicron process and collaborate with the team on next-gen high-speed optical transceivers. **What You Can Expect** * Analyze block specifications and select appropriate topologies. * Design analog blocks at the transistor level. * Supervise layout activities, provide guidelines, and conduct post-layout verifications. * Model blocks and validate models. * Collaborate with other tea
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