Marvell
Semiconductor
SeniorStaffEngineer,ASIC/VLSISynthesisandDesign
“Senior Staff Engineer, ASIC/VLSI Synthesis and Design at Marvell. Skills: ASIC Synthesis, VLSI Design, Timing Closure, Front-End Implementation. Develop and validate timing constraints. Analyze timing complexities”
What You'll Achieve.
meeting performance, power and area goals
Industry & Context.
problem-solving skills; analyze and debug complex issues
access to technology and/or software subject to U. S. export control laws and regulations, eligible to access export-controlled information, export license review process prior to employment
What They're Looking For.
Must Have
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience, Minimum of 5 years of industry experience in ASIC implementation and synthesis, understanding of ASIC design flows, from RTL to GDSII, Knowledge and hands-on experience with synthesis and STA methodologies and implementation, Proficiency in using synthesis tools, STA tools, and scripting languages (e. g. , Tcl, Perl), Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5, understanding of timing constraint development for hierarchical designs, Experience doing functional ECOs using industry standard tools and flows like Conformal ECO, Experience with UPF development for blocks and SoCs, UPF validation using tools like Conformal Low Power (CLP), Familiarity with physical design and timing optimization techniques and strategies to achieve timing closure, Proven track record of delivering successful designs on time and meeting performance, power and area goals, Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues, communication and collaboration skills to work effectively within cross-functional teams
Nice to Have
experience with deep technology nodes such as 5nm/4nm
What You'll Do.
Develop and validate timing constraints
Analyze timing complexities
Develop consolidated timing modes
Own and contribute to Front-End Implementation tasks
Analyze tradeoffs between power/performance/area
Perform Physical Aware Synthesis
Automate Front End Flows and processes
Ensure compliance with Netlist Handoff checklists
Document best practices and lessons learned
How You'll Work.
Team & Collaboration
Collaborate with Architecture, RTL, DFT, and Analog teams; work effectively within cross-functional teams
Communication Scope
communication skills; collaboration skills
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