Marvell
Semiconductor
SiliconValidationManager
Neural analysis suggests this role is
optimal for Manager candidates.
“Silicon Validation Manager at Marvell. Skills: Silicon Validation, PCIe, High-speed SERDES. Manage PHY and functional validation in post-silicon environment. Define validation/test plan”
Industry & Context.
Analytical skills; Problem-solving skills; Debug issues; Troubleshoot failing tests
What They're Looking For.
Must Have
Bachelor's degree in computer science, Electrical Engineering or related fields and 7+ years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience, 3+ years managerial experience in Silicon Validation, understanding of high-speed SERDES, equalization technique and PCIe, UALink and Ethernet protocols, 5+ years’ experience with High Speed IO testing, debugging and validation, lab skills with hands on experience, in system bring up, system testing and debug, In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.), analytical, problem-solving and communication skills
Nice to Have
Working knowledge of PCIe interface and characterization, Working knowledge and experience on Ethernet and/or UALink is a definite plus, Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset, Working knowledge of board able to read board schematics and board layout, Knowledge in SERDES modeling techniques, Working experience with Python
What You'll Do.
Manage PHY and functional validation in post-silicon environment
Define validation/test plan
Document validation/test plan
Execute validation/test plan
Report validation/test plan
Perform lab-based silicon bring-up
Perform high speed signal validation
Analyze high speed signal
Analyze and debug issues on PHY protocol
Troubleshoot failing tests with diagnostics
Lead collaborative technical discussions
Drive resolution on technical issues
Work with cross-functional teams
Work with external vendors
Debug post-silicon issues
Debug customer issues
How You'll Work.
Team & Collaboration
Cross-functional teams; External vendors
Communication Scope
Technical discussions
Full Job Description
**About Marvell** Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. **Your Team, Your Impact** As a Silicon Validation Manager at Marvell, you’ll be helping to deliver high bandwidth devices within the rack. The team you manage performs Silicon validation on leading edge switch devices. Products use advanced Si technology nodes and advanced packaging, delivering the highest performance products in the datacenter market. **What You Can Expect** * Complete responsibility for management of PHY and functional Validation in post-silicon environment. * Defining, documenting, executing, and reporting the overall validation/test plan for Marvell switch devices * Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack. * Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER. * Analyze and debug issues on PHY protocol of storage interface (PCIe, UALink, Ethernet) * Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers. * Leading collaborative technical discussions to drive resolution on technical issues. Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe PHY. * Work closely with Si design engineering, SW engineering, and customers to address design issues and debug
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