{ "count" : 101097, "data" : [ { "id" : "6a3092acf292fd229c0c3aef", "title" : "Senior Engineer, ASIC development Engineering (ASIC, SOC Validation)", "company" : "Sandisk", "industry" : "Computer Hardware", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior ASIC Development Engineers in Bengaluru, India, adjusted for industry and seniority." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-16T13:08:28.814", "fingerprint" : "c147f099a5887f0664c1e1fc1db50da2c6f2d8e0facd8e79e15ce4813efedf3d", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000132211732-senior-engineer-asic-development-engineering-asic-soc-validation-with-3-to-5-years-of-experience", "externalId" : "744000132211732", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", 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verification, Apply assertion-based verification", "teamCollaboration" : "Cross-functional teams", "domainKnowledge" : "SoC designs; Data storage control SoCs; Digital world; Flash memory; Advanced memory technologies; 4IR innovations; Digital world; Data storage solutions; Next-generation data solutions; Storage solutions; Industry-standard protocols; SoC verification environments; SoC-level testbenches; Pre-/post-silicon phases; Datapath flows; Post-silicon ASIC; Hardware Abstraction Layer; SoC-level validation; SoC-level verification; Multiple domains; Low-power; DFT; Power-aware validation; ATE functional patterns; Performance bottlenecks; Traffic generation; Corner-case stress scenarios; Verification methodologies", "domainList" : [ "soc-designs", "data-storage-control-socs", "digital-world", "flash-memory", "advanced-memory-technologies", "4ir-innovations", "data-storage-solutions", "next-generation-data-solutions", "storage-solutions", "industry-standard-protocols", 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"Performance bottlenecks", "Traffic generation", "Corner-case stress scenarios", "Verification methodologies" ], "toolProficiency" : [ "Palladiumulation" ], "innovationCreativity" : "Relentlessly innovate; Groundbreaking innovations; Pushing possibility forward; Driving innovation", "problemSolvingSkills" : "Debugging; Root cause analysis", "qualificationsBasic" : "BE or MS degree in Electrical Engineering or Computer Engineering, 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up, Deep understanding of C, embedded programming, and hardware/software co-validation methodologies, Knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts, Proven history of developing and executing verification and validation strategies for complex SoCs, End-to-end ownership of one or more subsystems or SoC verification and validation flows, Experience in verification and validation of industry-standard protocols, Run complex SoC verification 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With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. As a SoC Validation/Verification Engineer, you will play a key role in ensuring the quality and reliability of our SoC designs. You will be responsible for: * Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation. * Independently developing and executing tests for verification and validation. * Collaborating with cross-functional teams to drive closure of verification and validation activities. * Signing off on verification and validation deliverables. * Debugging and root cause analysis of issues found during validation. * Developing and maintaining automated test environments and regression suites. * Contributing to the continuous improvement of verification methodologies and best practices. Your work will enable industry-leading data storage control SoCs that are deployed in high-volume consumer and enterprise products. Why Join Us? At SanDisk, you’ll be part of a team of highly skilled engineers solving complex verification challenges and driving innovation in data storage solutions. Your work will directly impact the performance and reliability of next-generation data solutions for both consumer and enterprise markets. Together, we’ll push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions. ## Qualifications Qualifications: Required: * BE or MS degree in Electrical Engineering or Computer Engineering, with 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up. * Deep understanding of C, embedded programming, and hardware/software co-validation methodologies. * Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts. * Proven history of developing and executing verification and validation strategies for complex SoCs. Essential Duties and Responsibilities * Ownership: End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure. * Protocol Expertise: Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB. * Emulation Experience: Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage. * Testbench Proficiency: Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components. * Simulation & Debug: Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis. * Pre-/Post-Silicon Validation: Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases. * Datapath Validation: Ability to understand and validate complex datapath flows of the controller, create datapath scenarios in SoC verification environments, and port them across pre-silicon and post-silicon environments. * Post-Silicon Experience: Hands-on experience in post-silicon ASIC bring-up, validation, and debug. * Firmware & HAL Development: Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code to enable datapath, integration, and SoC-level validation and verification. * Language Proficiency: Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development * Validation Infrastructure: Build and maintain validation infrastructure, including test content, regression automation, and lab equipment integration (oscilloscopes, analyzers, logic probes). * Debug Expertise: Proficiency in debugging SoC issues across multiple domains (digital logic, firmware, timing, low-power, DFT) using JTAG, trace, waveform capture, and performance counters. * Power & GLS Validation: Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns. * Performance & Stress Testing: Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios at the SoC level. * Verification Methodology: Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification to ensure design quality and completeness. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Senior Engineer, ASIC development Engineering (ASIC, SOC Validation) at Sandisk. Skills: SoC Validation, ASIC Development, Verification Planning, Test Environment Development. Understand complex ASIC specifications. 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"industry" : "Computer Hardware", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior ASIC Development Engineers in Bengaluru, India, adjusted for industry and seniority." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-16T11:51:51.039", "fingerprint" : "1c70e5a556fb053442b350f3c7129e251e686aafac4f20b2bb76601699e1a598", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000132211732-senior-engineer-asic-development-engineering-asic-soc-validation-with-3-to-5-years-of-experience", "externalId" : "744000132211732", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "C, SystemVerilog, UVM, Python, Perl, AXI, AHB, APB, UPF, CPF", "professionalSkills" : [ "Root cause analysis", "System design" ], "hardSkillsList" : [ "Embedded programming", "Hardware/software co-validation", "SoC verification", "SoC validation", "ASIC bring-up", "Post-silicon validation", "Firmware development", "HAL development", "Validation infrastructure", "Gate-level simulations", "Power-aware validation", "ATE functional patterns", "Performance testing", "Stress testing", "Constrained-random verification", "Coverage-driven verification", "Assertion-based verification" ], "hardSkills" : [ { "name" : "Embedded programming", "level" : "intermediate" }, { "name" : "Hardware/software co-validation", "level" : "intermediate" }, { "name" : "SoC verification", "level" : "intermediate" }, { "name" : "SoC validation", "level" : "intermediate" }, { "name" : "ASIC bring-up", "level" : "intermediate" }, { "name" : "Post-silicon validation", "level" : "intermediate" }, { "name" : "Firmware development", "level" : "intermediate" }, { "name" : "HAL development", "level" : "intermediate" }, { "name" : "Validation infrastructure", "level" : "intermediate" }, { "name" : "Gate-level simulations", "level" : "intermediate" }, { "name" : "Power-aware validation", "level" : "intermediate" }, { "name" : "ATE functional patterns", "level" : "intermediate" }, { "name" : "Performance testing", "level" : "intermediate" }, { "name" : "Stress testing", "level" : "intermediate" }, { "name" : "Constrained-random verification", "level" : "intermediate" }, { "name" : "Coverage-driven verification", "level" : "intermediate" }, { "name" : "Assertion-based verification", "level" : "intermediate" } ], "majorSkills" : "SoC Validation, ASIC Development, Verification Planning, Test Environment Development", "majorSkillsList" : [ "SoC Validation", "ASIC Development", "Verification Planning", "Test Environment Development" ], "coreResponsibilities" : "Understand complex ASIC specifications, Create comprehensive Verification/Validation plans, Independently develop and execute tests, Collaborate with cross-functional teams, Drive closure of verification and validation activities, Sign off on verification and validation deliverables, Debug and root cause analysis of issues, Develop and maintain automated test environments, Develop and maintain regression suites, Contribute to continuous improvement of verification methodologies, Contribute to best practices, Enable industry-leading data storage control SoCs, Plan verification and validation flows, Execute verification and validation flows, Close verification and validation flows, Verify industry-standard protocols, Validate industry-standard protocols, Run verification scenarios on Palladiumulation platforms, Accelerate debug on Palladiumulation platforms, Improve pre-silicon coverage on Palladiumulation platforms, Contribute to SoC-level testbenches, Perform initial debug, Perform root cause analysis, Validate complex datapath flows, Create datapath scenarios, Port datapath scenarios, Enable datapath validation, Enable integration validation, Enable SoC-level validation, Develop firmware, Develop bare-metal tests, Develop Hardware Abstraction Layer (HAL) code, Build validation infrastructure, Maintain validation infrastructure, Integrate lab equipment, Debug SoC issues, Debug digital logic issues, Debug firmware issues, Debug timing issues, Debug low-power issues, Debug DFT issues, Use JTAG for debugging, Use trace for debugging, Use waveform capture for debugging, Use performance counters for debugging, Run gate-level simulations, Debug gate-level simulations, Run power-aware validation, Debug power-aware validation, Validate ATE functional patterns, Validate performance bottlenecks, Validate traffic generation, Validate corner-case stress scenarios, Apply constrained-random verification, Apply coverage-driven verification, Apply assertion-based verification", "teamCollaboration" : "Cross-functional teams", "domainKnowledge" : "SoC designs; Data storage; Flash memory; Advanced memory technologies; Industry-standard protocols; DDR; PCIe; LPDDR; USB; Ethernet; I²C; I3C; SPI; Datapath flows; Low-power design; DFT; Power-aware design", "domainList" : [ "soc-designs", "data-storage", "flash-memory", "advanced-memory-technologies", "industry-standard-protocols", "ddr", "pcie", "lpddr", "usb", "ethernet", "i-c", "i3c", "spi", "datapath-flows", "low-power-design", "dft", "power-aware-design" ], "domainSpecificKnowledge" : [ "SoC designs", "Data storage", "Flash memory", "Advanced memory technologies", "Industry-standard protocols", "DDR", "PCIe", "LPDDR", "USB", "Ethernet", "I²C", "I3C", "SPI", "Datapath flows", "Low-power design", "DFT", "Power-aware design" ], "toolProficiency" : [ "Palladiumulation" ], "problemSolvingSkills" : "Debugging; Root cause analysis", "qualificationsBasic" : "BE or MS degree in Electrical Engineering or Computer Engineering, 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up, Deep understanding of C, embedded programming, and hardware/software co-validation methodologies, Knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts, Proven history of developing and executing verification and validation strategies for complex SoCs, End-to-end ownership of one or more subsystems or SoC verification and validation flows, Experience in verification and validation of industry-standard protocols, Run complex SoC verification and validation scenarios on Palladiumulation platforms, Understand and contribute to complex SoC-level testbenches, Execute verification and validation cases in simulation environments, Experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug, Ability to understand and validate complex datapath flows, Hands-on experience in post-silicon ASIC bring-up, validation, and debug, Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code, Build and maintain validation infrastructure, Proficiency in debugging SoC issues across multiple domains, Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns, Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios, Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification", "qualificationsPreferred" : "Experience with Python or Perl scripting languages", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. As a SoC Validation/Verification Engineer, you will play a key role in ensuring the quality and reliability of our SoC designs. You will be responsible for: * Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation. * Independently developing and executing tests for verification and validation. * Collaborating with cross-functional teams to drive closure of verification and validation activities. * Signing off on verification and validation deliverables. * Debugging and root cause analysis of issues found during validation. * Developing and maintaining automated test environments and regression suites. * Contributing to the continuous improvement of verification methodologies and best practices. Your work will enable industry-leading data storage control SoCs that are deployed in high-volume consumer and enterprise products. Why Join Us? At SanDisk, you’ll be part of a team of highly skilled engineers solving complex verification challenges and driving innovation in data storage solutions. Your work will directly impact the performance and reliability of next-generation data solutions for both consumer and enterprise markets. Together, we’ll push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions. ## Qualifications Qualifications: Required: * BE or MS degree in Electrical Engineering or Computer Engineering, with 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up. * Deep understanding of C, embedded programming, and hardware/software co-validation methodologies. * Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts. * Proven history of developing and executing verification and validation strategies for complex SoCs. Essential Duties and Responsibilities * Ownership: End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure. * Protocol Expertise: Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB. * Emulation Experience: Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage. * Testbench Proficiency: Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components. * Simulation & Debug: Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis. * Pre-/Post-Silicon Validation: Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases. * Datapath Validation: Ability to understand and validate complex datapath flows of the controller, create datapath scenarios in SoC verification environments, and port them across pre-silicon and post-silicon environments. * Post-Silicon Experience: Hands-on experience in post-silicon ASIC bring-up, validation, and debug. * Firmware & HAL Development: Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code to enable datapath, integration, and SoC-level validation and verification. * Language Proficiency: Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development * Validation Infrastructure: Build and maintain validation infrastructure, including test content, regression automation, and lab equipment integration (oscilloscopes, analyzers, logic probes). * Debug Expertise: Proficiency in debugging SoC issues across multiple domains (digital logic, firmware, timing, low-power, DFT) using JTAG, trace, waveform capture, and performance counters. * Power & GLS Validation: Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns. * Performance & Stress Testing: Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios at the SoC level. * Verification Methodology: Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification to ensure design quality and completeness. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Senior Engineer, ASIC development Engineering (ASIC, SOC Validation) at Sandisk. Skills: SoC Validation, ASIC Development, Verification Planning, Test Environment Development. Understand complex ASIC specifications. Create comprehensive Verification/Validation plans", "postedDate" : "2026-06-15T14:07:05.000", "createdAt" : "2026-06-16T01:41:33.626", "lastUpdated" : "2026-06-16T11:51:51.039", "ingestTimestamp" : "2026-06-16T01:41:33.626", "mongoId" : "6a3080e2f292fd229c068079", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Embedded programming", "Hardware/software co-validation", "SoC verification", "SoC validation", "ASIC bring-up", "Post-silicon validation", "Firmware development", "HAL development", "Validation infrastructure", "Gate-level simulations", "Power-aware validation", "ATE functional patterns", "Performance testing", "Stress testing", "Constrained-random verification", "Coverage-driven verification", "Assertion-based verification", "SoC Validation", "ASIC Development", "Verification Planning", "Test Environment Development", "Root cause analysis", "System design", "SoC designs", "Data storage", "Flash memory", "Advanced memory technologies", "Industry-standard protocols", "DDR", "PCIe", "LPDDR", "USB", "Ethernet", "I²C", "I3C", "SPI", "Datapath flows", "Low-power design", "DFT", "Power-aware design", "Palladiumulation" ], "skillCount" : 41, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a305b03f292fd229cf584e9", "title" : "Silicon Emulation Engineer", "company" : "Waymo", "industry" : "Technology", "salary" : { "min" : 175000.0, "max" : 215000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Mountain View, California, United States", "locations" : [ "Mountain View", "California", "United States" ], "timestamp" : "2026-06-16T07:21:35.569", "fingerprint" : "fd32fcc0842fd919e0180c0a7dbd6d78223e89d6761cd34e3cf329cc6e514780", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://careers.withwaymo.com/jobs?gh_jid=8004234", "externalId" : "8004234", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Mountain View", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "hybrid", "geo" : "37.3893889,-122.0832101" } ], "locationText" : "Mountain View, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "technicalSkills" : "SystemVerilog, C++, Python, TCL, QEMU, VirtualBox", "professionalSkills" : [ "System design", "Performance analysis", "Power analysis" ], "hardSkillsList" : [ "Hardware emulation", "Software development", "Testbench development", "Root cause analysis", "Infrastructure building", "Automation", "Regression testing", "Continuous integration", "Data analysis", "Bare metal programming", "Embedded systems", "Linux internals", "Operating systems", "Boot loaders", "Drivers", "Firmware" ], "hardSkills" : [ { "name" : "Hardware emulation", "level" : "intermediate" }, { "name" : "Software development", "level" : "intermediate" }, { "name" : "Testbench development", "level" : "intermediate" }, { "name" : "Root cause analysis", "level" : "intermediate" }, { "name" : "Infrastructure building", "level" : "intermediate" }, { "name" : "Automation", "level" : "intermediate" }, { "name" : "Regression testing", "level" : "intermediate" }, { "name" : "Continuous integration", "level" : "intermediate" }, { "name" : "Data analysis", "level" : "intermediate" }, { "name" : "Bare metal programming", "level" : "intermediate" }, { "name" : "Embedded systems", "level" : "intermediate" }, { "name" : "Linux internals", "level" : "intermediate" }, { "name" : "Operating systems", "level" : "intermediate" }, { "name" : "Boot loaders", "level" : "intermediate" }, { "name" : "Drivers", "level" : "intermediate" }, { "name" : "Firmware", "level" : "intermediate" } ], "majorSkills" : "Silicon emulation, Hardware/software debug, Testbench optimization", "majorSkillsList" : [ "Silicon emulation", "Hardware/software debug", "Testbench optimization" ], "coreResponsibilities" : "Collaborate with Design, Verification, Software teams, Simulate future silicon designs, Simulate software on emulation platform, Target functional validation, Target performance validation, Left-shift software development, Design emulation testbenches, Implement emulation testbenches, Optimize emulation testbenches, Write synthesizable transactors, Interact with emulated designs, Triage failures, Root-cause failures, Assist with post-silicon bring-up, Assist with debug, Assist with characterization, Build infrastructure for emulation users, Develop tools for model build, Develop tools for regression, Develop tools for automation, Develop tools for continuous integration, Develop tools for data analysis, Develop tools for training", "teamCollaboration" : "Design teams; Verification teams; Software teams; Silicon Engineering Lead", "domainKnowledge" : "Autonomous driving; Compute platforms; Automotive compute; Hardware/software co-design; Embedded systems; Linux internals; Operating systems; Bare metal programming", "domainList" : [ "autonomous-driving", "compute-platforms", "automotive-compute", "hardware-software-co-design", "embedded-systems", "linux-internals", "operating-systems", "bare-metal-programming" ], "domainSpecificKnowledge" : [ "Autonomous driving", "Compute platforms", "Automotive compute", "Hardware/software co-design", "Embedded systems", "Linux internals", "Operating systems", "Bare metal programming" ], "toolProficiency" : [ "Palladium", "Zebu", "Veloce", "Protium", "HAPS", "Trace32", "OpenOCD", "TARMAC" ], "problemSolvingSkills" : "Root-cause analysis; Debug; Problem-solving", "qualificationsBasic" : "BS degree in Computer Science / Electrical Engineering, 5 years of silicon development experience, Experience with major hardware emulation platform, High proficiency with emulation approaches, Experience with SystemVerilog, Experience with design verification methodologies, Programming and scripting for automation, Debug and problem-solving ability", "qualificationsPreferred" : "Experience with AXI/AMBA, Experience with PCIe, Experience with DRAM, Experience with Ethernet interfaces, Performance and power analysis techniques, Experience with JTAG, Experience with DFT, Experience with UART, Experience with SPI, Experience with GPIO, Experience with test/low-speed interfaces, Knowledge of advanced design verification methods, Post-silicon debug software experience, Lab bench tools experience, Understanding of bare metal programming, Understanding of embedded systems, Understanding of Linux internals, Understanding of operating systems, Understanding of boot loaders, Understanding of drivers, Understanding of firmware", "remoteFriendly" : true, "workSiteFlexibility" : "Hybrid", "rawDescription" : "Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U. S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle’s software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world’s highest performance automotive compute platforms. This role follows a hybrid work schedule and you will report to a Silicon Engineering Lead. You will: Collaborate with the Design, Verification, and Software teams to simulate future silicon designs and software on an emulation platform, targeting functional and performance validation and left-shift of software development Design, implement, and optimize emulation testbenches, balancing performance and debug capabilities based on user needs and hardware constraints Write end-to-end synthesizable transactors to interact with emulated designs through software APIs and C-DPI Triage and root-cause failures alongside emulation users, leveraging waveforms, software logging, and custom-built emulation monitors Assist with post-silicon bring-up, debug, and characterization Build infrastructure to support the emulation user base, including tools for model build, regression, automation, continuous integration, data analysis, and training You have: BS degree in Computer Science / Electrical Engineering or related field and 5 years of silicon development experience. Experience with at least one major hardware emulation platform (Palladium, Zebu, Veloce, Protium, HAPS). High level of proficiency with one or more of the following emulation approaches: virtual prototyping, testbench acceleration, hybrid emulation, in-circuit emulation (speed bridge), QEMU, or VirtualBox Experience with SystemVerilog and design verification methodologies Programming and scripting (C++, Python, or TCL) for automation, test development, debug flows, and release process. Strong debug and problem-solving ability across hardware and software We prefer: Experience with AXI/AMBA, PCIe, DRAM, and Ethernet interfaces Performance and power analysis techniques Experience with JTAG, DFT, UART, SPI, GPIO and other test/low-speed interfaces Knowledge of advanced design verification methods (coverage, gate-level simulation, assertions, and UVM). Post-silicon debug software (e. g. Trace32, OpenOCD, TARMAC) and lab bench tools (analyzers, scopes, meters) Understanding of bare metal programming, embedded systems, Linux internals, operating systems, boot loaders, drivers, and firmware The expected base salary range for this full-time position across US locations is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Your recruiter can share more about the specific salary range for the role location or, if the role can be performed remote, the specific salary range for your preferred location, during the hiring process. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range $175,000—$215,000 USD", "summaryDescription" : "Silicon Emulation Engineer at Waymo. Skills: Silicon emulation, Hardware/software debug, Testbench optimization. Collaborate with Design, Verification, Software teams. Simulate future silicon designs", "postedDate" : "2026-06-15T23:20:52.716", "createdAt" : "2026-06-15T23:20:52.716", "lastUpdated" : "2026-06-16T07:21:35.569", "ingestTimestamp" : "2026-06-15T23:20:52.716", "mongoId" : "6a305b03f292fd229cf584e9", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 175000, "salaryAnnualMax" : 215000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Hardware emulation", "Software development", "Testbench development", "Root cause analysis", "Infrastructure building", "Automation", "Regression testing", "Continuous integration", "Data analysis", "Bare metal programming", "Embedded systems", "Linux internals", "Operating systems", "Boot loaders", "Drivers", "Firmware", "Silicon emulation", "Hardware/software debug", "Testbench optimization", "System design", "Performance analysis", "Power analysis", "Autonomous driving", "Compute platforms", "Automotive compute", "Hardware/software co-design", "Palladium", "Zebu", "Veloce", "Protium", "HAPS", "Trace32", "OpenOCD", "TARMAC" ], "skillCount" : 34, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2d6c5874d8ee00a0bdce15", "title" : "Staff Engineer, ASIC Development Engineering", "company" : "Sandisk", "industry" : "Computer Hardware", "salary" : { "min" : 4500000.0, "max" : 7000000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Staff Engineer in Bengaluru, India, adjusted for lead seniority and technology industry." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-15T08:24:35.344", "fingerprint" : "254b7e1470a08195ff1aefe2d91409638815821adad19d00ca862ad250a43ae7", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000131871219-staff-engineer-asic-development-engineering", "externalId" : "744000131871219", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "Static Timing Analysis, Digital design, Physical design, Semiconductor fabrication", "professionalSkills" : [ "Timing closure", "Synthesis report analysis", "Constraints development", "Methodology development", "Cross-functional collaboration", "Process improvement", "Strategic vision" ], "hardSkillsList" : [ "Static Timing Analysis", "Timing analysis", "Critical path identification", "Timing violation mitigation" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Static Timing Analysis", "level" : "intermediate" }, { "name" : "Timing analysis", "level" : "intermediate" }, { "name" : "Critical path identification", "level" : "intermediate" }, { "name" : "Timing violation mitigation", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "Static Timing Analysis, Timing closure, STA methodologies", "majorSkillsList" : [ "Static Timing Analysis", "Timing closure", "STA methodologies" ], "coreResponsibilities" : "Own Subsystem level STA, Provide direction to PnR team, Analyze Synthesis report, Work with IP & Design team, Develop Timing constraints, Review Timing constraints, Develop and implement advanced STA methodologies, Meet timing closure requirements, Collaborate with cross-functional teams, Ensure seamless integration, Optimize timing performance, Drive development of STA scripts, Automate timing analysis processes, Streamline timing analysis processes, Conduct thorough timing analysis, Identify critical paths, Develop strategies to mitigate timing violations, Improve design performance, Stay abreast of industry trends, Incorporate best practices, Prepare detailed timing reports, Present technical documentation, Foster a culture of innovation, Foster a culture of collaboration, Foster a culture of continuous improvement", "teamCollaboration" : "Cross-functional teams; Design team; Verification team; Physical design team; DFT team; IP team", "domainKnowledge" : "Semiconductor design; Static Timing Analysis", "domainList" : [ "semiconductor-design", "static-timing-analysis" ], "domainSpecificKnowledge" : [ "Semiconductor design", "Static Timing Analysis" ], "toolProficiency" : [ "Synopsys PrimeTime", "Cadence Tempus", "Constraints Manager" ], "communicationSkills" : "Technical documentation; Timing reports", "documentationSkills" : "Technical documentation", "innovationCreativity" : "Innovation", "problemSolvingSkills" : "Problem-solving; Analytical thinking", "outcomesObjectives" : "Meet timing closure requirements; Improve overall design performance", "qualificationsBasic" : "Bachelor's or Master's degree, 5 years of experience in Static Timing Analysis, Proven track record of successfully executing STA, In-depth knowledge of STA tools, Understanding of digital design principles, Excellent problem-solving skills, Exceptional communication and interpersonal skills, Ability to prioritize tasks, Proactive, results-oriented mindset", "qualificationsPreferred" : "Experience with advanced process nodes", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Position Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities: - Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Development & Review activities. - Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. - Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance. - Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. - Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance. - Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow. - Prepare and present detailed timing reports and technical documentation to stakeholders - Foster a culture of innovation, collaboration, and continuous improvement within the STA team. ## Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - A minimum of 5 years of experience in Static Timing Analysis. - Proven track record of successfully executing STA - In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies. - Strong understanding of digital design principles, physical design, and semiconductor fabrication processes. - Excellent problem-solving skills and the ability to think strategically and analytically. - Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders. - Ability to prioritize tasks and manage multiple project work simultaneously. - A proactive, results-oriented mindset with a passion for innovation and continuous improvement. - Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying", "summaryDescription" : "Staff Engineer, ASIC Development Engineering at Sandisk. Skills: Static Timing Analysis, Timing closure, STA methodologies. Own Subsystem level STA. Provide direction to PnR team", "postedDate" : "2026-06-12T10:49:22.000", "createdAt" : "2026-06-14T01:34:54.291", "lastUpdated" : "2026-06-15T08:24:35.344", "ingestTimestamp" : "2026-06-14T01:34:54.291", "mongoId" : "6a2d6c5874d8ee00a0bdce15", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Static Timing Analysis", "Timing analysis", "Critical path identification", "Timing violation mitigation", "Leadership", "Timing closure", "STA methodologies", "Synthesis report analysis", "Constraints development", "Methodology development", "Cross-functional collaboration", "Process improvement", "Strategic vision", "Semiconductor design", "Synopsys PrimeTime", "Cadence Tempus", "Constraints Manager" ], "skillCount" : 17, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 1.0, "daysOld" : 2, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2a688674d8ee00a06347a0", "title" : "SR Engineer, ASIC DFT", "company" : "Micron Technology", "industry" : "Technology", "salary" : { "min" : 2250000.0, "max" : 3500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Senior ASIC DFT Engineer in Hyderabad, India, adjusted for Micron Technology's size and industry, reflecting 2024-2025 data." }, "location" : "Hyderabad - Phoenix Aquila, India", "locations" : [ "Hyderabad - Phoenix Aquila, India" ], "timestamp" : "2026-06-12T20:00:11.877", "fingerprint" : "bae2e6dacd5184c9adde615b8fa7cc5cd691d060b365d66353bfa9d7bed83725", "source" : "workday", "language" : "en", "applyUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/SR-Engineer--ASIC-DFT_JR96815", "externalId" : "JR96815", "industryFunction" : { }, "locationPoint" : "17.38405,78.45636", "structuredLocations" : [ { "city" : "Hyderabad", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "17.3605890,78.4740613" }, { "city" : "Bangalore", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Hyderabad, India; Bangalore, India", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Verilog, VHDL, C/C++, TCL, Perl, Python, Scan Codec, Memory BIST, Logic BIST, ATPG, BSCAN, JTAG, Fault Simulation, Scan Diagnosis, Memory Diagnosis", "professionalSkills" : [ "DFT implementation", "SOC design", "Gate level verification", "Silicon bring-up", "Characterization", "Methodology development" ], "hardSkillsList" : [ "Scan Codec insertion", "Memory BIST", "Logic BIST", "ATPG", "BSCAN", "JTAG", "Fault Simulation", "ATPG Fault models", "Scan Diagnosis", "Memory Diagnosis", "Hierarchical Scan implementations", "Core wrapping concepts", "Multi-clock domains", "Low power design" ], "hardSkills" : [ { "name" : "Scan Codec insertion", "level" : "intermediate" }, { "name" : "Memory BIST", "level" : "intermediate" }, { "name" : "Logic BIST", "level" : "intermediate" }, { "name" : "ATPG", "level" : "intermediate" }, { "name" : "BSCAN", "level" : "intermediate" }, { "name" : "JTAG", "level" : "intermediate" }, { "name" : "Fault Simulation", "level" : "intermediate" }, { "name" : "ATPG Fault models", "level" : "intermediate" }, { "name" : "Scan Diagnosis", "level" : "intermediate" }, { "name" : "Memory Diagnosis", "level" : "intermediate" }, { "name" : "Hierarchical Scan implementations", "level" : "intermediate" }, { "name" : "Core wrapping concepts", "level" : "intermediate" }, { "name" : "Multi-clock domains", "level" : "intermediate" }, { "name" : "Low power design", "level" : "intermediate" } ], "majorSkills" : "ASIC DFT, SOC DFT, ATPG, Memory BIST", "majorSkillsList" : [ "ASIC DFT", "SOC DFT", "ATPG", "Memory BIST" ], "coreResponsibilities" : "Implement DFT for Micron IPs, Implement DFT for Memory controllers, Ensure best quality products, Achieve lowest DPPM numbers, Support early analysis to Silicon bring-up, Support Silicon bring-up and Characterization, Implement innovative DFT, Generate ATPG patterns, Validate ATPG patterns, Validate DFT implementation, Work with Multi-functional Teams, Support Silicon bring up activities, Guarantee stability of test patterns/program, Chip in to DFT methodology development", "teamCollaboration" : "Design team; DV team; Physical Implementation team; Test Engineering; Product Engineering; Multi-functional Teams", "domainKnowledge" : "Storage products; SOC; ASIC DFT; Memory controllers; IEEE 1149.1; IEEE 1687; IEEE 1149.6; IEEE 1500; IEEE 1838; SSN; 2.5D IC; 3D IC", "domainList" : [ "storage-products", "soc", "asic-dft", "memory-controllers", "ieee-1149-1", "ieee-1687", "ieee-1149-6", "ieee-1500", "ieee-1838", "ssn", "2-5d-ic", "3d-ic" ], "domainSpecificKnowledge" : [ "Storage products", "SOC", "ASIC DFT", "Memory controllers", "IEEE 1149.1", "IEEE 1687", "IEEE 1149.6", "IEEE 1500", "IEEE 1838", "SSN", "2.5D IC", "3D IC" ], "toolProficiency" : [ "Siemens Cad tools", "Synopsys Cad tools", "Cadence Cad tools" ], "innovationCreativity" : "Innovation", "problemSolvingSkills" : "Diagnosis", "outcomesObjectives" : "Achieve lowest DPPM numbers", "qualificationsBasic" : "Bachelor’s or Master’s Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field, 5+ years of industry experience, Shown ability in DFT of highly sophisticated SOCs, Core skills include Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG (IEEE1149. 1 & IEEE1687), Fault Simulation, ATPG Fault models(SAF, TDF, SDD, PDT etc), SDF annotated gate level verification, Scan and Memory Diagnosis, Experience with Siemens, Synopsys and/or Cadence Cad tools, Experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python", "qualificationsPreferred" : "Knowledge of IEEE 1149. 6, 1500 and 1838, Good experience on Hierarchical Scan implementations with core wrapping concepts, Experience in handling multi-clock domains and low power design implementation, Knowledge/Experience on SSN, 2. 5D or 3D IC DFT implementation", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is awarded as a Great Place to Work! We focus on innovation through Integrity and inclusion. We are proud to have a set of core values(People, Innovation, Tenacity, Collaboration and Customer Focus) which is reflected in our culture! Micron is a diverse organization of dedicated and innovative individuals, and we provide equal opportunities to all. At Micron, we don't discriminate on the basis of race, color, religion, gender, sexual orientation, disability, identity, national origin, or status as a protected veteran. As a Micron's ASIC DFT team we implement DFT for Micron IPs and Memory controllers(SOC) developed for different type of Storage products in Micron. We are using the best in class DFT methodologies and process technologies to ensure that we deliver the best quality products to achieve the lowest DPPM numbers. We work closely with Design(RTL), DV, Physical Implementation team, Test Engineering and Product Engineering team to support early analysis to the Silicon bring-up and Characterization. ## **Required Skills and Experience :** Bachelor’s or Master’s Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field. The role of Senior DFT engineer require 5+ years of industry experience with shown ability in DFT of highly sophisticated SOCs : * Core skills include Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG (IEEE1149.1 & IEEE1687), Fault Simulation, ATPG Fault models(SAF, TDF, SDD, PDT etc), SDF annotated gate level verification, Scan and Memory Diagnosis. * Must have experience with Siemens, Synopsys and/or Cadence Cad tools. * Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python. **Responsibilities -** * Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level. * Generate and validate ATPG patterns using simulations. * Shall Validate the DFT implementation using RTL and Gate level simulation. * Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation. * Support the Silicon bring up activities to guarantee the highest stability of the test patterns/program. * Chip in to the overall DFT methodology development. **Nice to have Skills/Experience :-** * Shall have Knowledge of IEEE 1149.6, 1500 and 1838. * Good experience on Hierarchical Scan implementations with core wrapping concepts * Experience in handling multi-clock domains and low power design implementation. * Knowledge/Experience on SSN, 2.5D or 3D IC DFT implementation. * Communicate effusively with multi-functional functional teams in different geographies and time Zones. * Time management and multi-tasking skills. ## Job Location: You will be joining part of growing team in Hyderabad or Bangalore. We value People and our dedication is to reward people with multiple Micron benefits that include PTO and medical benefits to name the few. **About Micron Technology, Inc.** We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life _for all_. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact [hrsupport_india@micron.com](mailto:hrsupport_in@micron.com) Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "summaryDescription" : "SR Engineer, ASIC DFT at Micron Technology. Skills: ASIC DFT, SOC DFT, ATPG, Memory BIST. Implement DFT for Micron IPs. Implement DFT for Memory controllers", "postedDate" : "2026-06-10T15:49:56.867", "createdAt" : "2026-06-11T15:49:56.744", "lastUpdated" : "2026-06-12T20:00:11.877", "ingestTimestamp" : "2026-06-11T15:49:56.744", "mongoId" : "6a2a688674d8ee00a06347a0", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/SR-Engineer--ASIC-DFT_JR96815", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Scan Codec insertion", "Memory BIST", "Logic BIST", "ATPG", "BSCAN", "JTAG", "Fault Simulation", "ATPG Fault models", "Scan Diagnosis", "Memory Diagnosis", "Hierarchical Scan implementations", "Core wrapping concepts", "Multi-clock domains", "Low power design", "ASIC DFT", "SOC DFT", "DFT implementation", "SOC design", "Gate level verification", "Silicon bring-up", "Characterization", "Methodology development", "Storage products", "SOC", "Memory controllers", "IEEE 1149.1", "IEEE 1687", "IEEE 1149.6", "IEEE 1500", "IEEE 1838", "SSN", "2.5D IC", "3D IC", "Siemens Cad tools", "Synopsys Cad tools", "Cadence Cad tools" ], "skillCount" : 36, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "daysOld" : 2, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2d6c5874d8ee00a0bdce1f", "title" : "Staff Engineer, ASIC Development Engineering", "company" : "Sandisk", "industry" : "Computer Hardware", "salary" : { "min" : 3500000.0, "max" : 5500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Lead Staff Engineer in the Technology industry in Bengaluru, India, adjusted for seniority and company size." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-16T02:21:53.400", "fingerprint" : "9ca58f5b6edd1e29afb425e5613ac1f7e2ba95b7b4a0655e37bad9210888e525", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000131701914-staff-engineer-asic-development-engineering", "externalId" : "744000131701914", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 0, "experienceMaxYears" : 2, "experienceLevel" : "entry", "technicalSkills" : "SystemVerilog, UVM, Python, TCL, PERL, Linux, Unix, Shell scripting", "professionalSkills" : [ "Technical leadership", "Verification technology", "Emulation technology", "Automation skills", "Problem-solving skills", "Cross-Functional Collaboration" ], "hardSkillsList" : [ "Emulation platforms", "HW/SW co-debug", "Verification methodologies", "Testplan creation", "Testbench architecture" ], "hardSkills" : [ { "name" : "Emulation platforms", "level" : "intermediate" }, { "name" : "HW/SW co-debug", "level" : "intermediate" }, { "name" : "Verification methodologies", "level" : "intermediate" }, { "name" : "Testplan creation", "level" : "intermediate" }, { "name" : "Testbench architecture", "level" : "intermediate" } ], "majorSkills" : "ASIC development, Emulation, Verification, Debugging", "majorSkillsList" : [ "ASIC development", "Emulation", "Verification", "Debugging" ], "coreResponsibilities" : "Provide technical leadership, Define requirements for Emulation, Define requirements for Emulation IP development, Partner with ASIC engineers, Deploy emulation acceleration, Deploy advanced verification environment configuration, Deploy advanced verification environment management, Deploy AI technology for verification, Deploy AI technology for emulation, Bridge gaps between Emulation IP feature set, Close gaps between Emulation IP feature set, Bridge gaps for Design IP verification, Close gaps for Design IP verification, Bridge gaps for DFT emulation acceleration, Close gaps for DFT emulation acceleration, Bridge gaps for UPF emulation acceleration, Close gaps for UPF emulation acceleration, Collaborate cross-functionally, Optimize verification workflows, Optimize emulation workflows, Standardize methodologies, Work with extended teams, Debug environment, Drive cross-functional testing, Triage failures with design teams, Triage failures with verification teams, Triage failures with firmware teams, Triage failures with software teams, Mentor junior engineers, Guide junior engineers, Foster a culture of collaboration, Foster a culture of innovation, Foster a culture of continuous improvement", "teamCollaboration" : "Cross-functional teams; Design teams; Validation teams; Firmware teams; Software teams", "domainKnowledge" : "ASIC development; Controller SoCs; DFT; UPF", "domainList" : [ "asic-development", "controller-socs", "dft", "upf" ], "domainSpecificKnowledge" : [ "ASIC development", "Controller SoCs", "DFT", "UPF" ], "toolProficiency" : [ "Veloce", "Zebu", "Palladium" ], "innovationCreativity" : "GenAI; AI technology", "problemSolvingSkills" : "Debugging; Problem-solving", "qualificationsBasic" : "6 to 9 years of experience, BE or MS degree in Electrical Engineering or Computer Engineering, Solid experience working on emulation platforms, Debugging experience is a must, Understanding of SystemVerilog UVM, Able to debug problems between verification and emulation, Programming and automation skills in Python, TCL and PERL, Working knowledge of Linux/Unix environment and shell scripting, Excellent debugging and problem-solving skills with simulation and emulation environments", "qualificationsPreferred" : "Experience with emulation acceleration, AI technology for verification and emulation", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. * The ASIC emulation team is seeking highly motivated engineer to join a team of experienced engineers working on the development of advanced controller SoCs. As a Technologist Emulation Engineer in the ASIC Emulation team, you will be responsible for enabling new emulation & verification technology for the larger ASIC team. This includes traditional verification technology that is now being accelerated by GenAI and accelerating verification of DFT and UPF with emulation. This unique position requires a mix of verification and emulation skills. The growing diversity of data creates an exponential number of new possibilities – for the world, our company, and you. You’ll be part of a team driving the innovations necessary to outpace new demands and challenges everywhere data lives, from sensors to mobile devices to the cloud. We’ve only started to scratch the surface of what data can do. You can help unlock its full potential. * Providing technical leadership and expertise to define requirements for Emulation and Emulation IP development. * Partnering with ASIC engineers to deploy new technologies like emulation acceleration, advanced verification environment configuration and management, and AI technology for verification and emulation. * Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for DFT and UPF emulation acceleration. * Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies. * Work with extended teams to debug environment and drive cross-functional testing (Firmware, Software, Verification and Design) * Triage failures with design, verification, firmware, software teams * Mentoring and guiding junior engineers, fostering a culture of collaboration, innovation and continuous improvement. ## Qualifications Qualifications: * BE or MS degree in Electrical Engineering or Computer Engineering, with 6 to 9 years of experience. * Solid experience working on emulation platforms such as Veloce, Zebu, or Palladium (compilation, debug, performance, and throughput tuning) * Debugging experience is a must particularly in HW/SW co-debug environments * Understanding of SystemVerilog UVM and verification methodologies especially testplan creation and constructs of testbench architecture. Able to debug problems between verification and emulation. Skills Required: * Programming and automation skills in Python, TCL and PERL * Working knowledge of Linux/Unix environment and shell scripting * Excellent debugging and problem-solving skills with simulation and emulation environments. * Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues. * Strong team player, able to collaborate effectively across architecture, design, and validation teams. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at[jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Staff Engineer, ASIC Development Engineering at Sandisk. Skills: ASIC development, Emulation, Verification, Debugging. Provide technical leadership. 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With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. * The ASIC emulation team is seeking highly motivated engineer to join a team of experienced engineers working on the development of advanced controller SoCs. As a Technologist Emulation Engineer in the ASIC Emulation team, you will be responsible for enabling new emulation & verification technology for the larger ASIC team. This includes traditional verification technology that is now being accelerated by GenAI and accelerating verification of DFT and UPF with emulation. This unique position requires a mix of verification and emulation skills. The growing diversity of data creates an exponential number of new possibilities – for the world, our company, and you. You’ll be part of a team driving the innovations necessary to outpace new demands and challenges everywhere data lives, from sensors to mobile devices to the cloud. We’ve only started to scratch the surface of what data can do. You can help unlock its full potential. * Providing technical leadership and expertise to define requirements for Emulation and Emulation IP development. * Partnering with ASIC engineers to deploy new technologies like emulation acceleration, advanced verification environment configuration and management, and AI technology for verification and emulation. * Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for DFT and UPF emulation acceleration. * Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies. * Work with extended teams to debug environment and drive cross-functional testing (Firmware, Software, Verification and Design) * Triage failures with design, verification, firmware, software teams * Mentoring and guiding junior engineers, fostering a culture of collaboration, innovation and continuous improvement. ## Qualifications Qualifications: * BE or MS degree in Electrical Engineering or Computer Engineering, with 6 to 9 years of experience. * Solid experience working on emulation platforms such as Veloce, Zebu, or Palladium (compilation, debug, performance, and throughput tuning) * Debugging experience is a must particularly in HW/SW co-debug environments * Understanding of SystemVerilog UVM and verification methodologies especially testplan creation and constructs of testbench architecture. Able to debug problems between verification and emulation. Skills Required: * Programming and automation skills in Python, TCL and PERL * Working knowledge of Linux/Unix environment and shell scripting * Excellent debugging and problem-solving skills with simulation and emulation environments. * Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues. * Strong team player, able to collaborate effectively across architecture, design, and validation teams. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at[jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Staff Engineer, ASIC Development Engineering at Sandisk. Skills: ASIC emulation, Verification technology, Emulation acceleration. Provide technical leadership. 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Wi-Fi technology; Internet of Things (IoT); Semiconductor company; Fabless semiconductor; Next-generation Wi-Fi chips; Wi-Fi HaLow (802.11ah); Low power Wi-Fi; Wireless SoCs; Digital design fundamentals; Hierarchical DFT methodologies; SCAN solutions; MBIST; JTAG; IEEE 1149.1; IEEE 1500; ATPG; GLS; SDF; WGL/STIL; ATE; RTL; Verification; PnR; Third-party IPs; PLL; USB PHY; RRAM; FUSE", "domainList" : [ "wireless-connectivity", "wi-fi-technology", "internet-of-things-iot", "semiconductor-company", "fabless-semiconductor", "next-generation-wi-fi-chips", "wi-fi-halow-802-11ah", "low-power-wi-fi", "wireless-socs", "digital-design-fundamentals", "hierarchical-dft-methodologies", "scan-solutions", "mbist", "jtag", "ieee-1149-1", "ieee-1500", "atpg", "gls", "sdf", "wgl-stil", "ate", "rtl", "verification", "pnr", "third-party-ips", "pll", "usb-phy", "rram", "fuse" ], "domainSpecificKnowledge" : [ "Wireless connectivity", "Wi-Fi technology", "Internet of Things (IoT)", "Semiconductor company", "Fabless semiconductor", "Next-generation Wi-Fi chips", "Wi-Fi HaLow (802.11ah)", "Low power Wi-Fi", "Wireless SoCs", "Digital design fundamentals", "Hierarchical DFT methodologies", "SCAN solutions", "MBIST", "JTAG", "IEEE 1149.1", "IEEE 1500", "ATPG", "GLS", "SDF", "WGL/STIL", "ATE", "RTL", "Verification", "PnR", "Third-party IPs", "PLL", "USB PHY", "RRAM", "FUSE" ], "communicationSkills" : "Verbal communication; Written communication", "problemSolvingSkills" : "Problem-solving skills; Analytical skills", "qualificationsBasic" : "Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science, 5+ years experience as a DFT Engineer, Hands-on experience in scan insertion/stitching, Hands-on experience in ATPG setup, Hands-on experience in JTAG, Hands-on experience in simulation, Hands-on experience in debug, Hands-on experience in scan DRC analysis, Solid understanding of digital design fundamentals, Solid understanding of RTL coding, Solid understanding of verification, Proven expertise on hierarchical DFT methodologies, Post-silicon debug experience, Silicon bring-up experience, Excellent verbal communication skills, Excellent written communication skills, Proven to work constructively within your team, Proven to work constructively among other groups, Analytical and problem-solving skills, A determination to deliver even when subject to time pressures, A hands-on, practical attitude", "remoteFriendly" : false, "workSiteFlexibility" : "Flexible", "rawDescription" : "Morse Micro is at the forefront of next-generation Wi-Fi technology, delivering breakthrough solutions that redefine wireless connectivity. Our innovative products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability. Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things (IoT)? Keen to make a real difference in a VC-backed high-growth company while working in a dynamic & fun environment? Then join Morse Micro, Australia’s largest fabless semiconductor company! Your responsibilities would include: - Own end-to-end DFT for wireless SoCs, including architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support. - Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints. - Architect and implement SCAN solutions, including chains, sub-chains, masking, compressors, decompressors, SDCs, and ensure post synthesis SCAN DRC clean - Develop and integrate at-speed test methodologies using OPCG for intra- and inter-clock domain testing. - Implement low-power DFT techniques such as power-aware scan, clock staggering, and test-point insertion to meet ATE/package limits. - Own MBIST integration and diagnostics for all on-chip memories, including JTAG-based debug diagnostic flows. - Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test-mode/pin-mux control. - Integrate DFT for third-party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration. - Generate and validate ATPG (stuck-at, transition, path-delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring-up/debug. - Drive silicon debug, yield analysis, DFT scripting / automation, and cross-functional collaboration with frontend, verification, PnR, and ATE in fast-paced tapeout programs. Essential skills (you must have): - Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science - 5+ years experience as a DFT Engineer - Strong hands-on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis - Solid understanding of digital design fundamentals, including RTL coding and verification - Proven expertise on hierarchical DFT methodologies is a plug - Post-silicon debug and silicon bring-up experience - Excellent verbal and written communication skills - Proven to work constructively within your team and among other groups - Strong analytical and problem-solving skills - A determination to deliver even when subject to time pressures - A hands-on, practical attitude What we offer: - Competitive salary + excellent stock option package - Performance Bonus opportunity - Income protection Insurance - Healthy work environment with sit/stand desks and large screens - Lots of snacks & drinks, including barista coffee, Friday team lunches & some of the world’s best beers - Flexible working hours - Work from home policy - Community & social groups and much more - Join a high performing, inclusive company where you can make a real impact Who we are: Morse Micro is Australia’s largest semiconductor company building Wi-Fi HaLow (802.11ah) chips for the Internet of Things (IoT). We are a team of wireless experts that love to work hard, innovate, and invent. Together, we are building the world’s lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet. We are a global team with offices in Sydney, Picton & Melbourne (Australia), Irvine, Bay Area & Boston (USA), Bangalore (India), Cambridge (UK), Hangzhou (China), Taipei (Taiwan) and Tokyo (Japan).", "summaryDescription" : "Senior DFT Engineer at Morse Micro. Skills: DFT architecture, SCAN solutions, MBIST integration, ATPG patterns. Own end-to-end DFT for wireless SoCs. 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"intermediate" }, { "name" : "Automation", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "DFT, SoC, Wireless chips", "majorSkillsList" : [ "DFT", "SoC", "Wireless chips" ], "coreResponsibilities" : "Own end-to-end DFT for wireless SoCs, Define DFT architecture and coverage goals, Optimize test quality, pattern count, power, area, and, Architect and implement SCAN solutions, Ensure post synthesis SCAN DRC clean, Develop and integrate at-speed test methodologies, Implement low-power DFT techniques, Own MBIST integration and diagnostics, Implement and maintain IEEE 1149.1 JTAG/TAP, Integrate DFT for third-party hardened IPs, Generate and validate ATPG patterns, Validate MBIST patterns, Perform GLS with SDF, Deliver WGL/STIL, Support first silicon ATE bring-up/debug, Drive silicon debug, Drive yield analysis, Drive DFT scripting / automation", "teamCollaboration" : "Cross-functional collaboration; Frontend teams; Verification teams; PnR teams; ATE teams", "projectManagementSkills" : [ "Tapeout programs" ], "domainKnowledge" : "Next-generation Wi-Fi; Wireless connectivity; Internet of Things (IoT); Wi-Fi HaLow (802.11ah); Semiconductor; Fabless semiconductor; Wi-Fi technology; Low power Wi-Fi", "domainList" : [ "next-generation-wi-fi", "wireless-connectivity", "internet-of-things-iot", "wi-fi-halow-802-11ah", "semiconductor", "fabless-semiconductor", "wi-fi-technology", "low-power-wi-fi" ], "domainSpecificKnowledge" : [ "Next-generation Wi-Fi", "Wireless connectivity", "Internet of Things (IoT)", "Wi-Fi HaLow (802.11ah)", "Semiconductor", "Fabless semiconductor", "Wi-Fi technology", "Low power Wi-Fi" ], "toolProficiency" : [ "OPCG", "JTAG", "BSDL", "WGL", "STIL" ], "communicationSkills" : "Verbal communication; Written communication", "innovationCreativity" : "Innovate; Invent", "problemSolvingSkills" : "Problem-solving; Analytical skills; Silicon debug; Yield analysis", "specialRequirements" : "Relocation support, Visa support", "qualificationsBasic" : "Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science, 5+ years experience as a DFT Engineer, Hands-on experience in scan insertion/stitching, Hands-on experience in ATPG setup, Hands-on experience in JTAG, Hands-on experience in simulation, Hands-on experience in debug, Hands-on experience in scan DRC analysis, Solid understanding of digital design fundamentals, Proven expertise on hierarchical DFT methodologies, Post-silicon debug experience, Silicon bring-up experience, Excellent verbal and written communication skills, Proven to work constructively within your team, Proven to work constructively among other groups, Analytical and problem-solving skills, A determination to deliver even when subject to time pressures, A hands-on, practical attitude", "remoteFriendly" : true, "workSiteFlexibility" : "Flexible", "rawDescription" : "Morse Micro is at the forefront of next-generation Wi-Fi technology, delivering breakthrough solutions that redefine wireless connectivity. Our innovative products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability. Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things (IoT)? Keen to make a real difference in a VC-backed high-growth company while working in a dynamic & fun environment? Then join Morse Micro, Australia’s largest fabless semiconductor company! We welcome applications from overseas candidates, with relocation and visa support available for the successful applicant. Your responsibilities would include: - Own end-to-end DFT for wireless SoCs, including architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support. - Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints. - Architect and implement SCAN solutions, including chains, sub-chains, masking, compressors, decompressors, SDCs, and ensure post synthesis SCAN DRC clean - Develop and integrate at-speed test methodologies using OPCG for intra- and inter-clock domain testing. - Implement low-power DFT techniques such as power-aware scan, clock staggering, and test-point insertion to meet ATE/package limits. - Own MBIST integration and diagnostics for all on-chip memories, including JTAG-based debug diagnostic flows. - Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test-mode/pin-mux control. - Integrate DFT for third-party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration. - Generate and validate ATPG (stuck-at, transition, path-delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring-up/debug. - Drive silicon debug, yield analysis, DFT scripting / automation, and cross-functional collaboration with frontend, verification, PnR, and ATE in fast-paced tapeout programs. Essential skills (you must have): - Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science - 5+ years experience as a DFT Engineer - Strong hands-on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis - Solid understanding of digital design fundamentals, including RTL coding and verification - Proven expertise on hierarchical DFT methodologies is a plug - Post-silicon debug and silicon bring-up experience - Excellent verbal and written communication skills - Proven to work constructively within your team and among other groups - Strong analytical and problem-solving skills - A determination to deliver even when subject to time pressures - A hands-on, practical attitude What we offer: - Competitive salary + excellent stock option package - Performance Bonus opportunity - Income protection Insurance - Healthy work environment with sit/stand desks and large screens - Lots of snacks & drinks, including barista coffee, Friday team lunches & some of the world’s best beers - Flexible working hours - Work from home policy - Community & social groups and much more - Join a high performing, inclusive company where you can make a real impact Who we are: Morse Micro is Australia’s largest semiconductor company building Wi-Fi HaLow (802.11ah) chips for the Internet of Things (IoT). We are a team of wireless experts that love to work hard, innovate, and invent. Together, we are building the world’s lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet. We are a global team with offices in Sydney, Picton & Melbourne (Australia), Irvine, Bay Area & Boston (USA), Bangalore (India), Cambridge (UK), Hangzhou (China), Taipei (Taiwan) and Tokyo (Japan).", "summaryDescription" : "Senior DFT Engineer at Morse Micro. Skills: DFT, SoC, Wireless chips. Own end-to-end DFT for wireless SoCs. Define DFT architecture and coverage goals", "createdAt" : "2026-06-14T09:05:34.367", "lastUpdated" : "2026-06-15T06:54:13.932", "ingestTimestamp" : "2026-06-14T09:05:34.367", "mongoId" : "6a2c693474d8ee00a09067ce", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "150k-200k", "hasSalary" : false, "allSkills" : [ "Scan insertion", "ATPG setup", "JTAG", "Simulation", "Debug", "Scan DRC analysis", "Digital design fundamentals", "Hierarchical DFT methodologies", "Post-silicon debug", "Silicon bring-up", "DFT architecture", "Coverage goals", "Test quality", "Pattern count", "Power optimization", "Area optimization", "Tester time", "SCAN solutions", "Scan chains", "Scan sub-chains", "Masking", "Compressors", "Decompressors", "SDCs", "At-speed test methodologies", "OPCG", "Intra-clock domain testing", "Inter-clock domain testing", "Low-power DFT techniques", "Power-aware scan", "Clock staggering", "Test-point insertion", "ATE limits", "Package limits", "MBIST integration", "MBIST diagnostics", "On-chip memories", "JTAG-based debug", "Diagnostic flows", "IEEE 1149.1 JTAG/TAP", "BSDL", "IEEE 1500 wrappers", "DFT test-mode control", "DFT pin-mux control", "Third-party hardened IPs", "Wrapper design", "Vendor pattern integration", "ATPG", "Stuck-at patterns", "Transition patterns", "Path-delay patterns", "GLS with SDF", "WGL", "STIL", "Silicon debug", "Yield analysis", "DFT scripting", "Automation", "Leadership", "DFT", "SoC", "Wireless chips", "Problem-solving", "Analytical skills", "Tapeout programs", "Next-generation Wi-Fi", "Wireless connectivity", "Internet of Things (IoT)", "Wi-Fi HaLow (802.11ah)", "Semiconductor", "Fabless semiconductor", "Wi-Fi technology", "Low power Wi-Fi" ], "skillCount" : 73, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "69f9b8034c40e2acd11140c3", "title" : "Senior DFT Engineer", "company" : "Annapurna Labs Ltd.", "industry" : "Software Development, Cloud Computing", "salary" : { "min" : 450000.0, "max" : 700000.0, "currency" : "ILS", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Senior DFT Engineer in Tel Aviv-Yafo, Israel, adjusted for seniority and industry." }, "location" : "Tel Aviv-Yafo, Tel Aviv, ISR", "locations" : [ "Tel Aviv-Yafo, Tel Aviv, ISR" ], "timestamp" : "2026-06-15T11:06:00.983", "fingerprint" : "99cbc73c5508650adb037daccd3809db7f36118e6cee0e4d8f97923e3ed299e5", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10409912/apply", "externalId" : "206220e9-31d6-40ab-8312-9b9a9217c549", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Tel Aviv-Yafo", "state" : "Tel Aviv", "country" : "Israel", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "32.0852997,34.7818064" } ], "locationText" : "Tel Aviv-Yafo, Tel Aviv, Israel", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Verilog, System Verilog", "professionalSkills" : [ "Semiconductor design", "DFT engineering", "Chip design", "Memory test", "Memory repair", "Verification methodologies", "Design for Debug", "Static Timing Analysis" ], "hardSkillsList" : [ "Structural scan techniques", "Memory test methodologies", "Memory repair methodologies" ], "hardSkills" : [ { "name" : "Structural scan techniques", "level" : "intermediate" }, { "name" : "Memory test methodologies", "level" : "intermediate" }, { "name" : "Memory repair methodologies", "level" : "intermediate" } ], "majorSkills" : "DFT engineering, Semiconductor design, Chip design", "majorSkillsList" : [ "DFT engineering", "Semiconductor design", "Chip design" ], "coreResponsibilities" : "Assume responsibility over full range of DFT, Lead a talented team of engineers, Work closely with frontend teams, Work closely with backend teams, Participate in architecture reviews, Participate in design reviews, Create design solutions for testability, Create design solutions for debug ability, Create design solutions for reliability improvement, Create design solutions for yield improvement, Provide design constraints for implementation, Provide design constraints for sign-off, Build work plans, Drive execution of work plans, Track execution of work plans, Be involved in silicon bring-up, Be involved in reliability testing, Be involved in advanced physical failure analysis, Get high-quality product out into AWS fleet", "teamCollaboration" : "Frontend teams; Backend teams; Cross-functional teams", "projectManagementSkills" : [ "Build work plans", "Drive execution", "Track execution" ], "domainKnowledge" : "Semiconductor products; Cloud infrastructure; Cloud computing; Structural scan techniques; Memory test; Memory repair; Design for test; Design for debug; 3D testing technologies", "domainList" : [ "semiconductor-products", "cloud-infrastructure", "cloud-computing", "structural-scan-techniques", "memory-test", "memory-repair", "design-for-test", "design-for-debug", "3d-testing-technologies" ], "domainSpecificKnowledge" : [ "Semiconductor products", "Cloud infrastructure", "Cloud computing", "Structural scan techniques", "Memory test", "Memory repair", "Design for test", "Design for debug", "3D testing technologies" ], "continuousLearning" : "Continuous learning opportunities", "innovationCreativity" : "Innovate; Shape the future; Redefining semiconductor technology; Pushing technological boundaries", "problemSolvingSkills" : "Debug ability; Failure analysis", "outcomesObjectives" : "Get high-quality product out quickly", "qualificationsBasic" : "Bachelor's degree in Computer Engineering or Electrical Engineering, Extensive expertise in semiconductor design, Extensive expertise in DFT engineering, Advanced knowledge of chip design using Verilog, Advanced knowledge of chip design using System Verilog, Proficient in structural scan techniques, Proficient in structural scan flows, Deep understanding of memory test, Deep understanding of memory repair methodologies, Demonstrated experience in leading complex technical projects", "qualificationsPreferred" : "Expertise in verification methodologies, Expertise in UVM, Comprehensive understanding of Design for Debug principles, Proficiency with Static Timing Analysis (STA), Experience with 3D testing technologies", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Annapurna Labs is a fabless semiconductor company founded by industry veterans and operates as part of Amazon Web Services (AWS). We develop leading-edge semiconductor products that power Amazon's cloud infrastructure. As a startup-like organization within AWS, we create technologies that drive the world's largest cloud provider. Our engineers work with cutting-edge technologies to innovate and shape the future of cloud computing. At Annapurna Labs, you'll experience a fast-paced environment that offers continuous learning opportunities and the chance to develop next-generation platforms. Why Join Us At Annapurna Labs, you'll be part of a dynamic team that's redefining semiconductor technology. We offer an environment that values innovation, collaboration, and continuous learning. Your work will directly impact millions of customers worldwide, driving the future of cloud computing. Watch these videos to learn more about Annapurna Labs. AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: https://www.youtube.com/watch?v=JeUpUK0nhC0 Reducing design for test (DFT) effort with Tessent Streaming Scan Network (SSN) - Dan Trock, Amazon https://www.youtube.com/watch?v=CYpqna1ac-4 Key job responsibilities In this highly-visible role you will assume responsibility over a full range of DFT in an extremely challenging project, leading a talented team of engineers, working closely with frontend and backend teams. You will participate in architecture and design reviews, create design solutions for testability, debug ability, reliability and yield improvement. You will provide design constraints for implementation and sign-off. You will build work plans, drive and track their execution. You will be closely involved in silicon bring-up, reliability testing and advanced physical failure analysis activities, and will be responsible for getting a high-quality product out into AWS fleet for millions of our customers quickly. Come and join us as we work hard, have fun, and make history. About the team We are a passionate group of world-class DFT experts dedicated to pushing technological boundaries. Our team operates in a collaborative, high-performance environment where innovation meets precision. We're committed to developing semiconductor solutions that enable cloud computing at a global scale, working closely with cutting-edge technology teams across Amazon. Basic Qualifications: - Bachelor's degree in Computer Engineering or Electrical Engineering - Extensive expertise in semiconductor design and DFT engineering - Advanced knowledge of chip design using Verilog and System Verilog - Proficient in structural scan techniques and flows - Deep understanding of memory test and repair methodologies - Demonstrated experience in leading complex technical projects Preferred Qualifications: - Expertise in verification methodologies, particularly UVM - Comprehensive understanding of Design for Debug principles - Proficiency with Static Timing Analysis (STA) - Experience with 3D testing technologies Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "Senior DFT Engineer at Annapurna Labs Ltd.. Skills: DFT engineering, Semiconductor design, Chip design. Assume responsibility over full range of DFT. Lead a talented team of engineers", "postedDate" : "2026-06-13T17:34:05.380", "createdAt" : "2026-06-13T17:34:05.380", "lastUpdated" : "2026-06-15T11:06:00.983", "ingestTimestamp" : "2026-06-13T17:34:05.380", "mongoId" : "69f9b8034c40e2acd11140c3", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10409912/apply", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Structural scan techniques", "Memory test methodologies", "Memory repair methodologies", "DFT engineering", "Semiconductor design", "Chip design", "Memory test", "Memory repair", "Verification methodologies", "Design for Debug", "Static Timing Analysis", "Build work plans", "Drive execution", "Track execution", "Semiconductor products", "Cloud infrastructure", "Cloud computing", "Design for test", "Design for debug", "3D testing technologies" ], "skillCount" : 20, "jobCategory" : "engineering", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Semiconductor" }, { "id" : "69c94a719bc74574cbbb3a9e", "title" : "ASIC AI/ML Engineer, Annapurna Labs, MLA SOC, Methodology & Infrastructure", "company" : "Annapurna Labs Ltd.", "industry" : "Machine Learning Science, ASIC, Cloud Computing", "salary" : { "min" : 450000.0, "max" : 750000.0, "currency" : "ILS", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Senior ASIC AI/ML Engineer in Tel Aviv-Yafo, Israel, adjusted for the technology industry." }, "location" : "Tel Aviv-Yafo, Tel Aviv, ISR", "locations" : [ "Tel Aviv-Yafo, Tel Aviv, ISR" ], "timestamp" : "2026-06-16T02:40:25.707", "fingerprint" : "8ad7cb794a3b823a1dda42178d715368b3572f1dc3535803d8aea08cc54f226b", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3197213/apply", "externalId" : "852905bc-50db-435a-b3e8-f2b4f090c4b9", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Tel Aviv-Yafo", "state" : "Tel Aviv", "country" : "Israel", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "32.0852997,34.7818064" } ], "locationText" : "Tel Aviv-Yafo, Tel Aviv, Israel", "employmentType" : "FULL_TIME", "technicalSkills" : "AI, ML, LLM, GenAI", "professionalSkills" : [ "Application development", "Large-scale solutions", "Design verification", "Production deployment", "System design" ], "hardSkillsList" : [ "Semiconductor design", "Verification processes" ], "hardSkills" : [ { "name" : "Semiconductor design", "level" : "intermediate" }, { "name" : "Verification processes", "level" : "intermediate" } ], "majorSkills" : "AI/ML infrastructure, ASIC design, Semiconductor design", "majorSkillsList" : [ "AI/ML infrastructure", "ASIC design", "Semiconductor design" ], "coreResponsibilities" : "Automate workflows, Develop large-scale solutions, Develop AI/ML infrastructure, Maintain AI/ML infrastructure, Architect AI/ML applications, Develop AI/ML applications, Deploy AI/ML applications, Design GenAI solutions, Implement LLMs, Implement agentic AI systems, Invent AI-driven solutions, Establish best practices, Establish standards, Create monitoring frameworks, Create observability frameworks, Collaborate cross-functionally, Research emerging AI technologies, Evaluate emerging AI technologies", "teamCollaboration" : "Architects; Designers; Verification engineers; Software teams; Backend specialists", "domainKnowledge" : "ASIC design; ML acceleration; SOC development; Semiconductor design; Design verification; Generative AI; LLMs", "domainList" : [ "asic-design", "ml-acceleration", "soc-development", "semiconductor-design", "design-verification", "generative-ai", "llms" ], "domainSpecificKnowledge" : [ "ASIC design", "ML acceleration", "SOC development", "Semiconductor design", "Design verification", "Generative AI", "LLMs" ], "innovationCreativity" : "Invent innovative AI-driven solutions", "problemSolvingSkills" : "Eliminate identified inefficiencies", "outcomesObjectives" : "Accelerate silicon development; Accelerate path to tape-out", "qualificationsBasic" : "Experience with modern ASIC/FPGA design, Experience with verification tools, Developed scalable AI/ML infrastructure, Creating and maintaining automation frameworks, Practical semiconductor design/verification work experience", "qualificationsPreferred" : "Current on emerging AI technologies, Proficient in full-stack development, Proficient in infrastructure for ML, Proficient in infrastructure for GenAI", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Our Machine Learning Acceleration (MLA) team develops the SOCs that are used to power today’s AI workloads in datacenters all around the world. As a Frontend ASIC engineer, you’ll contribute to the project at the ground level by automating workflows and developing large-scale solutions that accelerate silicon development - it’s still Day One here at Amazon! We are seeking an experienced ASIC AI/ML Engineer with deep expertise in AI/ML infrastructure and application development specifically for semiconductor design verification disciplines. The ideal candidate will have a proven track record of delivering end-to-end AI solutions from concept to large-scale production deployment. In this role, you will collaborate directly with architects, designers, verification engineers, software teams, and backend specialists to define best practices and deploy production-ready AI-driven workflows and applications. Your focus will be on implementing LLM, GenAI, and classical ML solutions that transform our ASIC design verification processes and accelerate our path to tape-out. Key job responsibilities • Develop and maintain scalable AI/ML infrastructure for ASIC design and verification teams • Architect, develop, and deploy production-ready AI/ML applications for semiconductor design workflows • Design and implement GenAI solutions including LLMs and agentic AI systems for verification processes • Invent innovative AI-driven solutions to eliminate identified inefficiencies in design and verification flows • Establish best practices and standards for AI/ML application development in semiconductor environments • Create monitoring and observability frameworks for AI model performance in production design environments • Collaborate cross-functionally with architects, designers, verification engineers, and software teams • Research and evaluate emerging AI technologies for applicability to semiconductor design challenges Basic Qualifications: - Experience with modern ASIC/FPGA design and verification tools - Developed scalable AI/ML infrastructure for semiconductor design and verification teams - Creating and maintaining automation frameworks for design or verification - Practical semiconductor design/verification work experience Preferred Qualifications: - Current on emerging AI technologies for semiconductor design and verification applications - Proficient in full-stack development and infrastructure for state-of-the-art classic ML and generative AI technologies Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "ASIC AI/ML Engineer, Annapurna Labs, MLA SOC, Methodology & Infrastructure at Annapurna Labs Ltd.. Skills: AI/ML infrastructure, ASIC design, Semiconductor design. Automate workflows. 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"6a09f12b1663d49372a7dbb2", "title" : "Technologist, ASIC Development Engineering (Emulation Engineer, DFT, UPF, Zebu or Palladium, Methodology)", "company" : "Sandisk", "industry" : "Computer Hardware", "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-05-17T20:09:23.275", "fingerprint" : "279150d88ecd8899f1b7f5e5cdf8e856751e20cf69f0e3262043b891169f9525", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000126282209-technologist-asic-development-engineering-emulation-engineer-dft-upf-zebu-or-palladium-methodology-", "externalId" : "744000126282209", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "hybrid" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "minimumEducation" : "BE or MS degree in Electrical Engineering or Computer Engineering", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "Emulation, Verification, DFT, UPF, Zebu, Palladium, Veloce, SystemVerilog, UVM, Python, TCL, PERL, Linux/Unix, Shell scripting, ASIC, Controller SoCs, Emulation IP, Design IP, Firmware, Software", "professionalSkills" : [ "Technical leadership", "Technical expertise", "Methodology standardization", "Cross-functional collaboration" ], "hardSkillsList" : [ "Emulation platform operation (compilation, debug, performance, throughput tuning)", "HW/SW co-debug", "Testplan creation", "Testbench architecture construction", "Programming and automation", "Shell scripting", "Debugging simulation and emulation environments" ], "softSkillsList" : [ "Highly motivated", "Team player", "Collaboration", "Innovation", "Continuous improvement", "Mentoring", "Guiding junior engineers", "Fostering a culture of collaboration, innovation and continuous improvement" ], "hardSkills" : [ { "name" : "Emulation platform operation (compilation, debug, performance, throughput tuning)", "level" : "intermediate" }, { "name" : "HW/SW co-debug", "level" : "intermediate" }, { "name" : "Testplan creation", "level" : "intermediate" }, { "name" : "Testbench architecture construction", "level" : "intermediate" }, { "name" : "Programming and automation", "level" : "intermediate" }, { "name" : "Shell scripting", "level" : "intermediate" }, { "name" : "Debugging simulation and emulation environments", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Highly motivated" }, { "name" : "Team player" }, { "name" : "Collaboration" }, { "name" : "Innovation" }, { "name" : "Continuous improvement" }, { "name" : "Mentoring" }, { "name" : "Guiding junior engineers" }, { "name" : "Fostering a culture of collaboration, innovation and continuous improvement" } ], "majorSkills" : "Emulation, Verification, DFT, UPF, ASIC Development Engineering, Emulation platforms (Zebu, Palladium, Veloce), Python, TCL, PERL, Linux/Unix", "majorSkillsList" : [ "Emulation", "Verification", "DFT", "UPF", "ASIC Development Engineering", "Emulation platforms (Zebu, Palladium, Veloce)", "Python", "TCL", "PERL", "Linux/Unix" ], "coreResponsibilities" : "Enabling new emulation & verification technology for the larger ASIC team, Accelerating verification of DFT and UPF with emulation, Providing technical leadership and expertise to define requirements for Emulation and Emulation IP development, Partnering with ASIC engineers to deploy new technologies like emulation acceleration, advanced verification environment configuration and management, and AI technology for verification and emulation, Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for DFT and UPF emulation acceleration, Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies, Work with extended teams to debug environment and drive cross-functional testing (Firmware, Software, Verification and Design), Triage failures with design, verification, firmware, software teams, Mentoring and guiding junior engineers", "teamCollaboration" : "Partnering with ASIC engineers; Collaborating cross-functionally; Work with extended teams; Triage failures with design, verification, firmware, software teams; team player, able to collaborate effectively across architecture, design, and validation teams", "domainKnowledge" : "Advanced controller SoCs development; Flash and advanced memory technologies; ASIC emulation; Verification technology; DFT; UPF; SystemVerilog UVM; Verification methodologies; Testplan creation; Testbench architecture", "domainList" : [ "advanced-controller-socs-development", "flash-and-advanced-memory-technologies", "asic-emulation", "verification-technology", "dft", "upf", "systemverilog-uvm", "verification-methodologies", "testplan-creation", "testbench-architecture" ], "domainSpecificKnowledge" : [ "Advanced controller SoCs development", "Flash and advanced memory technologies", "ASIC emulation", "Verification technology", "DFT", "UPF", "SystemVerilog UVM", "Verification methodologies", "Testplan creation", "Testbench architecture" ], "toolProficiency" : [ "Veloce", "Zebu", "Palladium", "Linux/Unix environment", "Shell scripting" ], "continuousLearning" : "Fostering a culture of continuous improvement", "innovationCreativity" : "Relentlessly innovate to deliver solutions; Driving innovations necessary to outpace new demands and challenges; Fostering a culture of innovation", "problemSolvingSkills" : "Excellent debugging and problem-solving skills with simulation and emulation environments", "qualificationsBasic" : "BE or MS degree in Electrical Engineering or Computer Engineering, 13+ years of experience, Solid experience working on emulation platforms such as Veloce, Zebu, or Palladium (compilation, debug, performance, and throughput tuning), Debugging experience is a must particularly in HW/SW co-debug environments, Understanding of SystemVerilog UVM and verification methodologies especially testplan creation and constructs of testbench architecture, Able to debug problems between verification and emulation, Programming and automation skills in Python, TCL and PERL, Working knowledge of Linux/Unix environment and shell scripting, Excellent debugging and problem-solving skills with simulation and emulation environments", "qualificationsPreferred" : "GenAI experience for verification and emulation acceleration, Emulation IP feature set knowledge, Design IP verification for DFT and UPF emulation acceleration knowledge", "remoteFriendly" : false, "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. * The ASIC emulation team is seeking highly motivated engineer to join a team of experienced engineers working on the development of advanced controller SoCs. As a Technologist Emulation Engineer in the ASIC Emulation team, you will be responsible for enabling new emulation & verification technology for the larger ASIC team. This includes traditional verification technology that is now being accelerated by GenAI and accelerating verification of DFT and UPF with emulation. This unique position requires a mix of verification and emulation skills. The growing diversity of data creates an exponential number of new possibilities – for the world, our company, and you. You’ll be part of a team driving the innovations necessary to outpace new demands and challenges everywhere data lives, from sensors to mobile devices to the cloud. We’ve only started to scratch the surface of what data can do. You can help unlock its full potential. * Providing technical leadership and expertise to define requirements for Emulation and Emulation IP development. * Partnering with ASIC engineers to deploy new technologies like emulation acceleration, advanced verification environment configuration and management, and AI technology for verification and emulation. * Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for DFT and UPF emulation acceleration. * Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies. * Work with extended teams to debug environment and drive cross-functional testing (Firmware, Software, Verification and Design) * Triage failures with design, verification, firmware, software teams * Mentoring and guiding junior engineers, fostering a culture of collaboration, innovation and continuous improvement. ## Qualifications * BE or MS degree in Electrical Engineering or Computer Engineering, with 13+ years of experience. * Solid experience working on emulation platforms such as Veloce, Zebu, or Palladium (compilation, debug, performance, and throughput tuning) * Debugging experience is a must particularly in HW/SW co-debug environments * Understanding of SystemVerilog UVM and verification methodologies especially testplan creation and constructs of testbench architecture. Able to debug problems between verification and emulation. Skills Required: * Programming and automation skills in Python, TCL and PERL * Working knowledge of Linux/Unix environment and shell scripting * Excellent debugging and problem-solving skills with simulation and emulation environments. * Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues. * Strong team player, able to collaborate effectively across architecture, design, and validation teams. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Technologist, ASIC Development Engineering (Emulation Engineer, DFT, UPF, Zebu or Palladium, Methodology) at Sandisk. Skills: Emulation, Verification, DFT, UPF, ASIC Development Engineering, Emulation platforms (Zebu, Palladium, Veloce), Python, TCL, PERL, Linux/Unix. Enabling new emulation & verification technology for the larger ASIC team. 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"majorSkillsList" : [ "Physical Design, PD Methodology, CAD, STA Signoff, ASIC Development Engineering" ], "coreResponsibilities" : "Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs. Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability. Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices. Work closely with foundry partners to understand node-specific challenges and develop correct-by-construction solutions. Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges. Develop “shift-left” and “push-up” methodologies. Deliver high-quality, signoff-clean flows with emphasis on reliability, yield, and manufacturability. Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity. Foster a culture of technical excellence and innovation.", "teamCollaboration" : "Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence. Experience working in multi-project, high-complexity environments with tight schedules.", "toolProficiency" : [ "Synthesis, Logical Equivalence Checking (LEC), DFT insertion, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis" ], "communicationSkills" : "communication", "continuousLearning" : "Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges.", "innovationCreativity" : "Drive innovation across flows, tools, and teams. Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges.", "problemSolvingSkills" : "cross-domain problems; design convergence; debug efficiency", "specialRequirements" : "SanDisk thrives on the power and potential of diversity. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. SanDisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs. accommodations@sandisk. com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "outcomesObjectives" : "Deliver best in class products. Enable best-in-class PPA, quality, and productivity. Drive continuous improvement in PPA and turnaround time. Deliver high-quality, signoff-clean flows with emphasis on reliability, yield, and manufacturability.", "qualificationsBasic" : "2+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs. Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis. Grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA. Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes. Proficiency in scripting and automation using TCL, Perl, and/or Python.", "qualificationsPreferred" : "Exposure to advanced nodes and complex signoff requirements. Experience with memory controllers or high-performance data-path designs. Prior experience applying AI/ML in EDA or design automation is a plus. Communication and stakeholder management skills. Experience working in multi-project, high-complexity environments with tight schedules.", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "SanDisk is uniquely positioned at the heart of the AI-driven data economy, with a focused portfolio centered on advanced NAND flash and SSD technologies that underpin cloud, enterprise, and hyperscale infrastructures. As AI workloads continue to explode in scale and complexity, the need for high-throughput, low-latency, and energy-efficient storage has become mission-critical—an area where SanDisk’s technology leadership clearly stands out. Now operating as a focused, independent storage company, SanDisk has sharpened its execution and innovation engine to serve the rapidly growing AI, data center, and edge markets. Its inclusion in the S &P 500 is a strong validation of both its operational maturity and its relevance as a core infrastructure player in the global technology ecosystem. As AI increasingly moves from training to large-scale inferencing , storage plays a decisive role in system performance. Fast access to models, embeddings, and real-time data requires ultra-low latency, high endurance, and power-efficient storage—particularly in distributed and edge deployments. SanDisk’s flash-based solutions are well aligned to enable efficient, scalable AI inferencing by minimizing data movement bottlenecks between compute and storage. Driven by experienced leadership and a clear long-term vision, SanDisk is not just responding to the AI wave—it is helping define the storage foundation on which next-generation AI systems will be built. Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-class NAND Flash products used globally at massive scale. Design Enablement team enables the Technology, Methodology and Flows to the Physical Design team to deliver best in class products. As the PD Methodology / CAD Lead , you will play a pivotal role in defining, architecting, and delivering robust RTL-to-GDS physical design methodologies on cutting-edge technology nodes , enabling best-in-class PPA, quality, and productivity. This role is ideal for a seasoned PD methodology leader who enjoys solving complex cross-domain problems, working closely with foundries, and driving innovation across flows, tools, and teams. Key Responsibilities * Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs. * Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability. * Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices. * Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions. * Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence. * Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules. * Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability. * Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity. * Foster a culture of technical excellence and innovation , encouraging the team to develop novel solutions for next-generation challenges. * ## Qualifications * Qualifications 2+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs. * Deep, hands-on understanding of complete PD flow , including: * Synthesis * Logical Equivalence Checking (LEC) * DFT insertion and integration * Place & Route * Static Timing Analysis (STA) * Physical Verification * EM/IR analysis * Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA. * Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes. * M.Tech in VLSI Design or a related field (or equivalent industry experience). * Proficiency in scripting and automation using TCL, Perl, and/or Python. * Additional information Desirable Skills * Exposure to advanced nodes and complex signoff requirements. * Experience with memory controllers or high-performance data-path designs. * Prior experience applying AI/ML in EDA or design automation is a strong plus. * Strong communication and stakeholder management skills. Experience working in multi-project, high-complexity environments with tight schedules. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Senior Engineer, ASIC Development Engineering at Sandisk. Skills: Physical Design, PD Methodology, CAD, STA Signoff, ASIC Development Engineering. Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs. Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability. Drive continuous improvement in PPA (Power, Performance, Area) and tur", "postedDate" : "2026-06-10T12:17:32.000", "createdAt" : "2026-06-14T19:13:11.720", "lastUpdated" : "2026-06-15T13:56:37.950", "ingestTimestamp" : "2026-06-14T19:13:11.720", "mongoId" : "6a2c70fb74d8ee00a092d252", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "hasSalary" : false, "allSkills" : [ "RTL to GDS physical design methodologies", "PPA", "design rules", "variability", "EM/IR", "signoff requirements", "memory controllers", "high-performance data-path designs", "stakeholder management", "Physical Design, PD Methodology, CAD, STA Signoff, ASIC Development Engineering", "ASIC Development Engineering (PD, PV Signoff, STA Signoff Flows), advanced NAND flash and SSD technologies, memory controllers, high-performance data-path designs.", "Synthesis, Logical Equivalence Checking (LEC), DFT insertion, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis" ], "skillCount" : 12, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "daysOld" : 5, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "69fda4e54c40e2acd1b99a29", "title" : "ASIC Sustaining Engineering Manager", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Project/Program/Product Management--Non-Tech, ASIC, alexa and amazon devices", "salary" : { "min" : 183000.0, "max" : 247600.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Sunnyvale, California, USA", "locations" : [ "Sunnyvale, California, USA" ], "timestamp" : "2026-06-15T05:02:55.478", "fingerprint" : "5f2038f1344f247178469cff2c20f373ce729cec3ec3d46b7ef9c42c82bdb298", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10412733/apply", "externalId" : "d5cba53a-1ed7-4876-afa4-d0caedefcd43", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "employmentType" : "FULL_TIME", "experienceLevel" : "Manager", "technicalSkills" : "ASIC, FPGA, RTL, AI tools", "professionalSkills" : [ "Supply Chain Management", "Cross-Functional Collaboration", "Relationship Management", "Production Operations", "Issue Management", "Quality Optimization", "Yield Optimization", "Cost Reduction", "Supplier Management", "Capacity Scaling", "Data Analytics" ], "hardSkillsList" : [ "Synthesis", "STA", "Physical design", "RTL coding", "RTL debug", "Performance analysis", "Power analysis", "Area analysis", "SOC bring-up", "Post-silicon validation" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Synthesis", "level" : "intermediate" }, { "name" : "STA", "level" : "intermediate" }, { "name" : "Physical design", "level" : "intermediate" }, { "name" : "RTL coding", "level" : "intermediate" }, { "name" : "RTL debug", "level" : "intermediate" }, { "name" : "Performance analysis", "level" : "intermediate" }, { "name" : "Power analysis", "level" : "intermediate" }, { "name" : "Area analysis", "level" : "intermediate" }, { "name" : "SOC bring-up", "level" : "intermediate" }, { "name" : "Post-silicon validation", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "ASIC Sustaining Engineering, Supply Chain, Operations Management", "majorSkillsList" : [ "ASIC Sustaining Engineering", "Supply Chain", "Operations Management" ], "coreResponsibilities" : "Lead offshore sustain engineers, Provide KPI, Provide technical training, Provide motivation, Build trust-based relationships, Maintain urgency, Maintain accountability, Solve complex problems, Partner with NPI teams, Partner with OSAT teams, Establish work models, Establish ownership, Establish expectations, Collaborate with NPI engineers, Debug test issues, Prioritize production needs, Manage SW/HW consignment, Respond to daily production issues, Determine local resolution needs, Determine NPI escalation needs, Establish JIRA workflows, Enable priority-setting, Identify quality concerns, Highlight yield improvement opportunities, Drive continuous improvement initiatives, Monitor production metrics, Alert stakeholders to deviations, Support cost reduction campaigns, Reduce test time, Implement multi-site testing, Simplify hardware, Eliminate cost adders, Eliminate redundant work, Eliminate material waste, Improve throughput, Improve resource utilization, Define capacity scaling criteria, Evaluate OSAT partners, Qualify new OSAT sources, Leverage internal systems, Query yield data, Query consignment status, Implement automated alerts", "teamCollaboration" : "Cross-functional stakeholders; NPI teams; OSAT teams; Cross-functional teams", "projectManagementSkills" : [ "Agile" ], "domainKnowledge" : "Deep sub-micron nodes; ASIC/FPGA design; SOC architecture; LEO satellites; Broadband access", "domainList" : [ "deep-sub-micron-nodes", "asic-fpga-design", "soc-architecture", "leo-satellites", "broadband-access" ], "domainSpecificKnowledge" : [ "Deep sub-micron nodes", "ASIC/FPGA design", "SOC architecture", "LEO satellites", "Broadband access" ], "toolProficiency" : [ "JIRA" ], "communicationSkills" : "Communicate effectively; Communicate respectfully", "problemSolvingSkills" : "Solve complex problems", "specialRequirements" : "U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S. as refugee, Lawfully admitted into the U. S. as granted asylum", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, 7+ years ASIC implementation experience, 7+ years synthesis experience, 7+ years STA experience, 7+ years physical design experience, Deep sub-micron nodes experience, U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S. as refugee, Lawfully admitted into the U. S. as granted asylum", "qualificationsPreferred" : "Master's degree or Ph. D. degree, Experience in RTL coding, Experience in RTL debug, Experience with performance analysis, Experience with power analysis, Experience with area analysis, Experience with modern ASIC design tools, Experience with modern FPGA design tools, Experience with SOC bring-up, Experience with post-silicon validation", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon Leo is an initiative to increase global broadband access through a constellation of 3,236 satellites in low Earth orbit (LEO). Its mission is to bring fast, affordable broadband to unserved and underserved communities around the world. Amazon Leo will help close the digital divide by delivering fast, affordable broadband to a wide range of customers, including consumers, businesses, government agencies, and other organizations operating in places without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. The Amazon Leo Supply Chain team is looking for a ASIC Sustaining Engineering Manager Lead offshore sustain engineers by providing KPI, technical training and motivation. The ideal candidate will have a successful track record building trust-based relationships while maintaining urgency and accountability. Experience working in new and ambiguous environments while solving complex problems with a broad range of cross functional stakeholders will also be an advantage. Key job responsibilities Cross-Functional Collaboration & Relationship Management • Partner with NPI and OSAT teams to establish clear work models, ownership, and expectations • Build trust-based relationships with OSAT while maintaining urgency and accountability • Collaborate with NPI engineers on test issue debugging while prioritizing production needs Production Operations & Issue Management • Manage SW/HW consignment to OSAT and respond to daily production issues (yield, QA failures, line downtime, data issues, logistics) • Determine whether issues require local resolution or NPI escalation • Establish and maintain JIRA workflows that enable priority-setting in dynamic situations Quality & Yield Optimization • Proactively identify quality concerns from OSAT reports and site visits (repetitive failures, abnormal behavior changes) • Highlight yield improvement opportunities and drive continuous improvement initiatives • Monitor production metrics and alert stakeholders to deviations from targets Cost Reduction & Efficiency • Support NPI cost reduction campaigns (test time reduction, multi-site testing, hardware simplification) • Identify and eliminate cost adders, redundant work, and material waste • Improve throughput and resource utilization Supplier Management & Scaling • Define capacity scaling criteria for OSAT partners • Evaluate and qualify new OSAT sources using defined metrics, execution plans, and correlation reports Data & Analytics • Leverage internal production monitoring systems to query real-time yield data and consignment status across multiple OSAT sites • Implement automated alerts using AI tools to notify stakeholders of missed targets Basic Qualifications: - Bachelor's degree in Electrical Engineering or a related field - 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience Preferred Qualifications: - Master's degree or Ph.D. degree in Electrical Engineering or related field - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs - Experience with modern ASIC/FPGA design and verification tools - Experience with SOC bring-up and post-silicon validation Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Sunnyvale - 183,000.00 - 247,600.00 USD annually", "summaryDescription" : "ASIC Sustaining Engineering Manager at Amazon Kuiper Manufacturing Enterprises LLC. Skills: ASIC Sustaining Engineering, Supply Chain, Operations Management. Lead offshore sustain engineers. Provide KPI", "postedDate" : "2026-06-13T17:19:52.447", "createdAt" : "2026-06-13T17:19:52.447", "lastUpdated" : "2026-06-15T05:02:55.478", "ingestTimestamp" : "2026-06-13T17:19:52.447", "mongoId" : "69fda4e54c40e2acd1b99a29", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10412733/apply", "salaryAnnualMin" : 183000, "salaryAnnualMax" : 247600, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Synthesis", "STA", "Physical design", "RTL coding", "RTL debug", "Performance analysis", "Power analysis", "Area analysis", "SOC bring-up", "Post-silicon validation", "Leadership", "ASIC Sustaining Engineering", "Supply Chain", "Operations Management", "Supply Chain Management", "Cross-Functional Collaboration", "Relationship Management", "Production Operations", "Issue Management", "Quality Optimization", "Yield Optimization", "Cost Reduction", "Supplier Management", "Capacity Scaling", "Data Analytics", "Agile", "Deep sub-micron nodes", "ASIC/FPGA design", "SOC architecture", "LEO satellites", "Broadband access", "JIRA" ], "skillCount" : 32, "jobCategory" : "project-management", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2b534474d8ee00a07b194d", "title" : "Sr DFT Engineer", "company" : "eInfochips Inc", "industry" : "Semiconductor Design Services", "salary" : { "min" : 38.0, "max" : 38.0, "currency" : "USD", "frequency" : "yearly" }, "location" : "United States of America", "locations" : [ "United States of America" ], "timestamp" : "2026-06-14T22:54:42.338", "fingerprint" : "420a77dadbdc52d06cb80622bad77eb27413f09412692e0a755a3276cefb8989", "source" : "workday", "language" : "en", "applyUrl" : "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-California-Remote-Employees/Sr-DFT-Engineer--eInfochips-Inc-_R242729", "externalId" : "R242729", "industryFunction" : { }, "locationPoint" : "51.43667,5.97917", "structuredLocations" : [ { "city" : "San Jose", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "hybrid", "geo" : "37.3361663,-121.8905910" } ], "locationText" : "San Jose, California, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "DFT, Scan, MBIST, ATPG, JTAG, TCL", "professionalSkills" : [ "Test pattern verification", "Silicon debug", "Data analysis" ], "hardSkillsList" : [ "DFT implementation", "DFT specifications", "DFT architectures", "DFT issues debugging", "ATPG patterns", "MBIST implementations", "Coverage analysis", "Scripting automation" ], "hardSkills" : [ { "name" : "DFT implementation", "level" : "intermediate" }, { "name" : "DFT specifications", "level" : "intermediate" }, { "name" : "DFT architectures", "level" : "intermediate" }, { "name" : "DFT issues debugging", "level" : "intermediate" }, { "name" : "ATPG patterns", "level" : "intermediate" }, { "name" : "MBIST implementations", "level" : "intermediate" }, { "name" : "Coverage analysis", "level" : "intermediate" }, { "name" : "Scripting automation", "level" : "intermediate" } ], "majorSkills" : "DFT, Scan, MBIST, ATPG", "majorSkillsList" : [ "DFT", "Scan", "MBIST", "ATPG" ], "coreResponsibilities" : "Design DFT, Implement DFT, Verify test patterns, Collaborate with Synthesis, Collaborate with STA, Collaborate with physical design, Debug DFT-related problems, Resolve DFT-related problems, Work with test engineers, Bring up test vectors, Ensure successful testing", "teamCollaboration" : "Synthesis; STA; Physical design; Test engineers", "domainKnowledge" : "Scan; ATPG; JTAG; MBIST; Block level DFT; SoC level DFT", "domainList" : [ "scan", "atpg", "jtag", "mbist", "block-level-dft", "soc-level-dft" ], "domainSpecificKnowledge" : [ "Scan", "ATPG", "JTAG", "MBIST", "Block level DFT", "SoC level DFT" ], "toolProficiency" : [ "Siemens-Tessent", "Synopsys" ], "continuousLearning" : "Tuition Reimbursement", "problemSolvingSkills" : "Root cause analysis", "specialRequirements" : "Travel to Arrow Client office", "outcomesObjectives" : "Successful testing", "qualificationsBasic" : "understanding of industry standards and best practices in DFT, Proven experience in developing DFT specifications and architectures, Expertise in debugging DFT issues, Ability to conduct experiments during silicon debug, Efficient scripting skills using TCL", "qualificationsPreferred" : "Siemens-Tessent for DFT implementation, Synopsys for DFT implementation", "remoteFriendly" : true, "workSiteFlexibility" : "Onsite", "rawDescription" : "# **Position:** Sr DFT Engineer (eInfochips Inc) # **Job Description:** **What You 'll Be Doing: ** * Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level * Verify test patterns using gate-level simulations. * Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems. * Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. **What We Are Looking For:** * Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG, and MBIST. * Proven experience in developing DFT specifications and architectures for complex designs. * Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. * Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation, and verification. * Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes. * Efficient scripting skills using TCL for automating tasks and developing custom flows. **What’s In It for You:** At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That’s why we offer competitive financial compensation, including various compensation plans and a solid benefits package. * Medical, Dental, Vision Insurance * 401k, With Matching Contributions * Short-Term/Long-Term Disability Insurance * Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options * Paid Time Off (including sick, holiday, vacation, etc.) * Tuition Reimbursement * Growth Opportunities * And more! **Work Arrangement Fully OnSite:** Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership. **Location:** San Jose, CA-Remote **About eInfochips:** eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries & verticals. **EEO Statement:** Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) # **Location:** US-CA-California (Remote Employees) Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes, at the Company’s request and sole discretion. # **Time Type:** Full time # **Job Category:** Engineering Services # **EEO Statement:** Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. [(Arrow EEO/AAP policy)](http://cdn.phenompeople.com/CareerConnectResources/ARELUS/documents/EqualEmploymentOpportunityPolicy_UnitedStates_2024-1713302215740.pdf) _All Arrow job postings are for existing job vacancies_. _We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application._", "summaryDescription" : "Sr DFT Engineer at eInfochips Inc. Skills: DFT, Scan, MBIST, ATPG. Design DFT. Implement DFT", "postedDate" : "2026-06-12T05:24:40.476", "createdAt" : "2026-06-12T05:24:40.301", "lastUpdated" : "2026-06-14T22:54:42.338", "ingestTimestamp" : "2026-06-12T05:24:40.301", "mongoId" : "6a2b534474d8ee00a07b194d", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-California-Remote-Employees/Sr-DFT-Engineer--eInfochips-Inc-_R242729", "salaryAnnualMin" : 79040, "salaryAnnualMax" : 79040, "salaryBand" : "75k-100k", "hasSalary" : true, "allSkills" : [ "DFT implementation", "DFT specifications", "DFT architectures", "DFT issues debugging", "ATPG patterns", "MBIST implementations", "Coverage analysis", "Scripting automation", "DFT", "Scan", "MBIST", "ATPG", "Test pattern verification", "Silicon debug", "Data analysis", "JTAG", "Block level DFT", "SoC level DFT", "Siemens-Tessent", "Synopsys" ], "skillCount" : 20, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "daysOld" : 2, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Semiconductor Design Services" }, { "id" : "6a2c70fb74d8ee00a092d24c", "title" : "Senior Engineer, ASIC Development Engineering (IP Verification )", "company" : "Sandisk", "industry" : "Computer Hardware", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Senior ASIC Development Engineering (IP Verification) roles in Bengaluru, India, adjusted for seniority and industry." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-15T07:46:29.780", "fingerprint" : "bedc111270cdea0dd79fe72f304991b534f8ec5fd53a296d9e84a5f73d89484c", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000131603659-senior-engineer-asic-development-engineering-ip-verification-", "externalId" : "744000131603659", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "SystemVerilog, SV-UVM, Perl, Python, AI/ML", "professionalSkills" : [ "Logic design", "Verification engineering", "Regression triage", "Failure clustering", "Coverage prediction" ], "hardSkillsList" : [ "RTL verification", "Testbench development", "Debugging", "Root-cause analysis" ], "hardSkills" : [ { "name" : "RTL verification", "level" : "intermediate" }, { "name" : "Testbench development", "level" : "intermediate" }, { "name" : "Debugging", "level" : "intermediate" }, { "name" : "Root-cause analysis", "level" : "intermediate" } ], "majorSkills" : "RTL verification, SystemVerilog, UVM, FPGA verification", "majorSkillsList" : [ "RTL verification", "SystemVerilog", "UVM", "FPGA verification" ], "coreResponsibilities" : "Design complex logic blocks, Design IPs, Work in multi-disciplinary environment, Develop FPGA solutions, Validate memory devices, Develop testbenches, Automate flows, Automate logs, Automate regressions, Triage regressions, Cluster failures, Predict coverage", "teamCollaboration" : "Multi-disciplinary environment; Local and global teams; Multiple interfaces", "domainKnowledge" : "Hardware verification; eMMC; UFS; USB; PCIe; DDR4", "domainList" : [ "hardware-verification", "emmc", "ufs", "usb", "pcie", "ddr4" ], "domainSpecificKnowledge" : [ "Hardware verification", "eMMC", "UFS", "USB", "PCIe", "DDR4" ], "toolProficiency" : [ "Cadence NCSim", "SimVision", "VManager", "Mentor waveform-debug", "Synopsys waveform-debug", "Git" ], "communicationSkills" : "Communicate findings; Communicate across interfaces", "documentationSkills" : "Written form communication", "innovationCreativity" : "Leveraging new technologies", "problemSolvingSkills" : "Root-cause analysis; Debugging; Troubleshooting", "qualificationsBasic" : "BE/ME in ECE, 5 years RTL verification, SystemVerilog proficiency, EDA tools knowledge, FPGA-based verification, SV-UVM simulation, Testbenches development, Debugging capability, Perl/Python proficiency, AI/ML fundamentals, ML techniques experience, Version control systems", "qualificationsPreferred" : "Advanced SVA experience, Advanced UVM experience, Standard protocols exposure, EMMC exposure, UFS exposure, USB exposure, PCIe exposure, DDR4 exposure", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. * The FPGA design team, part of the (VHS) group is responsible for developing a wide range of FPGA solutions for post-silicon validation of memory devices across Western Digital. Your main responsibilities as part of a winning group: * Complex logic blocks & IPs design * Work in a multi-disciplinary environment with a variety of complex interfaces. ## Qualifications * BE/ME in ECE, Electronics, or a related engineering discipline. * 5 years of hands-on experience in RTL verification at Block/IP/Sub-system/SoC levels. * Proficient in SystemVerilog for verification; advanced experience with SVA and UVM is a strong advantage. * Deep knowledge of EDA tools such as Cadence NCSim, SimVision, vManager, and waveform-debug tools from Mentor/Synopsys. * Experience with FPGA-based verification environments. * Practical experience with SV- UVM-based simulation environments. * Skilled in developing testbenches for constrained-random and metric-driven verification. * Strong debugging capability with the ability to root-cause design issues and communicate findings clearly in written form. * Exposure to standard protocols such as eMMC, UFS, USB, PCIe, and DDR4 is an advantage. * Proficiency in Perl/Python scripting; ability to automate flows, logs, and regressions. * Understanding of AI/ML fundamentals as applied to hardware verification workflows. * Experience using ML techniques for regression triage, failure clustering, anomaly detection, or coverage prediction. * Excellent communication and collaboration skills across local and global teams. * Ability to coordinate and communicate across multiple interfaces within the organization. * Innovative mindset; capable of leveraging new technologies, including AI/ML, to improve verification efficiency, organizational workflows, and alignment between technical and business goals. * Familiarity with version control systems such as Git. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Senior Engineer, ASIC Development Engineering (IP Verification ) at Sandisk. Skills: RTL verification, SystemVerilog, UVM, FPGA verification. Design complex logic blocks. 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As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the world’s largest cloud provider, in a dynamic, open, and fast-paced environment. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of Amazon Web Services (AWS), is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture. Key job responsibilities * Design and implement advanced Design-for-Test (DFT) architectures for complex semiconductor platforms * Develop high-quality test and debug patterns ensuring robust performance * Conduct comprehensive static timing analysis across multiple DFT modes * Verify intricate DFT logic and components with precision and creativity * Support silicon bring-up and device diagnostic processes A day in the life Annapurna Labs is a fabless semiconductor company established by semiconductor industry veterans and is part of Amazon Web Services (AWS). We are developing leading edge products widely used in the Amazon cloud. Annapurna Labs is like a big start-up in AWS. We develop using cutting-edge technologies, work with amazingly talented engineers, innovate and truly shape the future. Working for Annapurna Labs is thrilling, fast-paced, and a constant learning experience. Our offices are located in Sarona/Tel Aviv and Matam/Haifa. About the team Diverse Experiences Amazon values diverse experiences. Even if you do not meet all of the preferred qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying. Why AWS Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses. Work/Life Balance We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why flexible work hours and arrangements are part of our culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud. Inclusive Team Culture AWS values curiosity and connection. Our employee-led and company-sponsored affinity groups promote inclusion and empower our people to take pride in what makes us unique. Our inclusion events foster stronger, more collaborative teams. Our continual innovation is fueled by the bold ideas, fresh perspectives, and passionate voices our teams bring to everything we do. Mentorship and Career Growth We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional. Basic Qualifications: - Bachelor's degree in electrical engineering, computer engineering, or equivalent - 2+ years of experience in a semiconductor company as a DFT engineer Preferred Qualifications: - Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing - Experience with chip design, Verilog and System Verilog, ATPG tools, Scan insertion tools, Gate-level simulations, Static timing analysis, Scripting (Perl/Tcl) - Familiarity with ATE - Pro-active, oriented on execution Attentive to details and quality - Good communications and reporting skills Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. 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"name" : "Pattern generation", "level" : "intermediate" }, { "name" : "Silicon bring-up", "level" : "intermediate" }, { "name" : "Production support", "level" : "intermediate" }, { "name" : "Flow development", "level" : "intermediate" }, { "name" : "Backend flows", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" }, { "name" : "Influence" } ], "majorSkills" : "DFT Architecture, DFT Implementation, DFT Verification, Silicon Bring-up", "majorSkillsList" : [ "DFT Architecture", "DFT Implementation", "DFT Verification", "Silicon Bring-up" ], "coreResponsibilities" : "Define DFT architecture for SoCs, Own DFT architecture, Lead DFT planning, Lead DFT specification, Track DFT quality, Provide technical leadership, Drive DFT sign-off readiness, Lead DFT implementation, Lead DFT integration, Lead DFT verification, Own end-to-end DFT activities, Ensure high test coverage, Ensure robust pattern generation, Align with manufacturing requirements, Develop scalable DFT methodologies, Drive scalable DFT flows, Develop automation frameworks, Optimize DFT integration, Improve quality, Improve PPA, Improve turnaround time", "teamCollaboration" : "RTL teams; Physical Design teams; STA teams; Test Engineering teams; Cross-functional teams globally", "projectManagementSkills" : [ "Project lifecycle management" ], "domainKnowledge" : "AI infrastructure; Connectivity solutions; CXL; Ethernet; NVLink; PCIe; UALink; ASIC/SoC design; Chiplet-based systems; High-speed connectivity", "domainList" : [ "ai-infrastructure", "connectivity-solutions", "cxl", "ethernet", "nvlink", "pcie", "ualink", "asic-soc-design", "chiplet-based-systems", "high-speed-connectivity" ], "domainSpecificKnowledge" : [ "AI infrastructure", "Connectivity solutions", "CXL", "Ethernet", "NVLink", "PCIe", "UALink", "ASIC/SoC design", "Chiplet-based systems", "High-speed connectivity" ], "toolProficiency" : [ "Siemens Tessent", "Synopsys TestMAX" ], "problemSolvingSkills" : "Root cause analysis", "outcomesObjectives" : "Ensure successful tapeout; Ensure first-pass silicon success; Ensure production quality", "qualificationsBasic" : "Bachelor’s degree in Electrical Engineering, 12+ years of experience in DFT design, Experience leading DFT activities, Deep expertise in DFT techniques, Understanding of DFT and Physical Design flows, Experience with industry-standard DFT tools, Solid experience with DFT verification methodologies, Scripting skills (Tcl, Python, or Perl)", "qualificationsPreferred" : "Master’s degree preferred, Experience with advanced process nodes, Background in high-speed connectivity designs, Experience with hierarchical DFT methodologies, Knowledge of silicon bring-up, Familiarity with STA, low-power design, CDC", "workSiteFlexibility" : "Onsite", "rawDescription" : "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle—from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams. This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions. Key Responsibilities DFT Architecture & Technical Leadership Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies Lead DFT planning, specification, and quality tracking across the project lifecycle Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout Execution Across the Full Lifecycle Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels Own end-to-end DFT activities from specification through silicon bring-up and production support Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements Methodology & Cross-Functional Impact Develop and drive scalable DFT methodologies, flows, and automation frameworks Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time Basic Qualifications Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred) 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs Proven experience in leading DFT activities across full chip development cycles Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent) Solid experience with DFT verification methodologies and coverage analysis Strong scripting skills (Tcl, Python, or Perl) for automation and flow development Preferred Qualifications Experience with advanced process nodes (7nm and below) Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar) Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems Knowledge of silicon bring-up, production test flows, and yield optimization Familiarity with STA, low-power design, and CDC as it relates to DFT integration Strong leadership and communication skills, with ability to influence cross-functional teams globally We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "summaryDescription" : "Principal DFT Engineer at Astera Labs. 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experience, Regression suite development experience, Python scripting, TCL scripting, Perl scripting, Excellent debugging skills, Excellent problem-solving skills, Simulation environments, Emulation environments, Test plan creation, Test plan execution", "qualificationsPreferred" : "SystemVerilog UVM proficiency, Advanced verification methodologies proficiency, Python programming proficiency, Perl programming proficiency, TCL programming proficiency, BASH programming proficiency, Linux/Unix environment working knowledge, Shell scripting working knowledge", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. * Providing technical leadership and expertise to define requirements for framework through programming/scripting of verification and emulation flows. * Partnering with ASIC engineers to deploy and support framework for technologies like advanced verification environment configuration and management. * Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies. ## Qualifications * BE or MS degree in Electrical Engineering or Computer Engineering, with 8+ years of experience. * Understanding C, SystemVerilog UVM, coverage driven verification methodology especially testplan creation and constructs of testbench architecture. * Scripting and regression suite development experience using Python, TCL and Perl * Excellent debugging and problem-solving skills with simulation and emulation environments. Skills Required: * Proficiency with SystemVerilog UVM and advanced verification methodologies. * Good Programming/Scripting skills with languages such as Python, Perl, TCL and BASH * Working knowledge of Linux/Unix environment and shell scripting * Excellent debugging and problem-solving skills with simulation and emulation environments. Experience with test plan creation and execution. * Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues. * Strong team player, able to collaborate effectively across architecture, design, and validation teams. * Great written and verbal communication skills * Strong team player who can collaborate with colleagues ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at[jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Principal Engineer, ASIC Development Engineering (SOC Verification, System Verilog, Flows, Python, Scripting) at Sandisk. Skills: SOC Verification, System Verilog, Python, Scripting. Provide technical leadership. Define framework requirements", "postedDate" : "2026-06-15T16:05:24.000", "createdAt" : "2026-06-16T03:32:54.442", "lastUpdated" : "2026-06-16T13:06:53.077", "ingestTimestamp" : "2026-06-16T03:32:54.442", "mongoId" : "6a3092acf292fd229c0c3aee", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Coverage driven verification", "Testplan creation", "Testbench architecture", "Regression suite development", "Debugging", "Problem-solving", "SOC Verification", "System Verilog", "Python", "Scripting", "Technical leadership", "Framework programming", "Flow scripting", "Verification flows", "Emulation flows", "Framework deployment", "Framework support", "Workflow optimization", "Methodology standardization", "Advanced verification methodologies", "Linux/Unix environment", "Shell scripting" ], "skillCount" : 22, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 1.0, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a3080e2f292fd229c068078", "title" : "Principal Engineer, ASIC Development Engineering (SOC Verification, System Verilog, Flows, Python, Scripting)", "company" : "Sandisk", "industry" : "Computer Hardware", "salary" : { "min" : 4500000.0, "max" : 7000000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Principal Engineer in Bengaluru, India, adjusted for lead seniority, senior experience, and the technology industry." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-16T11:15:30.528", "fingerprint" : "77153969077d85a8a57712c566db283f80c23778c9cc820714a773a065a2b83a", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000132241519-principal-engineer-asic-development-engineering-soc-verification-system-verilog-flows-python-scripting-with-8-to-12-years-of-experience-", "externalId" : "744000132241519", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "minimumEducation" : "BE or MS degree", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "SystemVerilog, Python, Scripting, C, UVM, TCL, Perl, BASH, Linux, Unix", "professionalSkills" : [ "Technical leadership", "Framework programming", "Flow programming", "Verification flows", "Emulation flows", "System-level issues resolution" ], "hardSkillsList" : [ "Coverage driven verification", "Testplan creation", "Testbench architecture", "Regression suite development", "Debugging", "Problem-solving" ], "hardSkills" : [ { "name" : "Coverage driven verification", "level" : "intermediate" }, { "name" : "Testplan creation", "level" : "intermediate" }, { "name" : "Testbench architecture", "level" : "intermediate" }, { "name" : "Regression suite development", "level" : "intermediate" }, { "name" : "Debugging", "level" : "intermediate" }, { "name" : "Problem-solving", "level" : "intermediate" } ], "majorSkills" : "SOC Verification, System Verilog, Python, Scripting", "majorSkillsList" : [ "SOC Verification", "System Verilog", "Python", "Scripting" ], "coreResponsibilities" : "Provide technical leadership, Define requirements for framework, Program framework, Script framework, Define verification flows, Define emulation flows, Partner with ASIC engineers, Deploy framework, Support framework, Configure verification environment, Manage verification environment, Optimize verification workflows, Optimize emulation workflows, Standardize methodologies", "teamCollaboration" : "Cross-functional collaboration; Design teams; Validation teams; Firmware teams; Physical design teams; Architecture teams", "domainKnowledge" : "SOC Verification; Advanced verification methodologies; Testplan creation; Testbench architecture", "domainList" : [ "soc-verification", "advanced-verification-methodologies", "testplan-creation", "testbench-architecture" ], "domainSpecificKnowledge" : [ "SOC Verification", "Advanced verification methodologies", "Testplan creation", "Testbench architecture" ], "toolProficiency" : [ "Simulation environments", "Emulation environments" ], "communicationSkills" : "Written communication; Verbal communication", "problemSolvingSkills" : "Problem-solving; Debugging", "qualificationsBasic" : "BE or MS degree, 8+ years of experience, Understanding C, SystemVerilog UVM, Coverage driven verification methodology, Testplan creation, Testbench architecture constructs, Scripting experience, Regression suite development experience, Python scripting, TCL scripting, Perl scripting, Excellent debugging skills, Excellent problem-solving skills, Simulation environments, Emulation environments, Test plan creation, Test plan execution", "qualificationsPreferred" : "SystemVerilog UVM proficiency, Advanced verification methodologies proficiency, Python programming skills, Perl programming skills, TCL programming skills, BASH programming skills, Linux/Unix environment working knowledge, Shell scripting working knowledge", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. * Providing technical leadership and expertise to define requirements for framework through programming/scripting of verification and emulation flows. * Partnering with ASIC engineers to deploy and support framework for technologies like advanced verification environment configuration and management. * Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies. ## Qualifications * BE or MS degree in Electrical Engineering or Computer Engineering, with 8+ years of experience. * Understanding C, SystemVerilog UVM, coverage driven verification methodology especially testplan creation and constructs of testbench architecture. * Scripting and regression suite development experience using Python, TCL and Perl * Excellent debugging and problem-solving skills with simulation and emulation environments. Skills Required: * Proficiency with SystemVerilog UVM and advanced verification methodologies. * Good Programming/Scripting skills with languages such as Python, Perl, TCL and BASH * Working knowledge of Linux/Unix environment and shell scripting * Excellent debugging and problem-solving skills with simulation and emulation environments. Experience with test plan creation and execution. * Cross-Functional Collaboration: Ability to work closely with design, validation, firmware, and physical design teams to resolve system-level issues. * Strong team player, able to collaborate effectively across architecture, design, and validation teams. * Great written and verbal communication skills * Strong team player who can collaborate with colleagues ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at[jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Principal Engineer, ASIC Development Engineering (SOC Verification, System Verilog, Flows, Python, Scripting) at Sandisk. Skills: SOC Verification, System Verilog, Python, Scripting. Provide technical leadership. Define requirements for framework", "postedDate" : "2026-06-15T16:05:24.000", "createdAt" : "2026-06-16T01:42:37.693", "lastUpdated" : "2026-06-16T11:15:30.528", "ingestTimestamp" : "2026-06-16T01:42:37.693", "mongoId" : "6a3080e2f292fd229c068078", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Coverage driven verification", "Testplan creation", "Testbench architecture", "Regression suite development", "Debugging", "Problem-solving", "SOC Verification", "System Verilog", "Python", "Scripting", "Technical leadership", "Framework programming", "Flow programming", "Verification flows", "Emulation flows", "System-level issues resolution", "Advanced verification methodologies", "Simulation environments", "Emulation environments" ], "skillCount" : 19, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 1.0, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "68c2e436f8b1b0376634c802", "title" : "ASIC Verification Engineer, Blink/Ring ASIC Team", "company" : "Amazon Development Center Taiwan Limited", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 2200000.0, "max" : 3500000.0, "currency" : "TWD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Senior ASIC Verification Engineers in Hsinchu City, Taiwan, adjusted for the technology industry and large company size." }, "location" : "Hsinchu City, TWN", "locations" : [ "Hsinchu City, TWN" ], "timestamp" : "2026-06-15T05:25:49.242", "fingerprint" : "56494f2ae4c94c53089192f4e749cc52bdc44cf951d85593b7648c0f51835d2d", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3073145/apply", "externalId" : "03e1c617-eccb-4c4d-8430-1293fe7d6030", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Hsinchu City", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "24.8402128,121.0177998" } ], "locationText" : "Hsinchu City, Taiwan", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 6, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "C, C++, Python, TCL, System Verilog, UVM", "professionalSkills" : [ "Architectural modeling", "Micro-architectural trade-offs", "Silicon validation", "Post-silicon validation" ], "hardSkillsList" : [ "Block level testplans", "System level testplans", "Traffic generators", "Scoreboards" ], "hardSkills" : [ { "name" : "Block level testplans", "level" : "intermediate" }, { "name" : "System level testplans", "level" : "intermediate" }, { "name" : "Traffic generators", "level" : "intermediate" }, { "name" : "Scoreboards", "level" : "intermediate" } ], "majorSkills" : "ASIC Verification, SoC Verification, System Verilog, UVM", "majorSkillsList" : [ "ASIC Verification", "SoC Verification", "System Verilog", "UVM" ], "coreResponsibilities" : "Build bit accurate C models, Evaluate block testability, Evaluate sub-systems testability, Write block level testplans, Write system level testplans, Build assertions, Build traffic generators, Build scoreboards, Execute testplans, Perform debug", "teamCollaboration" : "Vertically integrated team", "domainKnowledge" : "Image processing; AI; Video processing; Low power communications; CMOS fabrication", "domainList" : [ "image-processing", "ai", "video-processing", "low-power-communications", "cmos-fabrication" ], "domainSpecificKnowledge" : [ "Image processing", "AI", "Video processing", "Low power communications", "CMOS fabrication" ], "communicationSkills" : "Written skills; Verbal skills", "problemSolvingSkills" : "Rigorous debug", "qualificationsBasic" : "Bachelor's degree, 6+ years experience digital verification, 3+ years C/C++, 3+ years scripting, 6+ years System Verilog, 6+ years UVM", "qualificationsPreferred" : "Master's or PH. D, 8+ years experience digital verification, Familiarity with formal verification, Lab debug experience, FPGA debug experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Our verification team is involved in early architectural and micro-architectural trade-offs to reduce time-to-revenue by shortening the DV cycle. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Use and/or build bit accurate C models - Evaluate block and sub-systems for testability/verifiability - Write comprehensive block and system level testplans - Build assertions, traffic generators and scoreboards - Execute testplans and perform rigorous debug Basic Qualifications: - Bachelor's degree in Electrical / Computer Engineering or related field - 6+ years experience in digital verification, preferably in image processor, SoC/Interfaces - 3+ years of experience in C/C++ and scripting (Python or TCL) - 6+ years experience in System Verilog or UVM Preferred Qualifications: - Master's or PH.D in Computer Engineering - 8+ years of experience in digital verification, preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - Strong written and verbal skills Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "ASIC Verification Engineer, Blink/Ring ASIC Team at Amazon Development Center Taiwan Limited. Skills: ASIC Verification, SoC Verification, System Verilog, UVM. Build bit accurate C models. Evaluate block testability", "postedDate" : "2026-06-14T06:37:47.347", "createdAt" : "2026-06-14T06:37:47.347", "lastUpdated" : "2026-06-15T05:25:49.242", "ingestTimestamp" : "2026-06-14T06:37:47.347", "mongoId" : "68c2e436f8b1b0376634c802", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3073145/apply", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Block level testplans", "System level testplans", "Traffic generators", "Scoreboards", "ASIC Verification", "SoC Verification", "System Verilog", "UVM", "Architectural modeling", "Micro-architectural trade-offs", "Silicon validation", "Post-silicon validation", "Image processing", "AI", "Video processing", "Low power communications", "CMOS fabrication" ], "skillCount" : 17, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a30609ff292fd229cf9201b", "title" : "Junior ASIC Design Engineer", "company" : "Astera Labs", "industry" : "Technology", "salary" : { "min" : 180000.0, "max" : 270000.0, "currency" : "ILS", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Junior ASIC Design Engineer in Haifa, Israel, adjusted for entry-level seniority and the technology industry." }, "location" : "Haifa, Israel", "locations" : [ "Haifa", "Israel", "Tel Aviv", "Israel" ], "timestamp" : "2026-06-16T07:41:49.897", "fingerprint" : "38417ee06cf83642406e081430d6ac882d5a333bf1af74f1b1773c38cd45f3e3", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/asteralabs/jobs/4704182005", "externalId" : "4704182005", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Haifa", "country" : "Israel", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "32.8191218,34.9983856" } ], "locationText" : "Haifa, Israel", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 0, "experienceMaxYears" : 2, "experienceLevel" : "Entry", "technicalSkills" : "Verilog, SystemVerilog, RTL", "professionalSkills" : [ "Logic design", "Micro-architecture", "Implementation support" ], "hardSkillsList" : [ "Digital design principles", "RTL coding concepts" ], "softSkillsList" : [ "Adapt", "Collaborate" ], "hardSkills" : [ { "name" : "Digital design principles", "level" : "intermediate" }, { "name" : "RTL coding concepts", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Adapt" }, { "name" : "Collaborate" } ], "majorSkills" : "ASIC Design, Digital blocks, Connectivity projects", "majorSkillsList" : [ "ASIC Design", "Digital blocks", "Connectivity projects" ], "coreResponsibilities" : "Own the journey from high-level definition, Tackle complex logic challenges, Transform logic into hardware solutions, Serve as point of contact for logic blocks, Interact with Architecture teams, Interact with Verification teams, Interact with Backend teams, Utilize EDA tools, Utilize quality assurance tools, Ensure designs are robust, Ensure designs are scalable, Ensure designs are power-efficient, Apply design techniques, Meet PPA targets, Contribute to design quality, Participate in design methodology improvements, Participate in tool automation initiatives, Leverage AI assistance tools, Contribute to in-house automation development, Make engineering workflows faster, Make engineering workflows smarter, Collaborate effectively across teams, Ensure seamless integration", "teamCollaboration" : "Interacting with Architecture; Interacting with Verification; Interacting with Backend teams; Collaborate across teams", "domainKnowledge" : "AI infrastructure; Connectivity solutions; Deep-submicron processes", "domainList" : [ "ai-infrastructure", "connectivity-solutions", "deep-submicron-processes" ], "domainSpecificKnowledge" : [ "AI infrastructure", "Connectivity solutions", "Deep-submicron processes" ], "toolProficiency" : [ "Lint", "CDC", "Synthesis", "Timing", "Power" ], "communicationSkills" : "Communication skills", "innovationCreativity" : "Innovation", "problemSolvingSkills" : "Tackle complex logic challenges", "qualificationsBasic" : "Bachelor’s degree in Electrical Engineering, Bachelor’s degree in Computer Engineering, 0–2 years of experience in logic design, Foundational knowledge of Verilog, Foundational knowledge of SystemVerilog, Understanding of digital design principles, Understanding of fundamental RTL coding concepts", "qualificationsPreferred" : "Master's degree in Electrical Engineering, Master's degree in related field, Relevant internships valued, University labs valued, Hands-on academic projects valued", "workSiteFlexibility" : "Onsite", "rawDescription" : "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Junior ASIC Design Engineer, you won't just build chips - you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Responsibilities Design Ownership & Implementation Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams Quality Assurance & Design Optimization Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient Apply design techniques to meet PPA (Power, Performance, Area) targets Contribute to design quality through verification and validation activities Methodology Innovation & Collaboration Participate in design methodology improvements and tool automation initiatives Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter Collaborate effectively across teams to ensure seamless integration Basic Qualifications Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field. Experience: 0–2 years of experience in logic design (relevant internships, university labs, or hands-on academic projects are highly valued). Technical Skills: Foundational knowledge of Verilog and/or SystemVerilog. Strong understanding of digital design principles and fundamental RTL coding concepts. Soft Skills: Excellent communication skills with a strong motivation to learn, adapt, and collaborate effectively within cross-functional teams. Preferred Qualifications Master's degree in Electrical Engineering or related field We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "summaryDescription" : "Junior ASIC Design Engineer at Astera Labs. Skills: ASIC Design, Digital blocks, Connectivity projects. Own the journey from high-level definition. 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S. citizen or national, U. S. permanent resident, Lawfully admitted refugee, Granted asylum", "qualificationsBasic" : "Relocate to internship location, Work 40 hours/week, Commit to 12 week internship, Pursuing Bachelor's or Master's, Graduation date Dec 2026 - May 2028, Understanding of RF fundamentals, Understanding of digital communication systems, Programming skills in Python, Programming skills in C/C++, Familiarity with Verilog, Familiarity with VHDL, Familiarity with circuit simulation concepts", "qualificationsPreferred" : "Coursework in RFIC design, Coursework in digital design, Coursework in communication systems, Experience with Verilog, Experience with VHDL, Experience with circuit simulation tools, Familiarity with verification methodologies", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a Project Kuiper intern, you will work alongside experienced engineers in our RFIC, RF/Communications Systems, or Digital Design Verification teams. This internship offers hands-on experience in cutting-edge satellite communications technology development, from integrated circuit design to system-level implementation and verification. Export Control Requirement Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities - Support engineering teams in development and testing of satellite communication systems and integrated circuits - Assist in creating and executing test procedures for RF components and systems - Help maintain and analyze test data from IC-level to system-level testing - Contribute to verification and validation of RF/mixed-signal circuits and systems - Participate in cross-functional team meetings and technical reviews - Document processes and results - Support automation efforts for testing and verification workflows Basic Qualifications: - Can relocate to where the internship is based - Work 40 hours/week minimum and commit to 12 week internship maximum - Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical field with a graduation date between December 2026 - May 2028. - Understanding of RF fundamentals or digital communication systems - Programming skills in at least one language (e.g., Python, C/C++) - Familiarity with hardware description languages (e.g., Verilog, VHDL) or circuit simulation concepts Preferred Qualifications: - Coursework in RFIC design, digital design, or communication systems - Experience with hardware description languages (e.g., Verilog, VHDL) or circuit simulation tools - Familiarity with verification methodologies (e.g., UVM) or RF test equipment - Knowledge of Linux operating systems and scripting languages - Understanding of satellite communications systems or digital signal processing - Prior project experience in telecommunications, aerospace, or semiconductor industry Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $104,000/year in our lowest geographic market up to $212,200/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits . This position will remain posted until filled. Applicants should apply via our internal or external career site.", "summaryDescription" : "ASIC Engineering Internship (Summer 2026) at Amazon Kuiper Manufacturing Enterprises LLC. Skills: Satellite communication systems, Integrated circuits, RF components. Support development of satellite communication systems. Support testing of satellite communication systems", "postedDate" : "2026-06-13T19:56:56.785", "createdAt" : "2026-06-13T19:56:56.785", "lastUpdated" : "2026-06-15T07:09:39.803", "ingestTimestamp" : "2026-06-13T19:56:56.785", "mongoId" : "68c2e42af8b1b0376634c688", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3076360/apply", "salaryAnnualMin" : 104000, "salaryAnnualMax" : 212200, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "RF fundamentals", "Digital communication systems", "Circuit simulation", "Satellite communication systems", "Integrated circuits", "RF components", "Technical reviews", "Test procedures", "Satellite communication technology", "RFIC design", "Digital design", "Communication systems", "Circuit simulation tools" ], "skillCount" : 13, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Entry", "dataQualityScore" : 0.8888889, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "693c2b8a70f0b99d5843fcfa", "title" : "ASIC Test Engineer", "company" : "Annapurna Labs", "industry" : "Software Development, ASIC, Cloud Computing", "salary" : { "min" : 129800.0, "max" : 212800.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Austin, Texas, USA", "locations" : [ "Austin, Texas, USA" ], "timestamp" : "2026-06-14T22:23:51.717", "fingerprint" : "c766086b4015b6b682bcd0e67d6f2bff9e2adfe47960e6ad284635ddcae2c038", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3139009/apply", "externalId" : "3594309b-a223-486e-92c2-2698a63f7b8f", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Austin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.2711286,-97.7436995" } ], "locationText" : "Austin, Texas, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 2, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "technicalSkills" : "C/C++, VBA, VBT, Lua, Python, Shell scripting", "professionalSkills" : [ "Silicon operations", "Hardware development", "Software development", "Tool development", "System architecture" ], "hardSkillsList" : [ "ATE platforms", "Structural testing", "Mission profile testing", "Virtualized machines", "Microcontrollers" ], "softSkillsList" : [ "Curious mindset" ], "hardSkills" : [ { "name" : "ATE platforms", "level" : "intermediate" }, { "name" : "Structural testing", "level" : "intermediate" }, { "name" : "Mission profile testing", "level" : "intermediate" }, { "name" : "Virtualized machines", "level" : "intermediate" }, { "name" : "Microcontrollers", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Curious mindset" } ], "majorSkills" : "ASIC Test, ATE platforms, System level test", "majorSkillsList" : [ "ASIC Test", "ATE platforms", "System level test" ], "coreResponsibilities" : "Develop hardware for probe, Develop hardware for final test, Develop hardware for system level test, Develop software for each insert, Develop general tool support, Design and code solutions, Create metrics, Implement automation, Resolve root cause of defects, Build high-impact solutions, Participate in design discussions, Participate in code review, Communicate with stakeholders, Work cross-functionally, Drive business decisions", "teamCollaboration" : "Cross-functionally; Internal stakeholders; External stakeholders", "domainKnowledge" : "Machine learning accelerators; Server architecture; Process nodes; Virtualized machines; Microcontrollers", "domainList" : [ "machine-learning-accelerators", "server-architecture", "process-nodes", "virtualized-machines", "microcontrollers" ], "domainSpecificKnowledge" : [ "Machine learning accelerators", "Server architecture", "Process nodes", "Virtualized machines", "Microcontrollers" ], "toolProficiency" : [ "Advantest 93K", "Teradyne IGXL", "JMP", "Optimal plus" ], "continuousLearning" : "Mentorship", "problemSolvingSkills" : "Root cause analysis", "outcomesObjectives" : "Create extremely low DPPM product-line", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, Experience in C/C++, Experience in Microsoft VBA/VBT, Experience in terminal shell environments, Experience with Advantest 93K, Experience with Teradyne IGXL based testers, Experience with other system level testers", "qualificationsPreferred" : "Familiar with Lua, Familiar with Python, Familiar with shell scripting, Compilers, generating SOs and DLLs, Experience with JMP, Experience with Optimal plus", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Annapurna Labs develops the silicon used in our most advanced machine learning accelerator servers, utilizing the latest process nodes and massively scaled server clusters to provide the best hardware platform to customers for both inference and training workloads. We are seeking a mid-career semiconductor test engineer with a background in classic ATE platforms to create a clean running extremely low DPPM product-line forming the foundation to our servers. As our final product is a server, not just the silicon, you will find yourself stretching beyond structural testing and incorporating a lot more mission profile testing, utilizing a variety of external controlling ICs, porting server management and customer run-time software, including the use of virtualized machines and specific microcontrollers found in the end application. As such a curious mindset and an urge to learn system architecture will greatly benefit you in this role. We are a nurturing and supporting group that will ensure you have access to all tools, code and mentorship needed to become effective in this exciting new way of working! Key job responsibilities - Hardware development for probe, final test, system level test. - Software development for each insert - General tool development support A day in the life As you design and code solutions to help our team drive efficiencies in software architecture, you’ll create metrics, implement automation and other improvements, and resolve the root cause of software defects. You’ll also: - Build high-impact solutions to deliver to our large customer base. - Participate in design discussions, code review, and communicate with internal and external stakeholders. - Work cross-functionally to help drive business decisions with your technical input. - Work in a startup-like development environment, where you’re always working on the most important stuff. About the team Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. About AWS Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses. Diverse Experiences AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying. Work/Life Balance We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud. Inclusive Team Culture Here at AWS, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness. Mentorship & Career Growth We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional. Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future. Basic Qualifications: - Bachelor's degree in Electrical Engineering or a related field - Experience in C/C++ and/or Microsoft VBA/VBT and terminal shell environments - Experience with Advantest 93K, Teradyne IGXL based testers or other system level testers Preferred Qualifications: - Familiar with Lua, Python, shell scripting - Compilers, generating SOs and DLLs from large code bases - Experience with JMP, Optimal plus. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $129,800/year in our lowest geographic market up to $212,800/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits . This position will remain posted until filled. Applicants should apply via our internal or external career site.", "summaryDescription" : "ASIC Test Engineer at Annapurna Labs. Skills: ASIC Test, ATE platforms, System level test. Develop hardware for probe. Develop hardware for final test", "postedDate" : "2026-06-13T01:49:03.899", "createdAt" : "2026-06-13T01:49:03.899", "lastUpdated" : "2026-06-14T22:23:51.717", "ingestTimestamp" : "2026-06-13T01:49:03.899", "mongoId" : "693c2b8a70f0b99d5843fcfa", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3139009/apply", "salaryAnnualMin" : 129800, "salaryAnnualMax" : 212800, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "ATE platforms", "Structural testing", "Mission profile testing", "Virtualized machines", "Microcontrollers", "Curious mindset", "ASIC Test", "System level test", "Silicon operations", "Hardware development", "Software development", "Tool development", "System architecture", "Machine learning accelerators", "Server architecture", "Process nodes", "Advantest 93K", "Teradyne IGXL", "JMP", "Optimal plus" ], "skillCount" : 20, "jobCategory" : "engineering", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "69e1043a2beec4dd3def1c5b", "title" : "ASIC Design Engineer", "company" : "Evi Technologies Limited", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 65000.0, "max" : 95000.0, "currency" : "GBP", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for an ASIC Design Engineer in Cambridge, UK, adjusted for mid-seniority and the technology industry." }, "location" : "Cambridge, England, GBR", "locations" : [ "Cambridge, England, GBR" ], "timestamp" : "2026-06-15T02:56:51.677", "fingerprint" : "34a2ccfd7306b7e13ea6a2f2e805c488ebd16b9a288d976e64e361718686c768", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10387315/apply", "externalId" : "29cc8e76-1163-4a7e-9409-2533ed995736", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Cambridge", "state" : "England", "country" : "United Kingdom", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "52.1975846,0.1391537" } ], "locationText" : "Cambridge, England, United Kingdom", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "technicalSkills" : "System Verilog, Verilog, Python, Perl", "professionalSkills" : [ "Micro-architecture specs", "Power analysis", "Performance analysis", "Area estimation" ], "hardSkillsList" : [ "RTL design", "DFT", "UPF" ], "hardSkills" : [ { "name" : "RTL design", "level" : "intermediate" }, { "name" : "DFT", "level" : "intermediate" }, { "name" : "UPF", "level" : "intermediate" } ], "majorSkills" : "ASIC Design, RTL, Verification", "majorSkillsList" : [ "ASIC Design", "RTL", "Verification" ], "coreResponsibilities" : "Write micro-architecture specs, Solicit feedback, Link to KPIs, Execute on design specifications, Deliver high quality RTL, Evaluate 3rd party IP blocks, Estimate power, Estimate performance, Estimate area, Ensure quality, Run front-end tools, Track results, Work with pre-silicon verification teams, Assist in defining test-plans, Assist in defining test-benches, Work with post-silicon validation teams, Define test-plans, Execute test-plans", "teamCollaboration" : "Vertically integrated team; Pre-silicon verification teams; Post-silicon validation teams", "domainKnowledge" : "Battery powered devices; SoCs; AI; Video processing; Low power communications; CMOS fabrication", "domainList" : [ "battery-powered-devices", "socs", "ai", "video-processing", "low-power-communications", "cmos-fabrication" ], "domainSpecificKnowledge" : [ "Battery powered devices", "SoCs", "AI", "Video processing", "Low power communications", "CMOS fabrication" ], "toolProficiency" : [ "Lint", "CDC", "RDC", "STA", "Synthesis" ], "documentationSkills" : "Micro-architecture specs", "innovationCreativity" : "Innovators; Invent; Simplify; Build", "problemSolvingSkills" : "Debugging; Design problems", "qualificationsBasic" : "Experience identifying bugs, Debugging skills, Experience with front-end design tools, Lint, CDC, RDC, Ability to write micro-architectural specs, System Verilog, Verilog", "qualificationsPreferred" : "Bachelor's degree in Electrical or Communications Engineering, Experience with industry standard tools, Scripting languages for automation, Python, Perl, Experience with hardware-software interfaces, Using formal verification tools", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Write micro-architecture specs and solicit feedback/link to KPIs from architecture team - Execute on design specifications to deliver high quality RTL - Evaluate 3rd party IP blocks - Estimate power, performance, and area for significant IPs early in design cycle - Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon verification teams to assist in defining test-plans/test-benches - Work with post-silicon validation teams to define and execute on test-plans Basic Qualifications: - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills - Experience with front-end design tools (Lint, CDC, RDC and lint) - Ability to write detailed micro-architectural specs which work through the design problems before coding (System Verilog, Verilog). Preferred Qualifications: - Bachelor's degree in Electrical or Communications Engineering or a related field - Experience with industry standard tools and scripting languages (Python or Perl) for automation - Experience with hardware-software interfaces - Using formal verification tools to enhance RTL quality before testing. Amazon is an equal opportunities employer. We believe passionately that employing a diverse workforce is central to our success. We make recruiting decisions based on your experience and skills. We value your passion to discover, invent, simplify and build. Protecting your privacy and the security of your data is a longstanding top priority for Amazon. Please consult our Privacy Notice ( https://www.amazon.jobs/en/privacy_page ) to know more about how we collect, use and transfer the personal data of our candidates. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "ASIC Design Engineer at Evi Technologies Limited. Skills: ASIC Design, RTL, Verification. Write micro-architecture specs. Solicit feedback", "postedDate" : "2026-06-13T06:05:56.897", "createdAt" : "2026-06-13T06:05:56.897", "lastUpdated" : "2026-06-15T02:56:51.677", "ingestTimestamp" : "2026-06-13T06:05:56.897", "mongoId" : "69e1043a2beec4dd3def1c5b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10387315/apply", "salaryBand" : "50k-75k", "hasSalary" : false, "allSkills" : [ "RTL design", "DFT", "UPF", "ASIC Design", "RTL", "Verification", "Micro-architecture specs", "Power analysis", "Performance analysis", "Area estimation", "Battery powered devices", "SoCs", "AI", "Video processing", "Low power communications", "CMOS fabrication", "Lint", "CDC", "RDC", "STA", "Synthesis" ], "skillCount" : 21, "jobCategory" : "other", "dataQualityScore" : 0.8888889, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "69ce5e1f9bc74574cb6752b9", "title" : "Softgoods Engineering Technologist", "company" : "Nexus", "industry" : "Government", "salary" : { "min" : 125000.0, "max" : 175000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Senior Softgoods Engineering Technologist in Houston, adjusted for the aerospace industry and company size." }, "location" : "United States-Texas-Houston", "locations" : [ "United States-Texas-Houston" ], "timestamp" : "2026-06-15T04:49:37.594", "fingerprint" : "6a9c067a521a38a1bfd717d21b61a44bdaf211e0e00189e33df38768fd20019b", "source" : "taleo", "language" : "en", "applyUrl" : "https://jacobs.taleo.net/careersection/ex/jobdetail.ftl?job=322157", "externalId" : "322157", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Houston", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "29.7589382,-95.3676974" } ], "locationText" : "Houston, Texas, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "High School", "technicalSkills" : "Sewing machines, Laser cutters, Fabric welders, 3D printers, Band saws, Drills, Adobe, AutoCAD, Rhino CAD", "professionalSkills" : [ "Design concepts", "Requirements understanding", "Task ownership", "Machine maintenance", "Machine repair", "Custom modifications", "Pattern creation", "Mockup development", "Fit verification", "Function verification", "Fabrication drawings interpretation", "Product design" ], "hardSkillsList" : [ "Sewing", "Fabrication", "CAD software", "Laser cutting", "3D printing", "Fabric welding" ], "hardSkills" : [ { "name" : "Sewing", "level" : "intermediate" }, { "name" : "Fabrication", "level" : "intermediate" }, { "name" : "CAD software", "level" : "intermediate" }, { "name" : "Laser cutting", "level" : "intermediate" }, { "name" : "3D printing", "level" : "intermediate" }, { "name" : "Fabric welding", "level" : "intermediate" } ], "majorSkills" : "Softgoods design, Softgoods fabrication, CAD software, Aerospace product design", "majorSkillsList" : [ "Softgoods design", "Softgoods fabrication", "CAD software", "Aerospace product design" ], "coreResponsibilities" : "Design softgoods articles, Develop softgoods articles, Fabricate softgoods articles, Present design concepts, Collaborate with engineers, Collaborate with designers, Understand requirements, Complete design tasks, Perform sewing machine maintenance, Perform sewing machine repair, Modify sewing machines, Create patterns, Develop mockups, Verify fit, Verify function, Interpret fabrication drawings, Assemble sewn products, Review fabrication drawings, Seek manufacturing techniques, Seek innovative materials, Fabricate softgoods, Install softgoods", "teamCollaboration" : "With engineers; With designers", "domainKnowledge" : "Manned spaceflight program; Deep space exploration; Aerospace product design; NASA/JSC Softgoods; JETS Engineering Life Cycle", "domainList" : [ "manned-spaceflight-program", "deep-space-exploration", "aerospace-product-design", "nasa-jsc-softgoods", "jets-engineering-life-cycle" ], "domainSpecificKnowledge" : [ "Manned spaceflight program", "Deep space exploration", "Aerospace product design", "NASA/JSC Softgoods", "JETS Engineering Life Cycle" ], "toolProficiency" : [ "Adobe", "AutoCAD", "Rhino CAD", "Laser cutters", "Fabric welders", "3D printers" ], "communicationSkills" : "Present design concepts", "documentationSkills" : "Fabrication drawings", "innovationCreativity" : "New manufacturing techniques; Innovative materials", "problemSolvingSkills" : "Devise solutions; Complex design problems", "specialRequirements" : "Ability to lift, Transport materials, Work in confined spaces, Scale steps, Scale ladders, Travel to NASA centers, U.S. Citizenship, Permanent Residency, Background investigation, Lift up to 25 lbs, Work outside normal schedule, Adjust schedule", "qualificationsBasic" : "15 years of experience, BS in Engineering Technology, 5 years of experience, 3+ years softgoods lab, 3+ years softgoods design, 3+ years softgoods fabrication, Proficiency utilizing Adobe, Proficiency utilizing AutoCAD, Proficiency utilizing Rhino CAD", "qualificationsPreferred" : "BA in Industrial Design, BFA in Industrial Design, BS in Industrial Design, Aerospace product design experience, Fabricating processes experience, Prototyping experience, Flight softgood products experience, Adobe CAD software experience, AutoCAD CAD software experience, Rhino CAD software experience, Familiar with NASA/JSC Softgoods, Familiar with JETS Engineering Life Cycle", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Are you passionate about human space exploration, understanding the universe's origins, and working with a passionate and diverse team to make a difference? If you are, we need you! We need your talent, teamwork, and energy to help us achieve great things that inspire people all over the globe. We need you to bring creative ideas and diverse backgrounds to help us envision, shape, and deliver systems that will enable space exploration while benefiting people here on Earth. We are excited about what we do, and we need you on our team as we take on exciting challenges for NASA’s pursuits in deep space exploration. As NASA’s largest engineering solutions provider working with NASA at centers across the United States. We have an exciting opportunity for a Softgoods Engineering Technologist to join the team with JETS II teammate company, Nexus. The Softgoods Engineering Technologist will: Design, develop, and fabricate new and innovative functional softgoods articles for the manned spaceflight program such as stowage solutions, structural inflatables, ancillary space suit equipment, thermal blankets, and general deep space product design Clearly and thoroughly present design concepts and considerations Collaborate with engineers and designers to understand requirements of working on a variety of systems and hardware Take ownership and show initiative to complete softgoods design tasks Perform sewing machine maintenance, repair, and custom modifications to tailor the sewing machine for unique stitching operations Create patterns and develop mockups for verifying fit and function of softgood articles Interpret fabrication drawings to assemble sewn products, and review fabrication drawings before final release for flight fabrication Seek new manufacturing techniques and innovative materials Occasionally travel to other NASA centers to perform softgoods fabrication and installation Ability to lift and transport materials and equipment Ability to work in confined spaces, scale steps and ladders Perform other duties as required Requisition Qualifications: This position has been posted at multiple levels. Depending on the candidate's experience, requirements, and business needs, we reserve the right to consider candidates at any level for which this position has been advertised. Typically requires a HS diploma and 15 years of experience or BS in Engineering Technology or related field and 5 years of experience. 3+ years' experience in a softgoods lab environment with emphasis in softgoods design and fabrication Demonstrated capability to independently devise solutions to complex design problems by their own efforts, and by soliciting inputs from other technical experts Expertise in a wide range of hands-on fabrication – sewing machines, laser cutters, fabric welders, 3D printers, band saws, drills, etc. Demonstrated success working with a team Proficiency utilizing Adobe, AutoCAD, and Rhino CAD software Requisition Preferences: BA, BFA, or BS in Industrial Design or equivalent is desired Experienced in aerospace product design processes including ability to read, understand, and create fabrication drawings Experienced with fabricating processes for prototyping and flight softgood products Experienced in Adobe, AutoCAD, and Rhino CAD software Familiar with the NASA/JSC Softgoods design and development and JETS Engineering Life Cycle processes Why Join Our Team? In addition to exciting career opportunities, we also have: Excellent personal and professional career growth 9/80 work schedule (every other Friday off), when applicable Onsite cafeteria (breakfast & lunch) Much, much more! For more information on our partnership with NASA at Johnson Space Center (JSC), please visit www.wehavespaceforyou.com Proof of U.S. Citizenship or US Permanent Residency may be a requirement for this position Must be able to complete a U.S. government background investigation Management has the prerogative to select at any level for which the position is advertised Essential Functions Work Environment Generally, an office environment, but can involve inside or outside work depending on task. Physical Requirements Work may involve sitting or standing for extended periods (90% of time). May require lifting and carrying up to 25 lbs. (5% of time). Equipment and Machines Standard office equipment (PC, telephone, printer, etc.). Attendance Regular attendance in accordance with established work schedule is critical. Ability to work outside normal schedule and adjust schedule to meet peak periods and surge requirements. Other Essential Functions Professional behavior that enhances productivity and promotes teamwork and cooperation. Grooming and dress must be appropriate for the position and must not impose a safety risk/hazard to the employee or others. #JETS #JETSII United States-Texas-Houston-20331-ESCG", "summaryDescription" : "Softgoods Engineering Technologist at Nexus. Skills: Softgoods design, Softgoods fabrication, CAD software, Aerospace product design. Design softgoods articles. Develop softgoods articles", "createdAt" : "2026-06-14T00:39:25.785", "lastUpdated" : "2026-06-15T04:49:37.594", "ingestTimestamp" : "2026-06-14T00:39:25.785", "mongoId" : "69ce5e1f9bc74574cb6752b9", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 125000, "salaryAnnualMax" : 175000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Sewing", "Fabrication", "CAD software", "Laser cutting", "3D printing", "Fabric welding", "Softgoods design", "Softgoods fabrication", "Aerospace product design", "Design concepts", "Requirements understanding", "Task ownership", "Machine maintenance", "Machine repair", "Custom modifications", "Pattern creation", "Mockup development", "Fit verification", "Function verification", "Fabrication drawings interpretation", "Product design", "Manned spaceflight program", "Deep space exploration", "NASA/JSC Softgoods", "JETS Engineering Life Cycle", "Adobe", "AutoCAD", "Rhino CAD", "Laser cutters", "Fabric welders", "3D printers" ], "skillCount" : 31, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.7777778, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Aerospace", "llmIndustryConfidence" : 0.95 }, { "id" : "6a25146374d8ee00a00bb795", "title" : "Manager, ASIC Sustaining Engineering, Silicon Operations", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Project/Program/Product Management--Non-Tech, Technical Program Management, alexa and amazon devices", "salary" : { "min" : 188100.0, "max" : 254500.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Sunnyvale, California, USA", "locations" : [ "Sunnyvale, California, USA" ], "timestamp" : "2026-06-16T02:31:10.897", "fingerprint" : "13c9edad2061c93830d4ae49a9816fa0e007ed778273cc6d155568a5a7b94e9b", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10440379/apply", "externalId" : "d7941625-42d7-4bfb-9d41-b1546071f1aa", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceLevel" : "Manager", "technicalSkills" : "Semiconductor manufacturing, ASIC, Silicon, Process control, Yield enhancement, Failure analysis, Statistical process control, Data analysis, Manufacturing execution systems, Python, SQL", "professionalSkills" : [ "Problem-solving", "Analytical skills", "Project management", "Cross-functional collaboration" ], "hardSkillsList" : [ "Semiconductor fabrication", "Statistical analysis", "Root cause analysis" ], "hardSkills" : [ { "name" : "Semiconductor fabrication", "level" : "intermediate" }, { "name" : "Statistical analysis", "level" : "intermediate" }, { "name" : "Root cause analysis", "level" : "intermediate" } ], "majorSkills" : "ASIC Sustaining Engineering, Silicon Operations, Semiconductor Manufacturing", "majorSkillsList" : [ "ASIC Sustaining Engineering", "Silicon Operations", "Semiconductor Manufacturing" ], "coreResponsibilities" : "Manage ASIC sustaining engineering activities, Drive silicon operations improvements, Analyze manufacturing data, Identify and resolve yield issues, Implement process control strategies, Collaborate with cross-functional teams, Develop and maintain manufacturing documentation, Support new product introductions", "teamCollaboration" : "Cross-functional teams; Engineering teams; Manufacturing teams; Product teams", "projectManagementSkills" : [ "Agile methodologies", "Project planning", "Risk management" ], "domainKnowledge" : "Semiconductor manufacturing; ASIC design; Silicon technology; Process control; Yield management; Failure analysis; Manufacturing execution systems", "domainList" : [ "semiconductor-manufacturing", "asic-design", "silicon-technology", "process-control", "yield-management", "failure-analysis", "manufacturing-execution-systems" ], "domainSpecificKnowledge" : [ "Semiconductor manufacturing", "ASIC design", "Silicon technology", "Process control", "Yield management", "Failure analysis", "Manufacturing execution systems" ], "toolProficiency" : [ "JIRA", "SQL", "Python" ], "communicationSkills" : "Technical presentations; Status reports", "documentationSkills" : "Technical documentation; Process documentation", "problemSolvingSkills" : "Root cause analysis; Troubleshooting; Data analysis", "outcomesObjectives" : "Improve manufacturing yield; Reduce production costs; Enhance product reliability; Ensure timely product delivery", "qualificationsBasic" : "Bachelor's degree or equivalent practical experience, 5+ years of experience in semiconductor manufacturing, Experience with ASIC sustaining engineering, Experience with silicon operations", "qualificationsPreferred" : "Master's degree or PhD, Experience with yield enhancement, Experience with process control, Experience with failure analysis, Experience with manufacturing execution systems (MES)", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Leo is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. The Silicon Operations team is seeking a Manager,ASIC Sustaining Engineer who has the responsibility for Yield improvement to meet or beat target and Root Cause Analysis for Yield excursions across Wafer, Assembly and Test. Use statistical tools and data analysis to identify yield limiters and trends in electrical test and in-line inspection data. Conduct failure analysis (FA) on defective wafers and devices to identify the source of, or prevent, yield excursions. Design and execute experiments (DOE) to optimize manufacturing processes and reduce particle contamination. Partner with process, equipment, and design engineers to implement solutions to improve, maintain, or troubleshoot production lines. Install, qualify, and maintain in-line defect inspection and review equipment. Create and maintain specifications, process documentation, and best-known methods Key job responsibilities Lead team to identify root cause for chip performance / yield / quality issues. Analyze CP test bin / data log to identify failure mode. Electrical failure analysis and physical failure analysis to locate suspect process stage Work with appropriate supplier to define corrective actions / solutions. Trace action implementation to verify effectiveness. Product early-stage design support to help product tape-out smoothly and Si success: Design rule review & assessment for robust product design Layout review or DFM to enlarge manufacturing window Yield window characterization and device sweet spot identification for the best yield / performance process condition. Basic Qualifications: - 5+ years of people management experience - 5+ years of technical program management experience - Bachelor's degree in Engineering, Computer Science, or a related technical field - Experience managing efforts in Unix/Linux environments, distributed systems or developing large-scale web applications Preferred Qualifications: - Knowledge of the AWS product suite - Knowledge of data center infrastructure design, operations, or delivery - Experience communicating across technical and non-technical audiences, including executive level stakeholders or clients - Experience managing projects across cross functional teams, building sustainable processes and coordinating release schedules - Experience with Agile or other program management methodologies Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Sunnyvale - 188,100.00 - 254,500.00 USD annually USA, WA, Bellevue - 163,600.00 - 221,300.00 USD annually", "summaryDescription" : "Manager, ASIC Sustaining Engineering, Silicon Operations at Amazon Kuiper Manufacturing Enterprises LLC. Skills: ASIC Sustaining Engineering, Silicon Operations, Semiconductor Manufacturing. Manage ASIC sustaining engineering activities. Drive silicon operations improvements", "postedDate" : "2026-06-14T20:21:31.739", "createdAt" : "2026-06-14T20:21:31.739", "lastUpdated" : "2026-06-16T02:31:10.897", "ingestTimestamp" : "2026-06-14T20:21:31.739", "mongoId" : "6a25146374d8ee00a00bb795", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10440379/apply", "salaryAnnualMin" : 188100, "salaryAnnualMax" : 254500, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Semiconductor fabrication", "Statistical analysis", "Root cause analysis", "ASIC Sustaining Engineering", "Silicon Operations", "Semiconductor Manufacturing", "Problem-solving", "Analytical skills", "Project management", "Cross-functional collaboration", "Agile methodologies", "Project planning", "Risk management", "Semiconductor manufacturing", "ASIC design", "Silicon technology", "Process control", "Yield management", "Failure analysis", "Manufacturing execution systems", "JIRA", "SQL", "Python" ], "skillCount" : 23, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Manager", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a2c7b5d74d8ee00a0949547", "title" : "Distinguished Engineer, ASIC (CONTRACT)", "company" : "Butterfly Network", "industry" : "Manufacturing", "salary" : { "min" : 300000.0, "max" : 500000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for an Executive-level Distinguished Engineer in the Technology industry in Burlington, United States, adjusted for company size and contract employment type." }, "location" : "Burlington, Massachusetts, United States", "locations" : [ "Burlington", "Massachusetts", "United States", "New York", "New York", "United States", "Other", "United States - Remote" ], "timestamp" : "2026-06-15T08:13:21.122", "fingerprint" : "339add01e543196359cc5de6cc19b3b42dd2b110aad9b78929e415ea5b70e30b", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://www.butterflynetwork.com/careers?gh_jid=7753260003", "externalId" : "7753260003", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Burlington", "state" : "Massachusetts", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "hybrid", "geo" : "42.5048167,-71.1956111" } ], "locationText" : "Burlington, Massachusetts, United States", "employmentType" : "CONTRACT", "minimumEducation" : "BS/MS/PhD", "experienceMinYears" : 8, "experienceMaxYears" : 12, "experienceLevel" : "Senior", "technicalSkills" : "SystemVerilog, Verilog, DSP, AI, SRAM, IP integration", "professionalSkills" : [ "Architecture", "Tradeoffs", "Implementation", "Verification", "Signoff", "Handoff", "Integration", "Data paths", "Interfaces", "Pipelines", "Compute", "Accelerators", "Fabrics" ], "hardSkillsList" : [ "Digital IC design", "ASIC design", "SoC design", "RTL design", "Timing closure", "Power-aware design", "PPA analysis", "Digital signal processing", "High-speed interface design", "System-on-a-chip logic", "Data path design", "Control logic design", "State machine design", "Streaming interface design", "Memory hierarchy design", "Hardware-firmware interface design", "Register map design", "Control path design", "Status path design", "Data plane design", "Compute pipeline design", "Beamforming pipeline design", "AI accelerator design", "MPU integration", "EFPGA fabric integration" ], "hardSkills" : [ { "name" : "Digital IC design", "level" : "intermediate" }, { "name" : "ASIC design", "level" : "intermediate" }, { "name" : "SoC design", "level" : "intermediate" }, { "name" : "RTL design", "level" : "intermediate" }, { "name" : "Timing closure", "level" : "intermediate" }, { "name" : "Power-aware design", "level" : "intermediate" }, { "name" : "PPA analysis", "level" : "intermediate" }, { "name" : "Digital signal processing", "level" : "intermediate" }, { "name" : "High-speed interface design", "level" : "intermediate" }, { "name" : "System-on-a-chip logic", "level" : "intermediate" }, { "name" : "Data path design", "level" : "intermediate" }, { "name" : "Control logic design", "level" : "intermediate" }, { "name" : "State machine design", "level" : "intermediate" }, { "name" : "Streaming interface design", "level" : "intermediate" }, { "name" : "Memory hierarchy design", "level" : "intermediate" }, { "name" : "Hardware-firmware interface design", "level" : "intermediate" }, { "name" : "Register map design", "level" : "intermediate" }, { "name" : "Control path design", "level" : "intermediate" }, { "name" : "Status path design", "level" : "intermediate" }, { "name" : "Data plane design", "level" : "intermediate" }, { "name" : "Compute pipeline design", "level" : "intermediate" }, { "name" : "Beamforming pipeline design", "level" : "intermediate" }, { "name" : "AI accelerator design", "level" : "intermediate" }, { "name" : "MPU integration", "level" : "intermediate" }, { "name" : "EFPGA fabric integration", "level" : "intermediate" } ], "majorSkills" : "Digital ASIC Design, RTL Implementation, Verification Signoff, System-on-a-Chip", "majorSkillsList" : [ "Digital ASIC Design", "RTL Implementation", "Verification Signoff", "System-on-a-Chip" ], "coreResponsibilities" : "Design digital signal processing logic, Implement digital signal processing logic, Verify digital signal processing logic, Design high speed interface logic, Implement high speed interface logic, Verify high speed interface logic, Design system-on-a-chip logic, Implement system-on-a-chip logic, Verify system-on-a-chip logic, Own complex digital IC subsystems, Perform PPA tradeoffs, Implement RTL, Achieve verification signoff, Perform tapeout handoff, Architect sustained high-throughput datapaths, Design buffering, Design arbitration, Design backpressure, Perform bandwidth budgeting, Design SRAM/memory hierarchy, Collaborate with verification teams, Validate complex digital architectures, Resolve functional issues, Work cross-functionally with analog teams, Work cross-functionally with systems teams, Work cross-functionally with packaging/board teams, Close chip-level requirements, Close integration details, Define hardware-firmware interfaces, Define register maps, Define control/status paths, Define data-plane contracts, Implement compute-intensive digital pipelines, Design AI accelerators, Integrate AI accelerators, Integrate MPUs, Integrate eFPGA fabrics", "teamCollaboration" : "Cross-functional teams; Verification teams; Analog teams; Systems teams; Packaging/board teams", "domainKnowledge" : "Ultrasound-on-Chip technology; Point-of-care ultrasound; Medical imaging; Ultrasound systems; Beamforming pipelines; Sensor data acquisition; AI accelerators; MPUs; eFPGA fabrics", "domainList" : [ "ultrasound-on-chip-technology", "point-of-care-ultrasound", "medical-imaging", "ultrasound-systems", "beamforming-pipelines", "sensor-data-acquisition", "ai-accelerators", "mpus", "efpga-fabrics" ], "domainSpecificKnowledge" : [ "Ultrasound-on-Chip technology", "Point-of-care ultrasound", "Medical imaging", "Ultrasound systems", "Beamforming pipelines", "Sensor data acquisition", "AI accelerators", "MPUs", "eFPGA fabrics" ], "documentationSkills" : "Register maps", "innovationCreativity" : "Innovation", "problemSolvingSkills" : "Problem-solvers; Resolve functional issues", "qualificationsBasic" : "BS/MS/PhD in EE/CE/CS, 8-12+ years digital IC/ASIC/SoC design, Hands-on RTL ownership, Digital IC implementation understanding, Timing closure implications, Clock/reset domain architecture, Power-aware design, PPA tradeoffs, Own complex digital IC subsystems, RTL implementation, Verification signoff, Tapeout handoff, SystemVerilog/Verilog RTL skills, Silicon-proven digital architectures, Pipelined datapatths, Control logic, State machines, High-throughput streaming interfaces, Architect sustained high-throughput datapaths, Buffering, Arbitration, Backpressure, Bandwidth budgeting, SRAM/memory hierarchy design, Advanced technology nodes (28nm or smaller), Timing closure challenges, Integration of third-party IP, Collaborate with verification teams, Validate complex digital architectures, Resolve functional issues, Cross-functionally with analog teams, Cross-functionally with systems teams, Cross-functionally with packaging/board teams, Close chip-level requirements, Close integration details, Hardware-firmware interfaces, Register maps, Control/status paths, Data-plane contracts", "qualificationsPreferred" : "Experience implementing compute-intensive digital pipelines, DSP pipelines, Beamforming pipelines, AI pipelines, MAC-heavy/vector datapaths, Exposure to medical imaging systems, Exposure to ultrasound systems, Exposure to beamforming pipelines, Exposure to sensor data acquisition architectures, Designing programmable digital compute blocks, Integrating programmable digital compute blocks, AI accelerators, MPUs, EFPGA fabrics, Instruction/control interfaces, Memory hierarchy, Data movement, PPA tradeoffs", "workSiteFlexibility" : "Hybrid", "rawDescription" : "Company Description Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with its proprietary Ultrasound-on-Chip™ semiconductor technology and software solutions. Butterfly first proved its technology in the point-of-care ultrasound market – commercializing the world’s first single-probe, whole-body portable ultrasound device, which is now on its best-selling, third-generation: Butterfly iQ3™. The Company combines its advanced hardware with cloud software and AI, an enterprise workflow solution (Compass AI™) and other offerings to drive adoption of affordable, accessible ultrasound. Butterfly also enables third-party development of imaging AI apps through Butterfly Garden™, its software development kit and AI partnership initiative. In addition to its medical imaging products, Butterfly Embedded™ is the Company’s Ultrasound-on-Chip™ licensing and co-development program designed to enable a new wave of ultrasound-enabled technologies across non-competitive healthcare markets and beyond. Through Butterfly Embedded™, partners can build and scale novel ultrasound applications powered by Butterfly’s proprietary semiconductor chip and software platform. Butterfly’s innovations have been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions and Fast Company’s World Changing Ideas, among other achievements. We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let’s build something extraordinary together! Job Description The role of the Distinguished Engineer, Digital ASIC Designer offers the opportunity to work within the heart of the product development team to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products. Qualifications Baseline skills/experiences/attributes: BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience. 8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership. Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs. Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design. Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces. Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP. Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff. Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts). Ideally, you also have these skills/experiences/attributes (but it’s ok if you don’t!): Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths). Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures. Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs. Values Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in… Patient-Centric Innovators: Our mission is THE mission. Empowered to Impact: Every voice matters. One Team, One Goal: Unity fuels progress. Growth Champions: We embrace challenges. Action-Oriented Achievers: We follow through, every time. Location Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers. For this role, location will depend on candidate qualifications and experience. This role may be based out of one of our U. S. offices, including: SF Bay Area Burlington, MA For this temporary role, we are only considering candidates who are legally authorized to work in the United States and who do not now or in the future require sponsorship or transfer for employment visa status. Butterfly network does not accept agency resumes for this temporary position. Butterfly Network Inc. is an E-Verify Company and is an equal opportunity employer regardless of race, color, ancestry, religion, gender, national origin, sexual orientation, age, citizenship, marital status, disability or Veteran status. All your information will be kept confidential according to EEO guidelines. Butterfly requires security adherence responsibilities from all employees. These include: adhering to all company security policies and procedures, utilize provided company assets securely, and complete all required security awareness training programs. Safeguarding company data and systems from unauthorized access, modification, or", "summaryDescription" : "Distinguished Engineer, ASIC (CONTRACT) at Butterfly Network. Skills: Digital ASIC Design, RTL Implementation, Verification Signoff, System-on-a-Chip. Design digital signal processing logic. Implement digital signal processing logic", "postedDate" : "2026-06-13T20:32:43.377", "createdAt" : "2026-06-13T20:32:43.377", "lastUpdated" : "2026-06-15T08:13:21.122", "ingestTimestamp" : "2026-06-13T20:32:43.377", "mongoId" : "6a2c7b5d74d8ee00a0949547", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 300000, "salaryAnnualMax" : 500000, "salaryBand" : "200k+", "hasSalary" : true, "allSkills" : [ "Digital IC design", "ASIC design", "SoC design", "RTL design", "Timing closure", "Power-aware design", "PPA analysis", "Digital signal processing", "High-speed interface design", "System-on-a-chip logic", "Data path design", "Control logic design", "State machine design", "Streaming interface design", "Memory hierarchy design", "Hardware-firmware interface design", "Register map design", "Control path design", "Status path design", "Data plane design", "Compute pipeline design", "Beamforming pipeline design", "AI accelerator design", "MPU integration", "EFPGA fabric integration", "Digital ASIC Design", "RTL Implementation", "Verification Signoff", "System-on-a-Chip", "Architecture", "Tradeoffs", "Implementation", "Verification", "Signoff", "Handoff", "Integration", "Data paths", "Interfaces", "Pipelines", "Compute", "Accelerators", "Fabrics", "Ultrasound-on-Chip technology", "Point-of-care ultrasound", "Medical imaging", "Ultrasound systems", "Beamforming pipelines", "Sensor data acquisition", "AI accelerators", "MPUs", "eFPGA fabrics" ], "skillCount" : 51, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Executive", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "69d5e4952beec4dd3d931859", "title" : "Senior ASIC Design Engineer", "company" : "Amazon Technologies, Inc.", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 159000.0, "max" : 215300.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "San Diego, California, USA", "locations" : [ "San Diego, California, USA" ], "timestamp" : "2026-06-15T09:52:56.853", "fingerprint" : "4c4d7def052b1c1d6077329abbf6c24dab1c3adcdef406755c918bc043caf7a3", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10385600/apply", "externalId" : "164d406e-fb4b-4b88-862f-5c6a44d52db8", "industryFunction" : { }, "structuredLocations" : [ { "city" : "San Diego", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "32.7174202,-117.1627720" } ], "locationText" : "San Diego, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 7, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "CMOS, DSP, UVM, System C, DPI-C, Matlab", "professionalSkills" : [ "Wireless system architecture", "Chip specification", "Timing optimization", "Power optimization", "Chip level validation", "Trade-off analysis" ], "hardSkillsList" : [ "Digital design", "Low power design", "Wireless system design", "RTL design", "Timing closure", "Power analysis", "Verification test bench" ], "hardSkills" : [ { "name" : "Digital design", "level" : "intermediate" }, { "name" : "Low power design", "level" : "intermediate" }, { "name" : "Wireless system design", "level" : "intermediate" }, { "name" : "RTL design", "level" : "intermediate" }, { "name" : "Timing closure", "level" : "intermediate" }, { "name" : "Power analysis", "level" : "intermediate" }, { "name" : "Verification test bench", "level" : "intermediate" } ], "majorSkills" : "ASIC design, SOC design, Wireless communication", "majorSkillsList" : [ "ASIC design", "SOC design", "Wireless communication" ], "coreResponsibilities" : "Implement wireless system architecture in silicon, Develop solutions optimizing customer experience, Meet power and cost constraints, Drive high quality designs, Create standalone verification test bench, Verify correctness of your block, Participate in System level verification, Ensure block meets DFT targets, Ensure block meets timing targets, Ensure block meets power targets, Learn about systems operating in space, Drive trade-off analysis", "teamCollaboration" : "Customer requirements teams; Wireless system teams; Verification team; Implementation team", "domainKnowledge" : "Low Earth Orbit satellites; Broadband connectivity; Wireless communication systems; Space systems", "domainList" : [ "low-earth-orbit-satellites", "broadband-connectivity", "wireless-communication-systems", "space-systems" ], "domainSpecificKnowledge" : [ "Low Earth Orbit satellites", "Broadband connectivity", "Wireless communication systems", "Space systems" ], "toolProficiency" : [ "UVM", "System C", "DPI-C" ], "continuousLearning" : "Learn about systems operating in space", "innovationCreativity" : "Define a groundbreaking wireless solution", "problemSolvingSkills" : "Trade-off analysis", "specialRequirements" : "U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S.", "outcomesObjectives" : "Optimize customer experience; Meet power and cost constraints; Drive high quality designs; Meet power objectives", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, 7+ years of experience in digital design, Experience with products that have gone to volume production, Experience in low power design techniques", "qualificationsPreferred" : "10+ years of experience in digital design, Familiarity with UVM, Familiarity with Matlab, Ability to write assertions, Exposure to Formal verification", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Role: Be part of Amazon Leo’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation · Develop solutions optimizing customer experience (throughput, latency, and availability) while meeting power and cost constraints · Drive high quality designs for first-time right silicon solutions, and meeting the power objectives · Create standalone verification test bench to verify the correctness of your block · Work with the verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C · Ensure that the block meets DFT, timing and power targets by working closely with the implementation team · Learn about requirements and solutions for systems operating in space · Drive trade-off analysis to benefit customer experience and optimization of resources (costs, power, spectrum) Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Basic Qualifications: - Bachelor's degree in Electrical Engineering or a related field - 7+ years of experience in digital design, preferably in communication systems - Experience with products that have gone to volume production - Experience in low power design techniques Preferred Qualifications: - 10+ years of experience in digital design, preferably in communication systems - Familiarity with UVM and Matlab - Ability to write assertions and exposure to Formal verification - Strong written and verbal skills Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, San Diego - 159,200.00 - 215,300.00 USD annually", "summaryDescription" : "Senior ASIC Design Engineer at Amazon Technologies, Inc.. Skills: ASIC design, SOC design, Wireless communication. Implement wireless system architecture in silicon. Develop solutions optimizing customer experience", "postedDate" : "2026-06-13T17:15:55.737", "createdAt" : "2026-06-13T17:15:55.737", "lastUpdated" : "2026-06-15T09:52:56.853", "ingestTimestamp" : "2026-06-13T17:15:55.737", "mongoId" : "69d5e4952beec4dd3d931859", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10385600/apply", "salaryAnnualMin" : 159000, "salaryAnnualMax" : 215300, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Digital design", "Low power design", "Wireless system design", "RTL design", "Timing closure", "Power analysis", "Verification test bench", "ASIC design", "SOC design", "Wireless communication", "Wireless system architecture", "Chip specification", "Timing optimization", "Power optimization", "Chip level validation", "Trade-off analysis", "Low Earth Orbit satellites", "Broadband connectivity", "Wireless communication systems", "Space systems", "UVM", "System C", "DPI-C" ], "skillCount" : 23, "jobCategory" : "other", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "69d140072beec4dd3ddbe36f", "title" : "DFT Design Engineer, Machine Learning Acceleration", "company" : "Annapurna Labs", "industry" : "Software Development, ASIC, Cloud Computing", "salary" : { "min" : 136000.0, "max" : 184000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Austin, Texas, USA", "locations" : [ "Austin, Texas, USA" ], "timestamp" : "2026-06-15T08:21:32.958", "fingerprint" : "0a390115d03548f047c5590dd8e59bda71c803201e1048791b5ec55609a144fc", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3198587/apply", "externalId" : "3bd93094-2672-408b-915b-ef1f61fb6d54", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Austin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.2711286,-97.7436995" } ], "locationText" : "Austin, Texas, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Verilog, System Verilog, Perl, Python, Tcl", "professionalSkills" : [ "SoC design", "Test quality", "Test time" ], "hardSkillsList" : [ "ATPG", "JTAG", "MBIST" ], "hardSkills" : [ { "name" : "ATPG", "level" : "intermediate" }, { "name" : "JTAG", "level" : "intermediate" }, { "name" : "MBIST", "level" : "intermediate" } ], "majorSkills" : "DFT, SoC design, Machine Learning Acceleration", "majorSkillsList" : [ "DFT", "SoC design", "Machine Learning Acceleration" ], "coreResponsibilities" : "Define DFT architectures, Develop DFT architectures, Work closely with block designers, Work with physical design team, Implement DFT solutions, Perform RTL coding, Perform Verification, Utilize DFT tools, Create test patterns, Participate in Silicon debug efforts, Communicate with team members", "teamCollaboration" : "Block designers; Physical design team; ATE teams; System teams; Multiple disciplines", "domainKnowledge" : "Machine Learning Acceleration; Advanced technology nodes; Silicon defects; Silicon debug; Yield optimization", "domainList" : [ "machine-learning-acceleration", "advanced-technology-nodes", "silicon-defects", "silicon-debug", "yield-optimization" ], "domainSpecificKnowledge" : [ "Machine Learning Acceleration", "Advanced technology nodes", "Silicon defects", "Silicon debug", "Yield optimization" ], "toolProficiency" : [ "DFT tools" ], "innovationCreativity" : "Trailblaze new technologies; Trailblaze new architectures", "problemSolvingSkills" : "Debug silicon", "outcomesObjectives" : "Ensure high design quality; Make right trade-offs", "qualificationsBasic" : "Bachelor's degree in Electrical or Communications Engineering or related field, 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes, Experience with standard tools and practices in DFT, Experience with automation script development", "qualificationsPreferred" : "Master's degree in Electrical or Communications Engineering or related field, Practical experience developing STA constraints for DFT modes, Working directly with PD teams to close timing, Experience with RTL coding and design verification (DV) flows, Experience with gate-level simulation setup and debug with SDF, Silicon debug and yield optimization experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for an ASIC DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs. Key job responsibilities • Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes • Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions • Perform RTL coding and Verification using Verilog/System Verilog • Utilize industry standard DFT tools to create high coverage and cost-effective test patterns to target advanced silicon defects • Participate in Silicon debug efforts alongside ATE and System teams • Communicate and work with team members across multiple disciplines Basic Qualifications: - Bachelor's degree in Electrical or Communications Engineering or a related field - 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes - Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time - Experience with automation script development Preferred Qualifications: - Master's degree in Electrical or Communications Engineering or a related field - Practical experience developing STA constraints for DFT modes and working directly with PD teams to close timing - Experience with RTL coding and design verification (DV) flows - Experience with gate-level simulation setup and debug with SDF - Strong programming and scripting skills in Perl, Python or Tcl - Practical experience with silicon debug and yield optimization Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, TX, Austin - 136,000.00 - 184,000.00 USD annually", "summaryDescription" : "DFT Design Engineer, Machine Learning Acceleration at Annapurna Labs. Skills: DFT, SoC design, Machine Learning Acceleration. Define DFT architectures. Develop DFT architectures", "postedDate" : "2026-06-13T13:04:14.074", "createdAt" : "2026-06-13T13:04:14.074", "lastUpdated" : "2026-06-15T08:21:32.958", "ingestTimestamp" : "2026-06-13T13:04:14.074", "mongoId" : "69d140072beec4dd3ddbe36f", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3198587/apply", "salaryAnnualMin" : 136000, "salaryAnnualMax" : 184000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "ATPG", "JTAG", "MBIST", "DFT", "SoC design", "Machine Learning Acceleration", "Test quality", "Test time", "Advanced technology nodes", "Silicon defects", "Silicon debug", "Yield optimization", "DFT tools" ], "skillCount" : 13, "jobCategory" : "engineering", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "69fa9cc04c40e2acd174f901", "title" : "ASIC Design Engineer II", "company" : "Annapurna Labs", "industry" : "Software Development, ASIC, Cloud Computing", "salary" : { "min" : 157000.0, "max" : 212800.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Cupertino, California, USA", "locations" : [ "Cupertino, California, USA" ], "timestamp" : "2026-06-15T03:53:11.995", "fingerprint" : "81772131019640896a3f0c61ebddab23aaf87c81c3e54753e2742c06053e7641", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10411920/apply", "externalId" : "c5bc1cc6-17ae-40ce-b19e-0c1c6f623c41", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Cupertino", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3228934,-122.0322895" } ], "locationText" : "Cupertino, California, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 2, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "technicalSkills" : "SystemVerilog, RTL", "professionalSkills" : [ "Design optimization", "Trade-off analysis" ], "hardSkillsList" : [ "RTL design", "Microarchitecture implementation", "Synthesis", "Timing clean designs", "Lint checks" ], "softSkillsList" : [ "Innovate" ], "hardSkills" : [ { "name" : "RTL design", "level" : "intermediate" }, { "name" : "Microarchitecture implementation", "level" : "intermediate" }, { "name" : "Synthesis", "level" : "intermediate" }, { "name" : "Timing clean designs", "level" : "intermediate" }, { "name" : "Lint checks", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Innovate" } ], "majorSkills" : "ASIC design, Machine learning acceleration, Hardware design", "majorSkillsList" : [ "ASIC design", "Machine learning acceleration", "Hardware design" ], "coreResponsibilities" : "Develop RTL designs, Implement RTL designs, Conduct design analysis, Conduct microarchitecture analysis, Conduct architecture analysis, Optimize trade-offs, Create microarchitectures, Implement SystemVerilog RTL, Deliver synthesis designs, Deliver timing-clean designs, Execute lint checks, Execute clock domain crossing checks", "teamCollaboration" : "Cross-functional teams; Architects; Fellow designers; Verification specialists; Pre- and post-silicon validation teams; Synthesis experts; Timing experts; Back-end experts", "domainKnowledge" : "Machine learning; Interconnects; DMAs; Memory sub-systems; Accelerator engines; Debug architectures; System level architectures; Cloud-Scale Machine Learning Acceleration", "domainList" : [ "machine-learning", "interconnects", "dmas", "memory-sub-systems", "accelerator-engines", "debug-architectures", "system-level-architectures", "cloud-scale-machine-learning-acceleration" ], "domainSpecificKnowledge" : [ "Machine learning", "Interconnects", "DMAs", "Memory sub-systems", "Accelerator engines", "Debug architectures", "System level architectures", "Cloud-Scale Machine Learning Acceleration" ], "continuousLearning" : "Learning experiences; Knowledge sharing; Mentorship", "innovationCreativity" : "Innovate; Explore new solutions; Contribute to intellectual property; Patents", "problemSolvingSkills" : "Analytical skills; Problem-solving skills", "qualificationsBasic" : "Bachelor's degree or equivalent, 3+ years of non-internship design or architecture experience", "qualificationsPreferred" : "Master's degree in computer science, 3+ years of full software development life cycle experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer, you will: • Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets • Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements • Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints • Execute lint and clock domain crossing quality checks to ensure design integrity • Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts The ideal candidate will have a strong background in ASIC design, proficiency in SystemVerilog, and excellent analytical and problem-solving skills. Experience with high-performance and power-efficient designs is highly desirable. You will thrive in this role if you: - Have a \"Learn and Be Curious\" mindset - Have familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures - Have a strong drive to innovate, explore new solutions, and contribute to the company's intellectual property through patents About the team Inclusive Team Culture Here at AWS, we embrace our differences. We are committed to furthering our culture of inclusion. We have ten employee-led affinity groups, reaching 40,000 employees in over 190 chapters globally. We have innovative benefit offerings, and host annual and ongoing learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon conferences. Amazon’s culture of inclusion is reinforced within our 16 Leadership Principles, which remind team members to seek diverse perspectives, learn and be curious, and earn trust. Work/Life Balance Our team puts a high value on work-life balance. It isn’t about how many hours you spend at home or at work; it’s about the flow you establish that brings energy to both parts of your life. We believe striking the right balance between your personal and professional life is critical to life-long happiness and fulfillment. We offer flexibility in working hours and encourage you to find your own balance between your work and personal lives. Mentorship & Career Growth Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge sharing and mentorship. We care about your career growth and strive to assign projects based on what will help each team member develop into a better-rounded professional and enable them to take on more complex tasks in the future. Basic Qualifications: - Bachelor's degree or equivalent - 3+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience Preferred Qualifications: - Master's degree in computer science or equivalent - 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Cupertino - 157,300.00 - 212,800.00 USD annually USA, TX, Austin - 136,000.00 - 184,000.00 USD annually", "summaryDescription" : "ASIC Design Engineer II at Annapurna Labs. Skills: ASIC design, Machine learning acceleration, Hardware design. Develop RTL designs. Implement RTL designs", "postedDate" : "2026-06-13T06:33:06.775", "createdAt" : "2026-06-13T06:33:06.775", "lastUpdated" : "2026-06-15T03:53:11.995", "ingestTimestamp" : "2026-06-13T06:33:06.775", "mongoId" : "69fa9cc04c40e2acd174f901", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10411920/apply", "salaryAnnualMin" : 157000, "salaryAnnualMax" : 212800, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "RTL design", "Microarchitecture implementation", "Synthesis", "Timing clean designs", "Lint checks", "Innovate", "ASIC design", "Machine learning acceleration", "Hardware design", "Design optimization", "Trade-off analysis", "Machine learning", "Interconnects", "DMAs", "Memory sub-systems", "Accelerator engines", "Debug architectures", "System level architectures", "Cloud-Scale Machine Learning Acceleration" ], "skillCount" : 19, "jobCategory" : "engineering", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Machine Learning" }, { "id" : "69d5e4972beec4dd3d931a71", "title" : "ASIC Design Verification Engineer", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 136000.0, "max" : 184000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Austin, Texas, USA", "locations" : [ "Austin, Texas, USA" ], "timestamp" : "2026-06-15T01:26:32.455", "fingerprint" : "9ba1ca1574b488710f10af9ffd9b62b2d2317fed71cb8a23742dfb4233527476", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10384504/apply", "externalId" : "39133271-b948-4cf9-9106-372c4b7dcde3", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Austin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.2711286,-97.7436995" } ], "locationText" : "Austin, Texas, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Matlab, C, Verilog, SystemVerilog, SystemC, DPI-C", "professionalSkills" : [ "Communication systems", "Modem design", "DSP solutions", "Wireless solution", "Chip SOCs" ], "hardSkillsList" : [ "Formal verification", "Regression testing", "Coverage matrices" ], "hardSkills" : [ { "name" : "Formal verification", "level" : "intermediate" }, { "name" : "Regression testing", "level" : "intermediate" }, { "name" : "Coverage matrices", "level" : "intermediate" } ], "majorSkills" : "ASIC Design Verification, SOC verification, Communication systems", "majorSkillsList" : [ "ASIC Design Verification", "SOC verification", "Communication systems" ], "coreResponsibilities" : "Implement verification environment, Facilitate testing of RTL, Develop test plans, Write tests, Run regressions, Collect coverage matrices, Report progress, Participate in validation of ASIC implementations, Run formal verification, Ensure functional correctness, Work with design team, Work with communication systems team, Participate in system level verification, Construct test benches, Develop automated environment, Run regressions for builds, Maintain organization of database", "teamCollaboration" : "Design team; Communication systems team; Wireless system teams", "domainKnowledge" : "Low Earth Orbit satellites; Digital chip SOCs; CMOS generation technologies; Wireless solution; Modems; High-speed interfaces; Embedded processors; DSP solutions", "domainList" : [ "low-earth-orbit-satellites", "digital-chip-socs", "cmos-generation-technologies", "wireless-solution", "modems", "high-speed-interfaces", "embedded-processors", "dsp-solutions" ], "domainSpecificKnowledge" : [ "Low Earth Orbit satellites", "Digital chip SOCs", "CMOS generation technologies", "Wireless solution", "Modems", "High-speed interfaces", "Embedded processors", "DSP solutions" ], "toolProficiency" : [ "UVM" ], "communicationSkills" : "Written skills; Verbal skills", "innovationCreativity" : "Groundbreaking wireless solution", "problemSolvingSkills" : "Functional correctness", "specialRequirements" : "Export Control Requirement", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, 5+ years in verification, 2+ years in UVM, 2+ years in C, 2+ years in scripting, U. S. citizen or national, U. S. permanent resident, lawfully admitted into the U. S. as a refugee, granted asylum", "qualificationsPreferred" : "Master's degree in Electrical or Communications Engineering, 7+ years in digital verification, Familiarity with Matlab, Modem design verification experience, System C or Matlab model development, DV integration experience, Familiarity with formal verification techniques", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon Leo is Amazon’s low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. The Role: Be part of Amazon Leo’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models · Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program · Participate in the validation of ASIC implementations in Verilog/SystemVerilog · Run formal verification of complex blocks to ensure functional correctness · Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C · Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Basic Qualifications: - Bachelor's degree in Electrical Engineering or a related field - 5+ years in verification preferably in communication systems - 2+ years in UVM, C, and scripting Preferred Qualifications: - Master's degree in Electrical or Communications Engineering or a related field - 7+ years in digital verification, preferably in communication systems - Familiarity with Matlab - Modem design verification experience - System C or Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, TX, Austin - 136,000.00 - 184,000.00 USD annually", "summaryDescription" : "ASIC Design Verification Engineer at Amazon Kuiper Manufacturing Enterprises LLC. Skills: ASIC Design Verification, SOC verification, Communication systems. Implement verification environment. Facilitate testing of RTL", "postedDate" : "2026-06-13T05:39:36.211", "createdAt" : "2026-06-13T05:39:36.211", "lastUpdated" : "2026-06-15T01:26:32.455", "ingestTimestamp" : "2026-06-13T05:39:36.211", "mongoId" : "69d5e4972beec4dd3d931a71", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10384504/apply", "salaryAnnualMin" : 136000, "salaryAnnualMax" : 184000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Formal verification", "Regression testing", "Coverage matrices", "ASIC Design Verification", "SOC verification", "Communication systems", "Modem design", "DSP solutions", "Wireless solution", "Chip SOCs", "Low Earth Orbit satellites", "Digital chip SOCs", "CMOS generation technologies", "Modems", "High-speed interfaces", "Embedded processors", "UVM" ], "skillCount" : 17, "jobCategory" : "other", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "68c2e412f8b1b0376634c1e7", "title" : "Sr. ASIC Design Engineer, Blink/Ring ASIC Team", "company" : "Amazon Development Center Taiwan Limited", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 2200000.0, "max" : 3500000.0, "currency" : "TWD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Senior ASIC Design Engineer in Hsinchu City, Taiwan, adjusted for Amazon's company size and the technology industry." }, "location" : "Hsinchu City, TWN", "locations" : [ "Hsinchu City, TWN" ], "timestamp" : "2026-06-15T06:11:46.935", "fingerprint" : "5d92a9e3af1e67b6120f85e12cc928cd151d039006b3c56157a116b3d46ef4fc", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3073147/apply", "externalId" : "cf497d56-409d-4d13-8183-4f3cb2d02c3f", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Hsinchu City", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "24.8078135,121.0336572" } ], "locationText" : "Hsinchu City, Taiwan", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "RTL, DFT, UPF", "professionalSkills" : [ "Microarchitecture specification", "Architectural modeling", "Post-silicon validation", "Power analysis", "Performance estimation", "Area estimation" ], "hardSkillsList" : [ "Low power design" ], "hardSkills" : [ { "name" : "Low power design", "level" : "intermediate" } ], "majorSkills" : "ASIC Design, SoC Design, RTL Design", "majorSkillsList" : [ "ASIC Design", "SoC Design", "RTL Design" ], "coreResponsibilities" : "Define architecture specifications, Create microarchitecture specifications, Evaluate 3rd party IP blocks, Estimate power, performance, and area, Execute on design specifications, Deliver high quality RTL, Run and track results of front-end tools, Take lead and work with verification teams, Define functional coverage, Work with pre-silicon verification teams, Assist in defining testplans/testbenches, Work with post-silicon validation teams, Define and execute on testplans, Write high quality documents", "teamCollaboration" : "Vertically integrated team; Work with verification teams; Work with pre-silicon verification teams; Work with post-silicon validation teams", "domainKnowledge" : "AI; Video processing; Low power communications; CMOS fabrication technology; Formal verification; Physical implementation", "domainList" : [ "ai", "video-processing", "low-power-communications", "cmos-fabrication-technology", "formal-verification", "physical-implementation" ], "domainSpecificKnowledge" : [ "AI", "Video processing", "Low power communications", "CMOS fabrication technology", "Formal verification", "Physical implementation" ], "toolProficiency" : [ "Synthesis", "Lint" ], "documentationSkills" : "Write high quality documents", "innovationCreativity" : "Innovators will be delighted", "problemSolvingSkills" : "Architectural trade-offs", "outcomesObjectives" : "Reduce time-to-revenue; Shorten time to revenue", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, Communications Engineering or related field, or equivalent experience, Experience with products that have gone to volume production, Hands on experience in low power design techniques, Written and verbal skills", "qualificationsPreferred" : "Master's or Ph. D degree in Electrical / Communications Engineering, Exposure to Formal verification, Experience with physical implementation flows", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Join the team which delivers highly differentiated silicon into Amazon Cameras and Doorbells. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Drive early architectural and micro-architectural trade-offs to reduce time-to-revenue by shortening the time to revenue. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Define architecture specifications based on requirements from product teams - Create microarchitecture specifications suitable for being implemented by junior engineers - Evaluate 3rd party IP blocks - Estimate power, performance, and area for significant IPs early in design cycle - Execute on design specifications to deliver high quality RTL - Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Take the lead and work with verification teams to define functional coverage - Work with pre-silicon verification teams to assist in defining testplans/testbenches - Work with post-silicon validation teams to define and execute on testplans - Write high quality documents to guide and lead a scalable team Basic Qualifications: - Bachelor's degree in Electrical Engineering, Communications Engineering or related field, or equivalent experience - Experience with products that have gone to volume production - Hands on experience in low power design techniques - Strong written and verbal skills Preferred Qualifications: - Master's or Ph.D degree in Electrical / Communications Engineering - Exposure to Formal verification - Experience with physical implementation flows Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "Sr. ASIC Design Engineer, Blink/Ring ASIC Team at Amazon Development Center Taiwan Limited. Skills: ASIC Design, SoC Design, RTL Design. Define architecture specifications. Create microarchitecture specifications", "postedDate" : "2026-06-13T05:44:34.869", "createdAt" : "2026-06-13T05:44:34.869", "lastUpdated" : "2026-06-15T06:11:46.935", "ingestTimestamp" : "2026-06-13T05:44:34.869", "mongoId" : "68c2e412f8b1b0376634c1e7", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3073147/apply", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Low power design", "ASIC Design", "SoC Design", "RTL Design", "Microarchitecture specification", "Architectural modeling", "Post-silicon validation", "Power analysis", "Performance estimation", "Area estimation", "AI", "Video processing", "Low power communications", "CMOS fabrication technology", "Formal verification", "Physical implementation", "Synthesis", "Lint" ], "skillCount" : 18, "jobCategory" : "other", "dataQualityScore" : 1.0, "daysOld" : 2, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a307110f292fd229cff7b48", "title" : "Staff DFT Engineer", "company" : "Renesas Electronics", "industry" : "Semiconductors", "salary" : { "min" : 1750000.0, "max" : 2500000.0, "currency" : "TWD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Senior DFT Engineer in Zhubei, Taiwan, adjusted for industry and company size." }, "location" : "Zhubei, TW", "locations" : [ "Zhubei", "TW" ], "timestamp" : "2026-06-16T13:40:32.572", "fingerprint" : "95437d71496819010928170673b2dc4b8e6a1e07e8e820cbc6f038866089af19", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/RenesasElectronics/744000131426269-staff-dft-engineer-zhubei-", "externalId" : "744000131426269", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Zhubei", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "24.8396820,121.0040779" } ], "locationText" : "Zhubei, Taiwan", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "remoteFriendly" : false, "rawDescription" : "Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. We are looking for a digital design engineer with DFT capabilities ## Qualifications 1. Experience: 5+ years of hands-on experience in DFT architecture and implementation for SoC/ASIC. 2. Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST. 3. Experience in creating and implementing hierarchical DFT architecture in complex SoC. 4. Experience in Low-Power DFT and MBIST. 5. Experience in test time and test coverage analysis for scan and MBIST patterns. 6. Experience in working with test engineering team to bring up production test program. 7. Extensive knowledge of timing concepts and constraint development. 8. Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments. 9. Experience in RTL is required. ## Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’ At Renesas, you can: * Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. * Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. * Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, disabilities, military status, veteran status, or any other basis protected by law. For more information, please read our [Diversity & Inclusion Statement](https://jobs.renesas.com/diversity-and-inclusion).", "summaryDescription" : "Staff DFT Engineer at Renesas Electronics", "postedDate" : "2026-06-10T11:07:25.000", "createdAt" : "2026-06-16T01:31:58.797", "lastUpdated" : "2026-06-16T13:40:32.572", "ingestTimestamp" : "2026-06-16T01:31:58.797", "mongoId" : "6a307110f292fd229cff7b48", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "daysOld" : 6, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "69dde4492beec4dd3d9a335e", "title" : "Engineering Assistant or II", "company" : "Texas Department of Transportation", "industry" : "Government", "salary" : { "min" : 51158.0, "max" : 70000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "UST-Texas-Brownwood-Brownwood District Headquarter", "locations" : [ "UST-Texas-Brownwood-Brownwood District Headquarter", "Yearly", "Nonexempt,
Brownwood District Headquarter (23DISTHQ)
2495 HWY 183 N
Brownwood, 76802

, Brownwood District Headquarter" ], "certifications" : [ "Engineering licensure" ], "timestamp" : "2026-06-16T01:55:49.835", "fingerprint" : "048a75b4358570aba6e9649f57f2c20ec120c1ce4c4baec5b6eba87e1caff88b", "source" : "taleo", "language" : "en", "applyUrl" : "https://fa009.taleo.net/careersection/ex/jobdetail.ftl?job=43015", "externalId" : "43015", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Brownwood", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "31.7208509,-98.9818701" } ], "locationText" : "Brownwood, Texas, United States", "employmentType" : "FULL_TIME", "professionalSkills" : [ "Infrastructure development" ], "majorSkills" : "Engineering design, Construction inspection", "majorSkillsList" : [ "Engineering design", "Construction inspection" ], "coreResponsibilities" : "Rotate through hands-on experiences, Work, licensed professionals, Build skills, Expand knowledge, Support journey toward licensure", "teamCollaboration" : "Licensed professionals", "domainKnowledge" : "Infrastructure", "domainList" : [ "infrastructure" ], "domainSpecificKnowledge" : [ "Infrastructure" ], "continuousLearning" : "Mentorship", "specialRequirements" : "Complete simulation", "outcomesObjectives" : "Achieve engineering licensure", "qualificationsBasic" : "Engineering licensure support", "qualificationsPreferred" : "Engineering Assistant II level", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Are you ready to launch your engineering career with purpose and momentum? As an Engineering Assistant I or II, you'll rotate through hands-on experiences in design, construction, inspection, and more all while working alongside licensed professionals who are invested in your growth. This roles is designed to build your skills, expand your knowledge, and support your journey toward engineering licensure. If you're passionate about infrastructure, innovation, and making a tangible impact in your community, we'd love to see what you bring to the table! Apply today and take that next step toward building a career that shapes the futures. Important: As part of the selection process, candidates will be required to complete a simulation designed to evaluate practical application of concepts relevant to the role. Salary/ Plan Grade: Engineering Assistant I: B20 $51,158 - $60,000/ yearly Engineering Assistant II: B21: $54,278 - $70,000/ yearly The Texas Department of Transportation reserves the sole right in determining the level of position based on the applicant’s work experience, education, skill level and all other appropriate factors, and based on business needs . 51,158.00 70,000.00", "summaryDescription" : "Engineering Assistant or II at Texas Department of Transportation. Skills: Engineering design, Construction inspection. Rotate through hands-on experiences. Work", "createdAt" : "2026-06-14T19:48:36.893", "lastUpdated" : "2026-06-16T01:55:49.835", "ingestTimestamp" : "2026-06-14T19:48:36.893", "mongoId" : "69dde4492beec4dd3d9a335e", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 51158, "salaryAnnualMax" : 70000, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "Engineering design", "Construction inspection", "Infrastructure development", "Infrastructure", "Engineering licensure" ], "skillCount" : 5, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Entry", "dataQualityScore" : 0.7777778, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.95 }, { "id" : "6a1688d858b93c861eafb75b", "title" : "Engineering Assistant or II", "company" : "TxDOT", "industry" : "Government", "salary" : { "min" : 51158.0, "max" : 87046.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "UST-Texas-San Angelo-San Angelo District Hdqtr", "locations" : [ "UST-Texas-San Angelo-San Angelo District Hdqtr", "Yearly", "Nonexempt,
San Angelo District Hdqtr (07DISTHQ)
4502 KNICKERBOCKER ROAD
San Angelo, 76904

, San Angelo District Hdqtr" ], "timestamp" : "2026-06-16T00:45:09.180", "fingerprint" : "63314945f15b8fca4d68fcdf88df0c541513c8286c20fa9ad23af27ed70bbb4c", "source" : "taleo", "language" : "en", "applyUrl" : "https://fa009.taleo.net/careersection/ex/jobdetail.ftl?job=44424", "externalId" : "44424", "industryFunction" : { }, "structuredLocations" : [ { "city" : "San Angelo", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "31.4649685,-100.4405094" } ], "locationText" : "San Angelo, Texas, United States", "employmentType" : "FULL_TIME", "professionalSkills" : [ "Roadway design", "Roadway construction", "Roadway maintenance" ], "majorSkills" : "Transportation projects", "majorSkillsList" : [ "Transportation projects" ], "coreResponsibilities" : "Assist in delivery of transportation projects, Participate in Engineering Assistant Career Development Program, Gain experience in roadway design, Gain experience in roadway construction, Gain experience in roadway maintenance, Receive classroom training, Receive on-the-job training", "domainKnowledge" : "Transportation projects", "domainList" : [ "transportation-projects" ], "domainSpecificKnowledge" : [ "Transportation projects" ], "continuousLearning" : "Classroom training; On-the-job training", "qualificationsBasic" : "Engineering Assistant Career Development Program participation, Roadway design experience, Roadway construction experience, Roadway maintenance experience, Classroom training, On-the-job training", "qualificationsPreferred" : "Licensure", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "TxDOT’s San Angelo District is looking for an Engineering Assistant I or II for our Transportation Planning & Development Office to assist in the delivery of essential transportation projects. As an EA, you will participate in our Engineering Assistant Career Development Program and gain valuable experience in roadway design, construction, and maintenance. We provide classroom and on-the-job training that will help you on your way to licensure. Engineering Assistants are our future leaders in the department and have countless opportunities for advancement. Come join our team, apply today! Work Schedule: Monday - Friday, 8:00 a.m. to 5:00 p.m. San Angelo is a vibrant city on the banks of the Concho River with a population of 100,000, yet still maintains a friendly small-town atmosphere. To learn more about the community and what it has to offer, check out these links: https://www.discoversanangelo.com/ https://www.youtube.com/watch?v=ZndGQGTh42s Salary Plan/Grade: Engineer Assistant I (B20): $51,158 - $81,351 yearly Engineer Assistant II (B21): $54,278 - $87,046 yearly *The Texas Department of Transportation reserves the sole right in determining the level of position offered based on the applicant's work experience, skill level and all other appropriate factors, and based on business needs. 51,158.00 87,046.00", "summaryDescription" : "Engineering Assistant or II at TxDOT. Skills: Transportation projects. Assist in delivery of transportation projects. Participate in Engineering Assistant Career Development Program", "createdAt" : "2026-06-14T18:54:07.399", "lastUpdated" : "2026-06-16T00:45:09.180", "ingestTimestamp" : "2026-06-14T18:54:07.399", "mongoId" : "6a1688d858b93c861eafb75b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 51158, "salaryAnnualMax" : 87046, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "Transportation projects", "Roadway design", "Roadway construction", "Roadway maintenance" ], "skillCount" : 4, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Entry", "dataQualityScore" : 0.7777778, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.92 }, { "id" : "69d3e6b82beec4dd3d3f7351", "title" : "ASIC II", "company" : "Annapurna Labs", "industry" : "Corporate Operations, ASIC, no business category", "salary" : { "min" : 136000.0, "max" : 184000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Austin, Texas, USA", "locations" : [ "Austin, Texas, USA" ], "timestamp" : "2026-06-15T03:14:31.273", "fingerprint" : "28e07010c7f1bb3a3c0b46f7c0fbd2c81a6eddae9ccbf1e3038e67ad9adc0e51", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10384121/apply", "externalId" : "65a6eee4-7290-4cf3-9680-a7e15287cb90", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Austin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.2711286,-97.7436995" } ], "locationText" : "Austin, Texas, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 2, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "technicalSkills" : "HSPICE, Cadence Sigrity, HFSS, Keysight ADS, SerDes, PCIe", "professionalSkills" : [ "Signal integrity", "Power integrity", "Electromagnetics" ], "hardSkillsList" : [ "Time-domain simulations", "Frequency-domain simulations", "EMIR analysis", "Transmission line theory", "High-speed interfaces", "System-level integrity", "Power delivery architectures" ], "hardSkills" : [ { "name" : "Time-domain simulations", "level" : "intermediate" }, { "name" : "Frequency-domain simulations", "level" : "intermediate" }, { "name" : "EMIR analysis", "level" : "intermediate" }, { "name" : "Transmission line theory", "level" : "intermediate" }, { "name" : "High-speed interfaces", "level" : "intermediate" }, { "name" : "System-level integrity", "level" : "intermediate" }, { "name" : "Power delivery architectures", "level" : "intermediate" } ], "majorSkills" : "Signal integrity, Power integrity, ASIC design, Machine learning ASICs", "majorSkillsList" : [ "Signal integrity", "Power integrity", "ASIC design", "Machine learning ASICs" ], "coreResponsibilities" : "Design SI/PI systems, Validate SI/PI systems, Perform simulations, Apply transmission line theory, Apply electromagnetics, Develop high-speed interfaces, Resolve SI issues, Ensure system-level integrity, Use lab equipment, Validate simulation results, Correlate simulation results, Debug prototypes, Propose innovative solutions, Document simulation outcomes, Document measurement data, Document design trade-offs, Present recommendations", "teamCollaboration" : "Cross-functionally with silicon teams; Cross-functionally with packaging teams; Cross-functionally with board design teams; Cross-functionally with validation teams", "domainKnowledge" : "Machine learning ASICs; Customized hardware platforms; AWS datacenter environments; High-speed interfaces; SoC power delivery; Large-scale compute environments", "domainList" : [ "machine-learning-asics", "customized-hardware-platforms", "aws-datacenter-environments", "high-speed-interfaces", "soc-power-delivery", "large-scale-compute-environments" ], "domainSpecificKnowledge" : [ "Machine learning ASICs", "Customized hardware platforms", "AWS datacenter environments", "High-speed interfaces", "SoC power delivery", "Large-scale compute environments" ], "toolProficiency" : [ "HSPICE", "Cadence Sigrity", "HFSS", "Keysight ADS" ], "communicationSkills" : "Present to stakeholders", "documentationSkills" : "Document simulation outcomes; Document measurement data; Document design trade-offs", "continuousLearning" : "Fostering a culture of continuous learning", "innovationCreativity" : "Proposing innovative solutions", "problemSolvingSkills" : "Resolving complex SI issues; Debugging prototypes; Tackle novel challenges", "outcomesObjectives" : "Meet stringent performance requirements", "qualificationsBasic" : "Bachelor's degree or foreign equivalent, 2 years of experience, 1 year experience using time domain and frequency domain tools, 1 year experience with PCB, Package, interposers, and Silicon, 1 year experience in Transmission line theory and Electromagnetics", "qualificationsPreferred" : "Please see job description and the position requirements above", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "MULTIPLE POSITIONS AVAILABLE Employer: ANNAPURNA LABS (U.S.) INC. Offered Position: ASIC II Job Location: Austin, Texas Job Number: AMZ9679283 Position Responsibilities: Design and validate signal and power integrity (SI/PI) systems for next generation machine learning ASICs and customized hardware platforms optimized for AWS datacenter environments. Perform both time-domain and frequency-domain simulations using tools such as HSPICE, Cadence Sigrity, HFSS, and Keysight ADS, including 3D/2.5D EMIR analysis. Apply transmission line theory and electromagnetics to develop high-speed interfaces like SerDes and PCIe, resolving complex SI issues across digital systems. Collaborate cross-functionally with silicon, packaging, board design, and validation teams to ensure system-level integrity across PCB, interposers, and advanced SoC power delivery architectures using die-level capacitors (DTC, IPD). Use high-speed lab equipment to validate and correlate simulation results, while debugging prototypes to meet stringent performance requirements. Tackle novel challenges in interconnects and power delivery for large-scale compute environments by proposing innovative, high-impact solutions. Document simulation outcomes, measurement data, and design trade-offs, presenting clear recommendations to both technical and non-technical stakeholders while fostering a culture of continuous learning and engineering excellence Position Requirements: Bachelor's degree or foreign equivalent degree in Electrical or Computer Engineering or related field and two years of experience in the job offered or related occupation. Must have one year of experience in the following skills: (1) using time domain and frequency domain tools: Hspice, Sigrity, HFSS, or Microwave Studio; (2) with PCB, Package, interposers (COWOS) and Silicon Technologies; (3) in Transmission line theory and Electromagnetics and its application in SerDes, Single-ended signal and parallel bus interfaces. Amazon.com is an Equal Opportunity-Affirmative Action Employer – Minority / Female / Disability / Veteran / Gender Identity / Sexual Orientation. 40 hours / week, 8:00am-5:00pm, Salary Range $136,000/year to $184,000/year. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, visit: https://www.aboutamazon.com/workplace/employee-benefits.#0000 Basic Qualifications: Position Requirements: Bachelor's degree or foreign equivalent degree in Electrical or Computer Engineering or related field and two years of experience in the job offered or related occupation. Must have one year of experience in the following skills: (1) using time domain and frequency domain tools: Hspice, Sigrity, HFSS, or Microwave Studio; (2) with PCB, Package, interposers (COWOS) and Silicon Technologies; (3) in Transmission line theory and Electromagnetics and its application in SerDes, Single-ended signal and parallel bus interfaces.#0000 Preferred Qualifications: Please see job description and the position requirements above. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "ASIC II at Annapurna Labs. Skills: Signal integrity, Power integrity, ASIC design, Machine learning ASICs. Design SI/PI systems. Validate SI/PI systems", "postedDate" : "2026-06-13T08:19:28.950", "createdAt" : "2026-06-13T08:19:28.950", "lastUpdated" : "2026-06-15T03:14:31.273", "ingestTimestamp" : "2026-06-13T08:19:28.950", "mongoId" : "69d3e6b82beec4dd3d3f7351", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10384121/apply", "salaryAnnualMin" : 136000, "salaryAnnualMax" : 184000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Time-domain simulations", "Frequency-domain simulations", "EMIR analysis", "Transmission line theory", "High-speed interfaces", "System-level integrity", "Power delivery architectures", "Signal integrity", "Power integrity", "ASIC design", "Machine learning ASICs", "Electromagnetics", "Customized hardware platforms", "AWS datacenter environments", "SoC power delivery", "Large-scale compute environments", "HSPICE", "Cadence Sigrity", "HFSS", "Keysight ADS" ], "skillCount" : 20, "jobCategory" : "operations", "dataQualityScore" : 1.0, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a2c9a9174d8ee00a09977bd", "title" : "SoC Emulation Engineer", "company" : "Solidigm", "industry" : "Outsourcing/Offshoring", "salary" : { "min" : 154160.0, "max" : 231300.0, "currency" : "CAD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Vancouver, BC, Canada", "locations" : [ "Vancouver", "BC", "Canada" ], "timestamp" : "2026-06-15T09:26:56.869", "fingerprint" : "4a525e33909ef582788fac8c8ce5c6df44268b0f0c1341eaf040d559457a2333", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Solidigm/744000131182800-soc-emulation-engineer", "externalId" : "744000131182800", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Vancouver", "state" : "British Columbia", "country" : "Canada", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "49.2608724,-123.1139520" } ], "locationText" : "Vancouver, British Columbia, Canada", "employmentType" : "FULL_TIME", "experienceLevel" : "not-applicable", "technicalSkills" : "SoC emulation, Logic design, Verification, RTL design, RTL simulation, UVM, FW co-simulation, Formal property verification, C, C++, Python, Java, Verilog, VHDL, SystemVerilog, NVMe, PCIe, DDR, ARM", "professionalSkills" : [ "Micro-architecture", "Verification strategy", "Verification architecture", "Logic design", "Firmware development", "System simulation", "Synthesis", "Place and route", "Timing analysis", "Power analysis" ], "hardSkillsList" : [ "Digital logic design", "Implementation experience", "Functional verification", "RTL design", "RTL simulation", "Formal property verification", "Synthesis", "Place and route", "Timing analysis", "Power analysis", "Low-power design" ], "softSkillsList" : [ "Customer inspired", "Trusting", "Innovative", "Inclusive", "Listening skills" ], "hardSkills" : [ { "name" : "Digital logic design", "level" : "intermediate" }, { "name" : "Implementation experience", "level" : "intermediate" }, { "name" : "Functional verification", "level" : "intermediate" }, { "name" : "RTL design", "level" : "intermediate" }, { "name" : "RTL simulation", "level" : "intermediate" }, { "name" : "Formal property verification", "level" : "intermediate" }, { "name" : "Synthesis", "level" : "intermediate" }, { "name" : "Place and route", "level" : "intermediate" }, { "name" : "Timing analysis", "level" : "intermediate" }, { "name" : "Power analysis", "level" : "intermediate" }, { "name" : "Low-power design", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Customer inspired" }, { "name" : "Trusting" }, { "name" : "Innovative" }, { "name" : "Inclusive" }, { "name" : "Listening skills" } ], "majorSkills" : "SoC Emulation, Logic Design, Verification, RTL Design", "majorSkillsList" : [ "SoC Emulation", "Logic Design", "Verification", "RTL Design" ], "coreResponsibilities" : "Build emulation models, Deliver emulation models, Perform logic design, Perform verification, Perform RTL design, Perform RTL simulation, Develop test plans, Review test plans, Develop execution plans, Review execution plans, Contribute to multidimensional designs, Perform SoC emulation flow, Investigate new tools, Investigate new technologies", "teamCollaboration" : "Collaborate with functional teams; Project-based teamwork; Engagement with stakeholders; Cross-functional teams", "projectManagementSkills" : [ "Time management", "Balance competing priorities", "Predictable delivery", "Risk identification", "Issue identification" ], "domainKnowledge" : "SoC development; Semiconductor products; Integrated circuits; Advanced technology nodes; ASIC/SoC design flows; Low-power design; NVMe standards; PCIe standards; DDR standards; ARM standards", "domainList" : [ "soc-development", "semiconductor-products", "integrated-circuits", "advanced-technology-nodes", "asic-soc-design-flows", "low-power-design", "nvme-standards", "pcie-standards", "ddr-standards", "arm-standards" ], "domainSpecificKnowledge" : [ "SoC development", "Semiconductor products", "Integrated circuits", "Advanced technology nodes", "ASIC/SoC design flows", "Low-power design", "NVMe standards", "PCIe standards", "DDR standards", "ARM standards" ], "toolProficiency" : [ "Jira", "Confluence" ], "communicationSkills" : "Written communication; Verbal communication; Project presentation; Listening skills", "documentationSkills" : "Documentation", "continuousLearning" : "Investigate new tools; Investigate new technologies", "innovationCreativity" : "Innovative solutions; Cutting-edge products", "problemSolvingSkills" : "Debugging; Problem-solving; Negotiating solutions; Risk identification; Issue identification", "outcomesObjectives" : "Deliver excellence; Deliver business value; Ensure semiconductor products success", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, Bachelor's degree in Computer Engineering, Bachelor's degree in Computer Science, Debugging and problem-solving skills, Digital logic design experience, Implementation experience in advanced technology nodes, Functional verification experience, C, C++, Python, Java, Verilog, SystemVerilog languages", "qualificationsPreferred" : "10+ years of experience in ASIC/SoC development, Advanced degree in Computer Engineering, Advanced degree in Computer Science, Advanced degree in Applied Science, Experience leading technical teams, Familiarity with formal verification methods, Familiarity with standard ASIC/SoC design flows, Experience in low-power design techniques, Experience using Atlassian tools, Working knowledge of NVMe standards, Working knowledge of PCIe standards, Working knowledge of DDR standards, Working knowledge of ARM standards, Familiarity with big box emulation platforms, Proven ability to architect verification efforts, Proven ability to lead verification efforts", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible. In this position you will join a fast-paced team delivering new, cutting-edge SoC's for Solidigm Solid State Drives (SSD). As an ASIC emulation engineer, you will perform various functions including logic design, verification, implementation, and/or documentation for SoC (System on a Chip) emulation. You will collaborate with other functional teams for micro-architecture, verification strategy/architecture, logic design, firmware development, and system simulation for the SoC development based on system requirements and customer feature requests. Regular responsibilities include, but are not limited to: * Build & deliver emulation models for internal SoC development using industry standard tools & methods * Perform logic design and/or verification for functional units and sub-systems in SoC IP and/or full chip designs * Perform Register Transfer Level (RTL) design and simulation for SoCs using industry-standard methodologies * Develop/review test and execution plans, ensuring that Solidigm’s semiconductor products will be successful * Use industry-standard verification methodologies such as UVM, FW co-simulation, formal property verification, etc. * Contribute to the development of multidimensional designs involving the layout of complex integrated circuits * Perform all aspects of the SoC emulation flow from high-level design synthesis to place and route, timing and power to create a design database that is ready for manufacturing. * Continuously investigate new tools and technologies A successful candidate will demonstrate: * Excellent written and verbal communication skills * Project-based teamwork experience * Advanced digital logic design skills * Proactive engagement with stakeholders across the team and organization * Effective time management skills and ability to balance competing priorities to ensure predictable delivery of projects * Developing recommendations and negotiating solutions for tactical issues * Proactive identification of risks and issues * Ability to create and deliver effective project presentation to diverse stakeholder audiences * Superior listening skills ## Qualifications * Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent * Strong debugging and problem-solving skills supported by relevant experience * Digital logic design and implementation experience in advanced technology nodes * Familiarity with performing functional verification, including verification methodologies such as UVM and FPV * Languages: C, C++, Python, Java, Verilog (or VHDL), and/or SystemVerilog Preferred Qualifications: * 10+ years of experience in ASIC/SoC development or equivalent * Advanced degree in Computer Engineering, Computer Science, Applied Science, etc. * Experience leading technical teams to deliver complex designs * Familiarity with formal verification methods (e.g., SystemVerilog Assertions) * Familiarity with standard ASIC/SoC design flows including synthesis, DFT, STA, UPF, and ECO flows * Experience in low-power design techniques * Experience using Atlassian tools (Jira, Confluence, etc.) to track and manage project execution * Working knowledge of NVMe, PCIe, DDR and/or ARM standards * Familiarity with big box emulation platforms * Proven ability to architect and lead IP/SoC-level verification efforts This position is also eligible to participate in Solidigm's restricted stock unit (RSU), restricted cash unit (RCU), and cash bonus programs. In addition, Solidigm offers a benefits package that includes medical, dental, vision, supplemental life and AD&D insurance; short- and long-term disability; healthcare and dependent care flexible spending accounts, and a company match on eligible 401(k) plan contributions. ## Additional Information At Solidigm Technology, we believe in transparency and fair compensation. In accordance with Canadian labor laws and our commitment to equitable hiring practices, we provide salary ranges for this position. Salary Range: $154,160 - $231,300 The actual compensation offered will be based on individual skills, qualifications, and experience. We strive to ensure that all employees are compensated fairly and in line with market standards. Powered by SmartRecruiters -[Candidate Privacy Policy](https://url.uk.m.mimecastprotect.com/s/9pxQClOPVtywX3Ju9h5UzXpnh?domain=smartrecruiters.com/)", "summaryDescription" : "SoC Emulation Engineer at Solidigm. Skills: SoC Emulation, Logic Design, Verification, RTL Design. Build emulation models. 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Then this role is for you. The Traffic Engineering team is looking for a talented and passionate Software Development Engineer to play a critical role in building Amazon’s next-gen data lakes and cloud networking fabric that will help drive innovation at Amazon. You will have the opportunity to re-define and automate how Amazon services connect with each other. Deliver frictionless connectivity experience innovating alongside teams at Amazon.com, Alexa, Kindle, Prime, and others. Work hard, have fun, make history! Key job responsibilities The ideal candidate is a champion of engineering excellence and improves quality, consistency, maintainability, performance, and security with every code commit. In addition, he/she contributes elegant, practical code with Generative AI that solves the most difficult problems at Amazon scale. There are no limits to the contribution and impact this role can have, so get ready to make history! About the team Our team is embarking on a journey to develop the next generation of networking software for customers. Your work will be highly visible and is instrumental in helping Amazon serve record breaking amounts everyday including flagship events such as Prime Day. If you love building high performance software with Generative AI that's focused on best-in-class networking, data processing, security, and leverages AWS technologies, we have the job for you. Key job responsibilities * 5+ years of experience contributing to the system design or architecture (architecture, design patterns, reliability and scaling) of new and current systems. * 4+ years of non-internship professional software development experience * Programming experience with at least one software programming language. Knowledge of professional software engineering and best practices for the full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations. Experience building large-scale software systems that have been successfully delivered to customers. Hands-on expertise in many disparate technologies, typically ranging from front-end user interfaces through to back-end software systems and all points in between. Basic Qualifications: - 3+ years of non-internship professional software development experience - 2+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience - Experience programming with at least one software programming language Preferred Qualifications: - 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience - Bachelor's degree in computer science or equivalent Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. 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Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We are seeking a passionate Emulation Engineer to build the next generation of our cloud server infrastructure using our emulation platform. You will work closely with various teams to determine the emulation platform requirements, models needed for functional testing and automation of various workflows. You will be delivering a state-of-the-art testbench, integrate the ViP components into the SoC and ensure a high quality of the design delivered to the customers. You will be developing a strong understanding of the product and continuously raise the bar to ensuring that emulation models are functionally correct and performant. Join us in creating the most advanced Machine Learning Accelerators in the world! Key job responsibilities * Design emulation capabilities in system verilog/C/C++/Python/Shell scripts to facilitate system validation flows * Develop scalable compile flows targeting project requirements * Knowledge of end to end emulation compilation flows involving front end and back end synthesis * Familiar with using emulation tool chain from Zebu, Cadence or Veloce * Develop System Verilog modules required for integrating with standard xtors * Experience in run time architecture of any emulation framework. * Develop run time framework in C++ to execute compiled emulation models * Optimize build and run times of emulation models. * Automate system flow execution in emulation using bash/python/tcl etc. * Work with SoC teams to learn about system flows and execute them on emulation framework * Debug RTL failures associated with chip functionality * Proficient with using various emulation debug technologies * Knowledge of using gdb and other techniques to debug software failures * Work with vendors to ensure emulation tool chain is up to date with latest technologies A day in the life As an emulation engineer, you would be working closely with our vendor, software, firmware, architecture, design and verification teams to design and execute system validation flows. Basic Qualifications: - Bachelor's degree in Electrical Engineering or a related field - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills - Experience in developing functional specifications, design verification plans and functional test procedures Preferred Qualifications: - Master's degree in Electrical or Communications Engineering or a related field - Experience with formal verification techniques including abstraction and end-to-end checking - Experience with ARM and various DSP ISAs - Experience with current and upcoming RF standards in cellular (4G/5G NR), WiMAX, 802.11ad, microwave backhaul, or related broadband wireless standards - Experience with industry standard tools and scripting languages (Python or Perl) for automation Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Cupertino - 157,300.00 - 212,800.00 USD annually", "summaryDescription" : "Emulation Engineer, Annapurna Labs - Cloud-Scale MLA at Annapurna Labs. Skills: Emulation platform, Hardware design, System validation. Design emulation capabilities. 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Drive technology roadmaps in areas of expertise to drive innovation and meet the needs of the long term Amazon Devices’ product roadmap. Work closely with Silicon and component suppliers to influence their chip roadmaps to meet needs. Perform video picture quality (PQ) evaluations to evaluate the performance of PQ intellectual property (IP) using industry tools and standards (ISO/IEC, VMAF, SSMI, PSNR, MOS) in both offline software simulations and in a physical laboratory. Prepare training data for Machine Learning (ML) based algorithms using cloud infrastructure such as AWS EC2 and S3 services in preparation for implementation into a ASIC or System-on-Chip (SoC). 40 hours / week, 8:00am-5:00pm, Salary Range $176,696/year to $212,800/year. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, visit: https://www.aboutamazon.com/workplace/employee-benefits. Amazon.com is an Equal Opportunity-Affirmative Action Employer – Minority / Female / Disability / Veteran / Gender Identity / Sexual Orientation.#0000 Basic Qualifications: Position Requirements: Bachelor’s degree or foreign equivalent degree in Electronic Engineering, Electrical Engineering, or a related field and three years of experience in the job offered or a related occupation. Must have one year of experience in the following skill(s): (1) hands-on experience performing video picture quality (PQ) evaluations to evaluate the performance of PQ intellectual property (IP); and (2) hands-on experience with industry standard picture quality (PQ) evaluation tools and standards including ISO/IEC, VMAF, SSMI, PSNR, and MOS.#0000 Preferred Qualifications: Please see job description and the position requirements above. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. 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With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Role: Mask Design Senior Technologist (Principal Engineer) Role Overview As a VLSI Layout Technologist, you will serve as a senior technical member driving full‑chip and block‑level layout architecture across Analog, Digital, and Mixed‑signal domains. Expectation is to influence design strategy, lead complex layout development, and ensure first‑pass silicon success. Key Responsibilities * Advanced Layout Design & Optimization Lead the development, optimization, and integration of peripheral and core circuit layouts across Analog, Digital, and Mixed‑Signal domains. Ensure adherence to design specifications, performance targets, and foundry rules while driving correct‑by‑construction methodologies. * Design Verification & Sign‑off Leadership Oversee DRC, LVS, parasitic extraction, and sign‑off flows. Ensure design integrity, manufacturability, and first‑pass silicon success through rigorous verification and closure strategies. * Power Distribution & Floor planning Architecture Architect full‑chip power distribution networks and floorplans to optimize electrical performance, minimize parasitic’s , and reduce die size. Provide guidance on placement, routing, and hierarchical layout planning. * Cross‑Functional Technical Leadership Collaborate with Design Engineering (DE), Integration (INTEG), and Process Technology teams across global sites to resolve design issues, align methodologies, and ensure seamless integration. Drive technical convergence on topics such as buffer topology, layout methodologies, and design‑rule interpretation. * Methodology Development & Continuous Improvement Define and enhance layout methodologies, automation flows, and best practices to improve productivity, consistency, and design quality. Champion innovation in layout automation and process optimization. * Technical Mentorship & Review Provide technical direction to senior layout engineers, conduct critical block reviews, and elevate team capability through mentorship and knowledge sharing. ## Qualifications Your Experience and Role Expectation Extensive IC Layout Expertise : 22+ years of full‑chip custom layout experience across analog, digital, and mixed‑signal designs with deep knowledge of power routing, signal planning, and physical constraints. Tool & Verification : Expert in DRC/LVS, parasitic extraction, EM/IR analysis, and sign‑off verification using industry‑standard tools. 'Floor planning Strength : Proven ability to architect efficient floorplans, optimize placement, and reduce die area using correct‑by‑construction approaches. Cross‑Site Leadership : Strong track record collaborating with multi‑site, cross‑disciplinary teams and leading small technical groups to successful design convergence. Communication & Methodology : Excellent communication skills with a proactive approach to methodology development, automation, and continuous improvement. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. 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With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Role: Mask Design Senior Technologist (Principal Engineer) Role Overview As a VLSI Layout Technologist, you will serve as a senior technical member driving full‑chip and block‑level layout architecture across Analog, Digital, and Mixed‑signal domains. Expectation is to influence design strategy, lead complex layout development, and ensure first‑pass silicon success. Key Responsibilities * Advanced Layout Design & Optimization Lead the development, optimization, and integration of peripheral and core circuit layouts across Analog, Digital, and Mixed‑Signal domains. Ensure adherence to design specifications, performance targets, and foundry rules while driving correct‑by‑construction methodologies. * Design Verification & Sign‑off Leadership Oversee DRC, LVS, parasitic extraction, and sign‑off flows. Ensure design integrity, manufacturability, and first‑pass silicon success through rigorous verification and closure strategies. * Power Distribution & Floor planning Architecture Architect full‑chip power distribution networks and floorplans to optimize electrical performance, minimize parasitic’s , and reduce die size. Provide guidance on placement, routing, and hierarchical layout planning. * Cross‑Functional Technical Leadership Collaborate with Design Engineering (DE), Integration (INTEG), and Process Technology teams across global sites to resolve design issues, align methodologies, and ensure seamless integration. Drive technical convergence on topics such as buffer topology, layout methodologies, and design‑rule interpretation. * Methodology Development & Continuous Improvement Define and enhance layout methodologies, automation flows, and best practices to improve productivity, consistency, and design quality. Champion innovation in layout automation and process optimization. * Technical Mentorship & Review Provide technical direction to senior layout engineers, conduct critical block reviews, and elevate team capability through mentorship and knowledge sharing. ## Qualifications Your Experience and Role Expectation Extensive IC Layout Expertise : 22+ years of full‑chip custom layout experience across analog, digital, and mixed‑signal designs with deep knowledge of power routing, signal planning, and physical constraints. Tool & Verification : Expert in DRC/LVS, parasitic extraction, EM/IR analysis, and sign‑off verification using industry‑standard tools. 'Floor planning Strength : Proven ability to architect efficient floorplans, optimize placement, and reduce die area using correct‑by‑construction approaches. Cross‑Site Leadership : Strong track record collaborating with multi‑site, cross‑disciplinary teams and leading small technical groups to successful design convergence. Communication & Methodology : Excellent communication skills with a proactive approach to methodology development, automation, and continuous improvement. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. 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Ft Worth District Headquarters (02DISTHQ)
2501 SOUTHWEST LOOP 820
Fort Worth, 76133

, Ft Worth District Headquarters" ], "certifications" : [ "PE License" ], "timestamp" : "2026-06-15T13:35:44.285", "fingerprint" : "713ce4756f95f1cdc8c0032366c864a170822294e879c80b045f858bddb951c1", "source" : "taleo", "language" : "en", "applyUrl" : "https://fa009.taleo.net/careersection/ex/jobdetail.ftl?job=43061", "externalId" : "43061", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Fort Worth", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "32.7531770,-97.3327459" } ], "locationText" : "Fort Worth, Texas, United States", "majorSkills" : "PS&E design", "majorSkillsList" : [ "PS&E design" ], "coreResponsibilities" : "Produce PS&E design, Oversee project design execution", "continuousLearning" : "Engineering Assistant Career Development Program; Training programs; Opportunity for growth/advancement", "qualificationsBasic" : "Engineering Assistant I or II, PE License training", "qualificationsPreferred" : "Recent engineering graduate", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "TxDOT’s Fort Worth District is looking for an Engineering Assistant; Level I or II. The Engineering Assistant position is focused on producing PS&E design for various types of construction projects. This position will also rotate into the field to help oversee the execution of the project design plans. If you are looking to build a career or if you are a recent engineering graduate and are looking to build your skills, gain engineering experience, and grow your career then TXDOT’s Fort Worth District is the place for you! TXDOT offers outstanding training programs, opportunity for growth/advancement, work/life balance and supports engineering assistants through the licensing process by providing the Engineering Assistant Career Development Program. This program will assist in training in a rotation of areas and providing you with experience for your PE License. Start growing your professional career with TXDOT, apply today! Physical Address: 2501 Southwest Loop 820, Fort Worth, TX 76133 Minimum/Maximum Monthly Salary: Engineering Assistant I: (B20) $4,263.16 - $6,779.25; Engineering Assistant II: (B21) $4,523.16 - $7,253.83 The Texas Department of Transportation reserves the sole right in determining the level of position based on the applicant's work experience, education, skill level and all other appropriate factors, and based on business needs. 51,158.00 87,046.00", "summaryDescription" : "Engineering Assistant or II at TxDOT. Skills: PS&E design. Produce PS&E design. Oversee project design execution", "createdAt" : "2026-06-14T08:30:26.184", "lastUpdated" : "2026-06-15T13:35:44.285", "ingestTimestamp" : "2026-06-14T08:30:26.184", "mongoId" : "69dde4492beec4dd3d9a3365", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 51156, "salaryAnnualMax" : 87036, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "PS&E design", "PE License" ], "skillCount" : 2, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Entry", "dataQualityScore" : 0.6666667, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.95 } ], "status" : 200, "message" : "technologist asic development engineering emulation engineer dft upf zebu or palladium methodology jobs", "metadata" : { "title" : "technologist asic development engineering emulation engineer dft upf zebu or palladium methodology" }, "pagination" : { "page" : 0, "limit" : 50, "totalCount" : 101097, "totalPages" : 2022, "hasNext" : true, "hasPrevious" : false } }

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