Sandisk
Technology
SeniorEngineer,ASICDevelopmentEngineering(IPVerification)
Neural analysis suggests this role is
optimal for mid candidates.
“Senior Engineer, ASIC Development Engineering (IP Verification ) at Sandisk. Skills: RTL verification, SystemVerilog, UVM, FPGA verification. Design complex logic blocks. Design IPs”
Industry & Context.
Root-cause analysis; Debugging; Troubleshooting
What They're Looking For.
Must Have
BE/ME in ECE, 5 years RTL verification, SystemVerilog proficiency, EDA tools knowledge, FPGA-based verification, SV-UVM simulation, Testbenches development, Debugging capability, Perl/Python proficiency, AI/ML fundamentals, ML techniques experience, Version control systems
Nice to Have
Advanced SVA experience, Advanced UVM experience, Standard protocols exposure, EMMC exposure, UFS exposure, USB exposure, PCIe exposure, DDR4 exposure
What You'll Do.
Design complex logic blocks
Work in multi-disciplinary environment
Develop FPGA solutions
Validate memory devices
How You'll Work.
Team & Collaboration
Multi-disciplinary environment; Local and global teams; Multiple interfaces
Communication Scope
Communicate findings; Communicate across interfaces
Full Job Description
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. * The FPGA design team, part of the (VHS) group is responsible for developing a wide range of FPGA solutions for post-silicon validation of memory devices across Western Digital. Your main responsibilities as part of a winning group: * Complex logic blocks & IPs design * Work in a multi-disciplinary environment with a variety of complex interfaces. ## Qualifications * BE/ME in ECE, Electronics, or a related engineering discipline. * 5 years of hands-on experience in RTL verification at Block/IP/Sub-system/SoC levels. * Proficient in SystemVerilog for verification; advanced experience with SVA and UVM is a strong advantage. * Deep knowledge of EDA tools such as Cadence NCSim, SimVision, vManager, and waveform-debug tools from Mentor/Synopsys. * Experience with FPGA-based verification environments. * Practical experience with SV- UVM-based simulation environments. * Skilled in developi
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