Morse Micro

Technology

SeniorDFTEngineer

₹22–35L ~AI est. Bangalore, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior DFT Engineer at Morse Micro. Skills: DFT architecture, SCAN solutions, MBIST integration, ATPG patterns. Own end-to-end DFT for wireless SoCs. Define DFT architecture”

Industry & Context.

Technology
Problems you'll solve

Problem-solving skills; Analytical skills

What They're Looking For.

Must Have

Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science, 5+ years experience as a DFT Engineer, Hands-on experience in scan insertion/stitching, Hands-on experience in ATPG setup, Hands-on experience in JTAG, Hands-on experience in simulation, Hands-on experience in debug, Hands-on experience in scan DRC analysis, Solid understanding of digital design fundamentals, Solid understanding of RTL coding, Solid understanding of verification, Proven expertise on hierarchical DFT methodologies, Post-silicon debug experience, Silicon bring-up experience, Excellent verbal communication skills, Excellent written communication skills, Proven to work constructively within your team, Proven to work constructively among other groups, Analytical and problem-solving skills, A determination to deliver even when subject to time pressures, A hands-on, practical attitude

What You'll Do.

Own end-to-end DFT for wireless SoCs

Define DFT architecture

Define coverage goals

Optimize test quality

Optimize pattern count

Optimize tester time/constraints

Architect SCAN solutions

Implement SCAN solutions

Integrate at-speed test methodologies

Implement low-power DFT techniques

Own MBIST integration

Own MBIST diagnostics

Implement IEEE 1149.1 JTAG/TAP

Implement IEEE 1500 wrappers

Integrate DFT for third-party IPs

Generate ATPG patterns

Validate ATPG patterns

Support first silicon ATE bring-up/debug

Drive DFT scripting / automation

Drive cross-functional collaboration

How You'll Work.

Team & Collaboration

Cross-functional collaboration

Communication Scope

Verbal communication; Written communication

Full Job Description

Morse Micro is at the forefront of next-generation Wi-Fi technology, delivering breakthrough solutions that redefine wireless connectivity. Our innovative products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability. Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things (IoT)? Keen to make a real difference in a VC-backed high-growth company while working in a dynamic & fun environment? Then join Morse Micro, Australia’s largest fabless semiconductor company! Your responsibilities would include: - Own end-to-end DFT for wireless SoCs, including architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support. - Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints. - Architect and implement SCAN solutions, including chains, sub-chains, masking, compressors, decompressors, SDCs, and ensure post synthesis SCAN DRC clean - Develop and integrate at-speed test methodologies using OPCG for intra- and inter-clock domain testing. - Implement low-power DFT techniques such as power-aware scan, clock staggering, and test-point insertion to meet ATE/package limits. - Own MBIST integration and diagnostics for all on-chip memories, including JTAG-based debug diagnostic flows. - Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test-mode/pin-mux control. - Integrate DFT for third-party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration. - Generate and validate ATPG (stuck-at, transition, path-delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring-up/debug. - Drive silicon debug, yield analysis, DFT scripting / automation, and cross-functional collaboration with frontend, verification, PnR, and ATE in fast-paced tapeout programs

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