SeniorDFTEngineer

Morse Micro is at the forefront of next-generation Wi-Fi technology, delivering breakthrough solutions that redefine wireless connectivity. Our innovative products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability. Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things (IoT)? Keen to make a real difference in a VC-backed high-growth company while working in a dynamic & fun environment? Then join Morse Micro, Australia’s largest fabless semiconductor company! We welcome applications from overseas candidates, with relocation and visa support available for the successful applicant. Your responsibilities would include: - Own end-to-end DFT for wireless SoCs, including architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support. - Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints. - Architect and implement SCAN solutions, including chains, sub-chains, masking, compressors, decompressors, SDCs, and ensure post synthesis SCAN DRC clean - Develop and integrate at-speed test methodologies using OPCG for intra- and inter-clock domain testing. - Implement low-power DFT techniques such as power-aware scan, clock staggering, and test-point insertion to meet ATE/package limits. - Own MBIST integration and diagnostics for all on-chip memories, including JTAG-based debug diagnostic flows. - Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test-mode/pin-mux control. - Integrate DFT for third-party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration. - Generate and validate ATPG (stuck-at, transition, path-delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring-up/debug. - Drive silicon debug, yield analysis, DFT scriptin