Sandisk

Technology

SeniorTechnologist,MaskDesignEngineering

₹60–90L ~AI est. Bengaluru, Karnataka, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for director candidates.

The Brief

“Senior Technologist, Mask Design Engineering at Sandisk. Skills: IC Layout Design, Analog Design, Digital Design, Mixed-Signal Design. Lead layout development. Optimize circuit layouts”

What You'll Achieve.

Ensure first-pass silicon success

Industry & Context.

Technology
Problems you'll solve

Resolve design issues; Design verification; Sign-off verification

What They're Looking For.

Must Have

22+ years IC layout experience, Expert in DRC/LVS, Expert in parasitic extraction, Expert in EM/IR analysis, Expert in sign-off verification, Proven ability to architect floorplans, Proven ability to optimize placement, Proven ability to reduce die area, Track record collaborating with multi-site teams, Track record leading small technical groups, Excellent communication skills

Nice to Have

Deep knowledge of power routing, Deep knowledge of signal planning, Deep knowledge of physical constraints, Correct-by-construction approaches

What You'll Do.

Lead layout development

Optimize circuit layouts

Integrate circuit layouts

Ensure adherence to specifications

Ensure adherence to targets

Ensure adherence to foundry rules

Drive correct-by-construction methodologies

Oversee parasitic extraction

Oversee sign-off flows

Ensure design integrity

Ensure manufacturability

Ensure first-pass silicon success

Architect power distribution networks

Optimize electrical performance

Provide placement guidance

Provide routing guidance

Provide hierarchical layout planning

Collaborate with Design Engineering

Collaborate with Integration teams

Collaborate with Process Technology teams

Resolve design issues

Ensure seamless integration

Drive technical convergence

Define layout methodologies

Enhance layout methodologies

Define automation flows

Enhance automation flows

Define best practices

Enhance best practices

Improve design quality

Champion innovation in layout automation

Champion process optimization

Provide technical direction

Conduct critical block reviews

Elevate team capability

How You'll Work.

Team & Collaboration

Cross-functional teams; Multi-site teams; Design Engineering; Integration teams; Process Technology teams

Communication Scope

Technical communication

Full Job Description

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Role: Mask Design Senior Technologist (Principal Engineer) Role Overview As a VLSI Layout Technologist, you will serve as a senior technical member driving full‑chip and block‑level layout architecture across Analog, Digital, and Mixed‑signal domains. Expectation is to influence design strategy, lead complex layout development, and ensure first‑pass silicon success. Key Responsibilities * Advanced Layout Design & Optimization Lead the development, optimization, and integration of peripheral and core circuit layouts across Analog, Digital, and Mixed‑Signal domains. Ensure adherence to design specifications, performance targets, and foundry rules while driving correct‑by‑construction methodologies. * Design Verification & Sign‑off Leadership Oversee DRC, LVS, parasitic extraction, and sign‑off flows. Ensure design integrity, manufacturability, and first‑pass silicon success through rig

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