Astera Labs
Technology
JuniorASICDesignEngineer
Neural analysis suggests this role is
optimal for Entry candidates.
“Junior ASIC Design Engineer at Astera Labs. Skills: ASIC Design, Digital blocks, Connectivity projects. Own the journey from high-level definition. Tackle complex logic challenges”
Industry & Context.
Tackle complex logic challenges
What They're Looking For.
Must Have
Bachelor’s degree in Electrical Engineering, Bachelor’s degree in Computer Engineering, 0–2 years of experience in logic design, Foundational knowledge of Verilog, Foundational knowledge of SystemVerilog, Understanding of digital design principles, Understanding of fundamental RTL coding concepts
Nice to Have
Master's degree in Electrical Engineering, Master's degree in related field, Relevant internships valued, University labs valued, Hands-on academic projects valued
What You'll Do.
Own the journey from high-level definition
Tackle complex logic challenges
Transform logic into hardware solutions
Serve as point of contact for logic blocks
Interact with Architecture teams
Interact with Verification teams
Interact with Backend teams
Utilize quality assurance tools
Ensure designs are robust
Ensure designs are scalable
Ensure designs are power-efficient
Apply design techniques
Contribute to design quality
Participate in design methodology improvements
Participate in tool automation initiatives
Leverage AI assistance tools
Contribute to in-house automation development
Make engineering workflows faster
Make engineering workflows smarter
Collaborate effectively across teams
Ensure seamless integration
How You'll Work.
Team & Collaboration
Interacting with Architecture; Interacting with Verification; Interacting with Backend teams; Collaborate across teams
Communication Scope
Communication skills
Full Job Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Junior ASIC Design Engineer, you won't just build chips - you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Re
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