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Senior Chip Design Verification Engineer Port Ip Group
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No openings found right now · Updated daily
Active Senior Chip Design Verification Engineer Port Ip Group roles are indexed directly from company ATS systems — Greenhouse, Lever, Workday, Ashby, and 15+ others. Advertised salaries average $564k/year based on live listings. 10% of roles are remote-friendly. These listings don't come from other job boards — they're pulled from source, so many won't appear on LinkedIn, Indeed, or Glassdoor.
Open Roles
0
Avg Salary
$564k
Remote-Friendly
10%
Added This Week
25
Sectors Hiring Senior Chip Design Verification Engineer Port Ip Groups
Senior Design Verification Engineer
Astera Labs
San Jose, United States Senior Direct
Group IP Paralegal
US Flexible Mid Direct
Principal Design Verification Engineer
Astera Labs
San Jose, United States Senior Direct
Chip Design Engineer
Annapurna Labs Ltd.
Tel Aviv-Yafo, TA, ISR Onsite Direct
Chip Design Engineer
Annapurna Labs Ltd.
Tel Aviv-Yafo, Tel Aviv, ISR Onsite Mid Direct
Silicon Design Verification Engineer
[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US] Onsite Direct
Design Verification Engineer, HW Compute Group
Amazon.com Services LLC
Sunnyvale, California, USA Onsite Senior Direct
Silicon Design Verification Engineer ll
[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN] Mid Direct
Senior SoC and IP Design Engineer, Google Cloud
[Haifa, Israel, [Andrei Sakharov St 9, Haifa, 3508409, Israel], Haifa, 3508409, Haifa District, IL] Senior Direct
Senior Silicon Design Verification Engineer, Google Cloud
[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN] Senior Direct
Design Verification Engineer
Annapurna Labs (U. S. ) Inc.
Austin, Texas, USA Onsite Mid Direct
Design Verification Engineer
Annapurna Labs (U. S. ) Inc.
Cupertino, California, USA Onsite Direct
Sr. Physical Design Engineer - Full Chip, Hardware Compute Group
ADCI
Bengaluru, Karnataka, IND Onsite Senior Direct
Chip Design Student
Annapurna Labs Ltd.
Haifa, HA, ISR Onsite Entry Direct
Silicon Design Verification Engineer, Google Cloud
[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN] Direct
ASIC Design Verification Engineer, TPU Cloud
[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US] Onsite Direct
Senior Modem Design Verification Engineer
Amazon Kuiper Manufacturing Enterprises LLC
San Diego, California, USA Onsite Senior Direct
Senior Design Engineer
Newsela
Remote - FTE Remote Senior Direct
ASIC Design Verification Engineer
Amazon Kuiper Manufacturing Enterprises LLC
Austin, Texas, USA Onsite Senior Direct
Satellite Design Verification Engineer
Amazon Kuiper Manufacturing Enterprises LLC
San Diego, California, USA Onsite Mid Direct
Sr. Physical Design Verification Engineer
Annapurna Labs
Austin, Texas, USA Onsite Senior Direct
Senior Verification Engineer
Annapurna Labs Ltd.
Haifa, HA, ISR Onsite Senior Direct
NPU Design Verification Principal/Staff Engineer
Bitdeer Technologies Group
Singapore Principal/Staff Direct
Senior Chip Design Verification Engineer, Port IP Group
NVIDIA
Israel, Tel Aviv Onsite Senior Direct
Senior Chip Design Verification Engineer, Port IP Group
NVIDIA
Israel, Tel Aviv Onsite Senior Direct
Senior/Staff/ Sr Staff Engineer, IP/SoC Design Verification
Renesas Electronics
Bengaluru, KA, IN Onsite mid Direct
Lead ASIC Design Verification Engineer
Amazon Kuiper Manufacturing Enterprises LLC
San Diego, California, USA Onsite Lead Direct
Sr. Physical Design Verification Engineer
Annapurna Labs
Cupertino, California, USA Onsite Senior Direct
Sr. ASIC Design Verification Engineer
Amazon Kuiper Manufacturing Enterprises LLC
Austin, Texas, USA Onsite Senior Direct
Sr. Physical Design Verification Engineer
Annapurna Labs
Cupertino, California, USA Onsite Senior Direct
Sr. Satellite Design Verification Engineer
Amazon Kuiper Manufacturing Enterprises LLC
Irvine, California, USA Onsite Senior Direct
ASIC Design Verification Technical Lead, TPU
[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US] Lead Direct
Senior FPGA Design Engineer
Lynk
Chantilly, VA Onsite Senior Direct
Senior Silicon Engineer- P and D- (gCPU), Design Verification (multiple openings)
[Austin, TX, USA, [500 W 2nd St, Austin, TX 78701, USA], Austin, 78701, TX, US] Onsite Senior Direct
Sr. Design Verification Manager
Annapurna Labs
Cupertino, California, USA Onsite Manager Direct
Verification Engineer
Annapurna Labs Ltd.
Haifa, Haifa, ISR Onsite Direct
Chip CAD DevOps Engineer, Google Cloud
[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US] Direct
Verification Engineer
Annapurna Labs Ltd.
Tel Aviv-Yafo, Tel Aviv, ISR Onsite Direct
Verification Engineer
Annapurna Labs Ltd.
Haifa, HA, ISR Onsite Senior Direct
Physical Design Verification Manager
Annapurna Labs
Cupertino, California, USA Onsite Manager Direct
Senior Engineer, ASIC Development Engineering (IP Verification )
Sandisk
Bengaluru, KA, IN Onsite mid Direct
Senior Mechanical Design Engineer
San Luis Obispo, CA Onsite Senior Direct
Senior Design Engineer
The Lumber Manufactory
Mississippi Onsite Senior Direct
ASIC Design Verification Engineer
Waymo
Mountain View, California, United States Hybrid Mid Direct
Verification Intern
AST SpaceMobile
Hyderabad, Telangana, India Onsite Entry Direct
Senior Digital Design Engineer
Riverlane
Cambridge Hybrid Senior Direct
Verification Engineer
Annapurna Labs Ltd.
Haifa, HA, ISR Onsite Direct
IP Counsel
ZURU
Ahmedabad | India Senior Direct
Digital Design Verification Engineer
OLIX
Bristol Onsite Senior / Staff Direct
Senior Software Engineer - Platform Group
Ash
New York, NY Senior Direct
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Common Questions
- How many Senior Chip Design Verification Engineer Port Ip Group jobs are available?
- JobsGlitch lists active Senior Chip Design Verification Engineer Port Ip Group jobs sourced daily from Greenhouse, Lever, Ashby, Workday, and other top ATS platforms.
- What skills are required for Senior Chip Design Verification Engineer Port Ip Group roles?
- The most in-demand skills for Senior Chip Design Verification Engineer Port Ip Group roles are UVM, RTL verification, SystemVerilog, ASIC Design Verification, Semiconductor platform. Requirements vary by seniority and company.
- What is the average salary for a Senior Chip Design Verification Engineer Port Ip Group?
- The average salary for Senior Chip Design Verification Engineer Port Ip Group roles on JobsGlitch is approximately $564k/year. Compensation varies by location, seniority, and company.
- Are there remote Senior Chip Design Verification Engineer Port Ip Group jobs?
- Yes — 10% of Senior Chip Design Verification Engineer Port Ip Group jobs on JobsGlitch are remote-friendly. Browse remote Senior Chip Design Verification Engineer Port Ip Group jobs at jobsglitch.com/jobs/remote/senior-chip-design-verification-engineer-port-ip-group.