Astera Labs
Technology
PrincipalDesignVerificationEngineer
“Principal Design Verification Engineer at Astera Labs. Skills: Design Verification, UVM, C/C++, System Verilog. Develop test-plans. Develop test-sequences in UVM”
Industry & Context.
Debugging
Authorized to work in Canada
What They're Looking For.
Must Have
Bachelor's in EE, ≥8 years' experience, Experience with C/C++, Experience using scripting tools, Experience developing infrastructure, Experience writing assertions, Experience analyzing coverage data, Prior experience using VIPs, Authorized to work in Canada
Nice to Have
Master's degree preferred, S/W debugging experience, Physical Layer expertise, Link Layer expertise, Transaction Layer expertise, Experience with FPGA-based verification
What You'll Do.
Develop test-sequences in UVM
Develop user-controlled random constraints
Analyze coverage data
Develop VIP abstraction layers
How You'll Work.
Team & Collaboration
Collaborate with RTL designers
Process & Methodology
Prioritize tasks, Plan meetings
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ANONYMOUS · UNFILTERED
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