Astera Labs
Technology
SeniorDesignVerificationEngineer
“Senior Design Verification Engineer at Astera Labs. Skills: Design Verification, UVM, C/C++, SoC/silicon products. Develop test-plans. Develop test-sequences in UVM”
Industry & Context.
Debugging
Authorized to work in Canada, Start immediately
What They're Looking For.
Must Have
Academic and technical background in electrical engineering, Bachelor’s in EE, ≥2 years’ experience supporting or developing complex SoC/silicon products, Professional attitude, Ability to prioritize a dynamic list of multiple tasks, Plan and prepare for customer meetings, Work with minimal guidance and supervision, Experience with integrating C/C++ in System Verilog environments using DPI/PLI, Ability to use scripting tools (Perl/Python) to automate verification infrastructure, Experience in developing infrastructure and tests in a hybrid directed and constrained random environments, Work independently to develop test-plans, Develop related test-sequences in UVM, Generate stimuli, Work collaboratively with RTL designers to debug failures, Develop user-controlled random constraints in transaction-based verification methodology, Experience writing assertions, Cover properties, Analyzing coverage data, Prior experience using Verification IPs from 3rd party vendors, Develop VIP abstraction layers
Nice to Have
Master’s in EE, S/W debugging for SoC based designs, Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe protocol, Experience in memory technologies like DDR4/DDR5/HBM, Experience with FPGA-based verificationulation
What You'll Do.
Develop test-sequences in UVM
Debug failures with RTL designers
Develop user-controlled random constraints
Write cover properties
Analyze coverage data
Integrate Verification IPs
Develop VIP abstraction layers
Debug SoC based designs
Verify Physical Layer
Verify Transaction Layer
How You'll Work.
Team & Collaboration
Collaborate with RTL designers
Communication Scope
Customer meetings
Process & Methodology
Prioritize tasks
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