{ "count" : 39539, "data" : [ { "id" : "69164d7f70f0b99d586f2294", "title" : "Senior Mixed-Signal Silicon Engineer", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 143300.0, "max" : 247600.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "San Diego, California, USA", "locations" : [ "San Diego, California, USA" ], "timestamp" : "2026-06-14T22:37:39.884", "fingerprint" : "45b8913df1d3089b3aca2c68296837c1c9f7c16fd0009c40540edb70d02b8a24", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3123280/apply", "externalId" : "1eef0927-7c61-40f5-aadc-2aab28c2ba32", "industryFunction" : { }, "structuredLocations" : [ { "city" : "San Diego", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "32.7174202,-117.1627720" } ], "locationText" : "San Diego, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Master's", "experienceMinYears" : 7, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "CMOS technologies, Matlab, Verilog-A, Python, Perl, SKILL", "professionalSkills" : [ "Product definition", "Product execution", "Product optimization", "Circuit architectures", "System performance", "Analog interface", "Digital interface", "Bench test plans", "Production test plans", "Volume production" ], "hardSkillsList" : [ "Mixed-signal design", "High-speed DACs", "High-speed ADCs", "Analog blocks", "Mixed-signal blocks", "Circuit layout", "Parasitic extraction", "Simulation", "SERDES", "Data converters", "Clock distribution", "Jitter concepts", "Phase noise concepts" ], "softSkillsList" : [ "Responsive" ], "hardSkills" : [ { "name" : "Mixed-signal design", "level" : "intermediate" }, { "name" : "High-speed DACs", "level" : "intermediate" }, { "name" : "High-speed ADCs", "level" : "intermediate" }, { "name" : "Analog blocks", "level" : "intermediate" }, { "name" : "Mixed-signal blocks", "level" : "intermediate" }, { "name" : "Circuit layout", "level" : "intermediate" }, { "name" : "Parasitic extraction", "level" : "intermediate" }, { "name" : "Simulation", "level" : "intermediate" }, { "name" : "SERDES", "level" : "intermediate" }, { "name" : "Data converters", "level" : "intermediate" }, { "name" : "Clock distribution", "level" : "intermediate" }, { "name" : "Jitter concepts", "level" : "intermediate" }, { "name" : "Phase noise concepts", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Responsive" } ], "majorSkills" : "Mixed-signal silicon, Data converters, SERDES, CMOS technologies", "majorSkillsList" : [ "Mixed-signal silicon", "Data converters", "SERDES", "CMOS technologies" ], "coreResponsibilities" : "Design innovative product solutions, Drive key aspects of product definition, Drive key aspects of product execution, Drive key aspects of product optimization, Architectural definition, Design mixed-signal circuit blocks, Simulate mixed-signal circuit blocks, Layout mixed-signal circuit blocks, Perform extracted simulation, Create power optimized solutions, Create cost optimized solutions, Design high-speed DACs, Design high-speed ADCs, Design analog/mixed-signal blocks, Explore circuit architectures, Perform circuit layout, Perform parasitic extraction, Perform simulation, Define analog interface requirements, Define digital interface requirements, Define supporting digital functions, Specify bench test plans, Specify production test plans, Enable volume production", "teamCollaboration" : "Cross-disciplinary staff; Internal inter-disciplinary team; Third-party suppliers; Cross-functional teams", "domainKnowledge" : "Low Earth Orbit satellites; Broadband connectivity; RFIC; Deeply scaled CMOS; FinFET; SOI; BiCMOS; Bulk CMOS; Time-interleaved ADC; Digitally-assisted analog; SERDES; Data converter clock distribution; Jitter concepts; Phase noise concepts", "domainList" : [ "low-earth-orbit-satellites", "broadband-connectivity", "rfic", "deeply-scaled-cmos", "finfet", "soi", "bicmos", "bulk-cmos", "time-interleaved-adc", "digitally-assisted-analog", "serdes", "data-converter-clock-distribution", "jitter-concepts", "phase-noise-concepts" ], "domainSpecificKnowledge" : [ "Low Earth Orbit satellites", "Broadband connectivity", "RFIC", "Deeply scaled CMOS", "FinFET", "SOI", "BiCMOS", "Bulk CMOS", "Time-interleaved ADC", "Digitally-assisted analog", "SERDES", "Data converter clock distribution", "Jitter concepts", "Phase noise concepts" ], "toolProficiency" : [ "Virtuoso Schematic Editor", "Incisive", "Xcelium", "VCS", "AMS Designer" ], "innovationCreativity" : "Conceive innovative product solutions", "problemSolvingSkills" : "Power/area/performance trade-offs", "specialRequirements" : "Export Control Requirement", "outcomesObjectives" : "Create power optimized solutions; Create cost optimized solutions", "qualificationsBasic" : "Master's degree in Electrical or Communications Engineering, 7+ years of experience in mixed-signal design, Experience in taking designs to volume production, U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S. as a refugee, Granted asylum", "qualificationsPreferred" : "10+ years of experience in high-speed, low-power mixed-signal circuit design, FinFET, SOI, BiCMOS, and Bulk CMOS technologies experience, Knowledge of time-interleaved ADC architectures, Knowledge of digitally-assisted analog techniques, Proficient in modeling circuits using Matlab, Proficient in modeling circuits using Verilog-A, Knowledgeable in SERDES, Knowledgeable in data converter clock distribution design, Knowledgeable in jitter/phase noise concepts, Proficiency with digital and mixed signal simulators, Knowledge of the Cadence Virtuoso Design Framework, Knowledge of Virtuoso Schematic Editor, Knowledge of Virtuoso Analog Design Environment, Knowledge of programming in Python, Knowledge of programming in Perl, Knowledge of programming in SKILL", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon LEO is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Come work at Amazon! The Role: As Senior Mixed-Signal Silicon Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third-party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment. As a member of the RFIC team, you will be responsible for the architectural definition, design, simulation, layout, and extracted simulation for transmit and receive mixed-signal circuit blocks including data converters and aspects of SERDES. Strong focus will be on creating power and cost optimized solutions for a given system performance. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities • Design & optimize high-speed (>800Msps) medium resolution (5-8 bits) DACs & ADCs and other analog/mixed-signal blocks in deeply scaled CMOS technologies. • Explore circuit architectures for power/area/performance trade-offs. • Perform circuit layout, parasitic extraction and simulation. • Collaborate with cross-functional teams to define analog/digital interface requirements and define supporting digital functions. • Specify bench and production test plans for your design and enable volume production. Basic Qualifications: - Master's degree in Electrical or Communications Engineering or a related field - 7+ years of experience in mixed-signal design, preferably in an advanced node. - Experience in taking designs to volume production. Preferred Qualifications: - 10+ years of experience in high-speed, low-power mixed-signal circuit design, layout and verification in the following : FinFET, SOI, BiCMOS, and Bulk CMOS technologies. - Knowledge of time-interleaved ADC architectures, digitally-assisted analog techniques. - Proficient in modeling circuits using Matlab, Verilog-A. - Knowledgeable in SERDES, data converter clock distribution design and jitter/phase noise concepts. - Proficiency with digital and mixed signal simulators, for example Incisive/Xcelium, VCS, AMS Designer. - Knowledge of the Cadence Virtuoso Design Framework, Virtuoso Schematic Editor, and Analog Design Environment (Explorer/Assembler). - Knowledge of programming in Python, Perl, and SKILL. - Effective written and verbal communication skills Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits . This position will remain posted until filled. Applicants should apply via our internal or external career site.", "summaryDescription" : "Senior Mixed-Signal Silicon Engineer at Amazon Kuiper Manufacturing Enterprises LLC. Skills: Mixed-signal silicon, Data converters, SERDES, CMOS technologies. Design innovative product solutions. Drive key aspects of product definition", "postedDate" : "2026-06-12T22:59:06.150", "createdAt" : "2026-06-12T22:59:06.150", "lastUpdated" : "2026-06-14T22:37:39.884", "ingestTimestamp" : "2026-06-12T22:59:06.150", "mongoId" : "69164d7f70f0b99d586f2294", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3123280/apply", "salaryAnnualMin" : 143300, "salaryAnnualMax" : 247600, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Mixed-signal design", "High-speed DACs", "High-speed ADCs", "Analog blocks", "Mixed-signal blocks", "Circuit layout", "Parasitic extraction", "Simulation", "SERDES", "Data converters", "Clock distribution", "Jitter concepts", "Phase noise concepts", "Responsive", "Mixed-signal silicon", "CMOS technologies", "Product definition", "Product execution", "Product optimization", "Circuit architectures", "System performance", "Analog interface", "Digital interface", "Bench test plans", "Production test plans", "Volume production", "Low Earth Orbit satellites", "Broadband connectivity", "RFIC", "Deeply scaled CMOS", "FinFET", "SOI", "BiCMOS", "Bulk CMOS", "Time-interleaved ADC", "Digitally-assisted analog", "Data converter clock distribution", "Virtuoso Schematic Editor", "Incisive", "Xcelium", "VCS", "AMS Designer" ], "skillCount" : 42, "jobCategory" : "other", "dataQualityScore" : 1.0, "_score" : 483.4919, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a305cf0f292fd229cf64237", "title" : "Traffic Signal Apprentice", "industry" : "Government", "salary" : { "min" : 45000.0, "max" : 65000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline data for an entry-level Traffic Signal Apprentice in Marietta, United States, adjusted for government industry and full-time employment." }, "location" : "Marietta, GA", "locations" : [ "Marietta, GA" ], "timestamp" : "2026-06-16T08:27:26.313", "fingerprint" : "bab75ae3d61958ccc35cb68470cd6d0b9d363a10047faa7c3c58aabffdec0253", "source" : "jazzhr", "language" : "en", "externalId" : "t3XP52g84f", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Marietta", "state" : "Georgia", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "33.9528472,-84.5496148" } ], "locationText" : "Marietta, Georgia, United States", "coreResponsibilities" : "Assist in the installation of traffic signal equipment, Perform routine maintenance on traffic signal systems, Respond to traffic signal malfunctions, Learn traffic signal control principles, Assist with traffic signal timing adjustments, Operate basic tools and equipment", "teamCollaboration" : "Work with senior technicians; Coordinate with city departments", "domainKnowledge" : "Traffic signal systems; Traffic control principles", "domainList" : [ "traffic-signal-systems", "traffic-control-principles" ], "domainSpecificKnowledge" : [ "Traffic signal systems", "Traffic control principles" ], "continuousLearning" : "Apprenticeship program", "problemSolvingSkills" : "Troubleshoot signal issues", "specialRequirements" : "Valid driver's license", "qualificationsBasic" : "Traffic Signal Apprentice training", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "summaryDescription" : "Traffic Signal Apprentice. Assist in the installation of traffic signal equipment. Perform routine maintenance on traffic signal systems", "createdAt" : "2026-06-15T22:18:59.431", "lastUpdated" : "2026-06-16T08:27:26.313", "ingestTimestamp" : "2026-06-15T22:18:59.431", "mongoId" : "6a305cf0f292fd229cf64237", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 45000, "salaryAnnualMax" : 65000, "salaryBand" : "30k-50k", "hasSalary" : true, "allSkills" : [ "Traffic signal systems", "Traffic control principles" ], "skillCount" : 2, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Entry", "dataQualityScore" : 0.44444445, "_score" : 439.55887, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.9 }, { "id" : "6a2a688574d8ee00a06346f5", "title" : "Design layout Engineer", "company" : "Micron Technology", "industry" : "Technology", "salary" : { "min" : 45000.0, "max" : 65000.0, "currency" : "EUR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "The estimated salary is based on the market baseline for a Mid-level Design Layout Engineer in Avezzano, Italy, within the Technology industry, adjusted for company size and seniority." }, "location" : "Avezzano (AQ), Italy", "locations" : [ "Avezzano (AQ), Italy" ], "timestamp" : "2026-06-12T21:06:07.485", "fingerprint" : "8a7d67e4f59f296978adf4661ea7c16d7f68b30ad82f389701cae172d6f2a80c", "source" : "workday", "language" : "en", "applyUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Avezzano-AQ-Italy/Design-layout-Engineer_JR103806", "externalId" : "JR103806", "industryFunction" : { }, "locationPoint" : "42.02896,13.42641", "structuredLocations" : [ { "city" : "Avezzano", "country" : "Italy", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "42.0402067,13.4545144" } ], "locationText" : "Avezzano, Italy", "employmentType" : "FULL_TIME", "minimumEducation" : "B.S. in Electrical Engineering, Electronics, data science, or a related field, with equivalent experience considered", "technicalSkills" : "Analog circuits, Digital circuits, Mixed-signal circuits, Python", "professionalSkills" : [ "Layout design", "Design validation", "Manufacturability", "Quality targets", "Performance targets", "Methodology improvement" ], "hardSkillsList" : [ "Layout integration", "Floorplanning", "Placement", "Routing", "Parasitic extraction", "Simulation correlation", "Silicon learning", "Tape-out revisions", "Matching", "Shielding", "EM", "ESD", "Latch-up", "HV design constraints" ], "softSkillsList" : [ "Problem-solving", "Communication" ], "hardSkills" : [ { "name" : "Layout integration", "level" : "intermediate" }, { "name" : "Floorplanning", "level" : "intermediate" }, { "name" : "Placement", "level" : "intermediate" }, { "name" : "Routing", "level" : "intermediate" }, { "name" : "Parasitic extraction", "level" : "intermediate" }, { "name" : "Simulation correlation", "level" : "intermediate" }, { "name" : "Silicon learning", "level" : "intermediate" }, { "name" : "Tape-out revisions", "level" : "intermediate" }, { "name" : "Matching", "level" : "intermediate" }, { "name" : "Shielding", "level" : "intermediate" }, { "name" : "EM", "level" : "intermediate" }, { "name" : "ESD", "level" : "intermediate" }, { "name" : "Latch-up", "level" : "intermediate" }, { "name" : "HV design constraints", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Problem-solving" }, { "name" : "Communication" } ], "majorSkills" : "Layout design, Automation, AI-assisted design", "majorSkillsList" : [ "Layout design", "Automation", "AI-assisted design" ], "coreResponsibilities" : "Design complex analog layout blocks, Design mixed-signal layout blocks, Design custom digital layout blocks, Perform layout integration, Perform floorplanning, Perform placement, Perform routing, Perform parasitic-aware optimization, Support design validation, Support parasitic extraction, Support simulation correlation, Support silicon learning, Support tape-out revisions, Develop automation methodologies, Drive automation methodologies, Develop AI-assisted layout methodologies, Drive AI-assisted layout methodologies, Contribute to methodology improvement, Contribute to user documentation", "teamCollaboration" : "Multi-functional teams; Build teams; CAD teams; Modeling teams; Product engineering teams", "domainKnowledge" : "NAND Flash memory; Non-volatile memory; Analog circuits; Digital circuits; Mixed-signal circuits; Memory storage solutions", "domainList" : [ "nand-flash-memory", "non-volatile-memory", "analog-circuits", "digital-circuits", "mixed-signal-circuits", "memory-storage-solutions" ], "domainSpecificKnowledge" : [ "NAND Flash memory", "Non-volatile memory", "Analog circuits", "Digital circuits", "Mixed-signal circuits", "Memory storage solutions" ], "toolProficiency" : [ "Cadence Virtuoso", "Calibre LVS/DRC" ], "documentationSkills" : "User documentation", "innovationCreativity" : "AI-assisted methodologies; Data-driven layout optimization; Scalable build approaches; High-productivity build approaches; Intelligent build approaches", "problemSolvingSkills" : "Problem-solving", "outcomesObjectives" : "Ensure manufacturability; Ensure quality targets; Ensure performance targets", "qualificationsBasic" : "B.S. in Electrical Engineering, Electronics, data science, or related field, Hands-on layout and verification tools experience, Understanding of advanced layout techniques, Experience with AI-assisted design methodologies or data-driven optimization", "qualificationsPreferred" : "Experience in NAND Flash or other non-volatile memory technologies, Familiarity with scripting and automation applied to layout or design flows, Experience collaborating on silicon validation, bring-up, or yield improvement", "remoteFriendly" : true, "workSiteFlexibility" : "Remote", "rawDescription" : "**Our vision is to transform how the world uses information to enrich life for** _**all**_**.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. .D**epartment Introduction** The Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital and mixed-signal circuits enabling advanced NAND Flash memory products. Close collaboration with multi-functional teams ensures scalable, manufacturable, and reliable solutions across technology nodes. **Role Overview** As a Layout Design Engineer at Micron Semiconductor Italia, you will play a critical role in the physical implementation of advanced NAND Flash products, working across analog, custom digital, and mixed‑signal circuits. Beyond traditional layout excellence, this role places strong emphasis on automation, AI‑assisted methodologies, and data‑driven layout optimization, which are central to Micron’s future design strategy. You will actively contribute to evolving the layout field from manual execution toward scalable, high‑productivity, and intelligent build approaches. **Responsibilities** Responsibilities include, but not limited to: • Design and implement complex analog, mixed-signal, and custom digital layout blocks (e.g., charge pumps, regulators, oscillators, IO, sensors). • Perform layout integration activities including floorplanning, placement, routing, and parasitic-aware optimization. • Support design validation through parasitic extraction, simulation correlation, silicon learning, and tape-out revisions. • Collaborate with multi-functional teams (build, CAD, modeling, product engineering) to ensure manufacturability, quality, and performance targets. • Develop and drive automation and AI-assisted layout methodologies (e.g., parameterized layout, scripting, data-driven optimization). • Contribute to methodology improvement, user documentation **Min Qualifications** • B.S. in Electrical Engineering, Electronics, data science, or a related field, with equivalent experience considered. • Hands-on experience with layout and verification tools (e.g., Cadence Virtuoso, Calibre LVS/DRC). • understanding of advanced layout techniques (matching, shielding, EM, ESD, latch-up, HV design constraints). • Experience with AI-assisted design methodologies or data-driven optimization approaches. • Strong problem-solving and communication skills, with ability to work in multi-functional environments. **Preferred Qualifications** • Experience in NAND Flash or other non-volatile memory technologies. • Familiarity with scripting and automation (e.g., Python) applied to layout or design flows. • Experience collaborating on silicon validation, bring-up, or yield improvement activities. The base salary range that Micron estimates it could pay in for this position full-time is: 29.000,00 € - 48.000,00 € per year, with B1 CCNL Level. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for the position. In addition to base pay, the remuneration package also includes: eligibility for a variable plan subject to the personal achievement of objectives and the company's performance, and benefits, which -at the discretion of the company- currently include meal vouchers, corporate welfare, yearly allowance of remote working days, supplementary health insurance, life coverage, Employee Assistance Program. Please refer to this page to check our current benefit offering: [EMEA Benefits](https://www.micron.com/about/careers/emea-benefits) All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. Remuneration is determined by objective criteria, regardless of gender and of any other factor protected by applicable federal, state, or local laws. To request assistance with the application process and/or for reasonable accommodations, please contact [ _HRsupport_EMEA @micron.com_](mailto:HRsupport_EMEA@micron.com). Before uploading your CV to apply for this position, please review our [ _Applicant Privacy Notice_](https://www.micron.com/Privacy/applicant-Privacy-Notice) and [ _Employment Privacy Notice_](https://www.micron.com/Privacy/Employment-Privacy-Notice). Micron recruiters use review tools to identify your unique skill set based on the information in your CV, to inform the recruiter of skills you may have that are not listed on your CV (based on your career history and work experience), to supplement the information provided in your CV with information obtained from publicly accessible professional-oriented sources (such as your publicly available LinkedIn profile) and to assess how closely your skill set matches the defined skill set for this position. While submitting your CV through this platform is not obligatory, we encourage you to do so. If you do not want to benefit from the skill and qualification matching features, then you should not upload your CV through this platform. Instead, email your CV to [ _TA_EMEA @micron.com_](mailto:ta_emea@micron.com) along with the Req Id number listed in the job description. Your CV will be forwarded to the appropriate recruiter for review. Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc. **About Micron Technology, Inc.** We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life _for all_. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® brand. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit [_micron.com/careers_](http://micron.com/careers)", "summaryDescription" : "Design layout Engineer at Micron Technology. Skills: Layout design, Automation, AI-assisted design. Design complex analog layout blocks. Design mixed-signal layout blocks", "postedDate" : "2026-06-11T15:57:00.333", "createdAt" : "2026-06-11T15:57:00.169", "lastUpdated" : "2026-06-12T21:06:07.485", "ingestTimestamp" : "2026-06-11T15:57:00.169", "mongoId" : "6a2a688574d8ee00a06346f5", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Avezzano-AQ-Italy/Design-layout-Engineer_JR103806", "salaryBand" : "30k-50k", "hasSalary" : false, "allSkills" : [ "Layout integration", "Floorplanning", "Placement", "Routing", "Parasitic extraction", "Simulation correlation", "Silicon learning", "Tape-out revisions", "Matching", "Shielding", "EM", "ESD", "Latch-up", "HV design constraints", "Problem-solving", "Communication", "Layout design", "Automation", "AI-assisted design", "Design validation", "Manufacturability", "Quality targets", "Performance targets", "Methodology improvement", "NAND Flash memory", "Non-volatile memory", "Analog circuits", "Digital circuits", "Mixed-signal circuits", "Memory storage solutions", "Cadence Virtuoso", "Calibre LVS/DRC" ], "skillCount" : 32, "jobCategory" : "engineering", "seniorityLevel" : "mid", "dataQualityScore" : 0.8888889, "_score" : 431.52246, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2cd32174d8ee00a0a35b51", "title" : "Layout Designer", "company" : "HDR", "industry" : "Consulting", "salary" : { "min" : 75000.0, "max" : 105000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Layout Designer in Omaha, United States, adjusted for the Engineering industry and company size." }, "location" : "United States-Nebraska-Omaha", "locations" : [ "United States-Nebraska-Omaha" ], "timestamp" : "2026-06-16T02:08:31.517", "fingerprint" : "b26b9ddf238e3faa03dfe0ce6a700b2d6f476a7e70e0f6f994da132b797daafb", "source" : "taleo", "language" : "en", "applyUrl" : "https://hdr.taleo.net/careersection/ex/jobdetail.ftl?job=783343", "externalId" : "783343", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Omaha", "state" : "Nebraska", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "41.2587459,-95.9383758" } ], "locationText" : "Omaha, Nebraska, United States", "employmentType" : "FULL_TIME", "professionalSkills" : [ "Layout design", "Document design", "Brand standards" ], "softSkillsList" : [ "Leadership" ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "Layout design, Document formatting, Brand consistency", "majorSkillsList" : [ "Layout design", "Document formatting", "Brand consistency" ], "coreResponsibilities" : "Design and format proposals, qualifications, Standard Form 330, Develop and update document layouts, templates, and design, Prepare and publish draft documents, ensuring accuracy and, Coordinate production, printing, and final delivery, Perform minor editing, formatting, and photo adjustments as, Collaborate with graphic designers, marketing coordinators, proposal managers,", "teamCollaboration" : "Graphic designers; Marketing coordinators; Proposal managers; Leaders", "domainKnowledge" : "Architecture; Engineering; Construction industry", "domainList" : [ "architecture", "engineering", "construction-industry" ], "domainSpecificKnowledge" : [ "Architecture", "Engineering", "Construction industry" ], "documentationSkills" : "Document design; Document layouts; Design guides", "problemSolvingSkills" : "Organizational skills; Problem-solving skills; Troubleshooting skills", "specialRequirements" : "Occasional overtime, Weekend work", "qualificationsBasic" : "3 years of relevant experience in layout design, marketing, or a related field, 3 years experience in the architecture, engineering, construction industry", "qualificationsPreferred" : "Understanding of design principles, typography, and color usage, Ability to collaborate effectively and incorporate feedback in a team environment, Ability to manage multiple projects, prioritize effectively, and meet deadlines, Organizational, problem-solving, and troubleshooting skills", "remoteFriendly" : false, "rawDescription" : "At HDR, our employee-owners are fully engaged in creating a welcoming environment where each of us is valued and respected, a place where everyone is empowered to bring their authentic selves and novel ideas to work every day. As we foster a culture of inclusion throughout our company and within our communities, we constantly ask ourselves: What is our impact on the world? Watch Our Story: ' https://www.hdrinc.com/our-story' Each and every role throughout our organization makes a difference in our ability to change the world for the better. Read further to learn how you could help make great things possible not only in your community, but around the world. At HDR, our employee‑ownership model shapes everything we do, including how we support and care for our people. Our diverse service lines, including Water, Architecture, Building Engineering Services, Field Services, Power, Waste, Industrial, and Transportation reflect our commitment to shaping resilient, sustainable, and forward‑thinking communities around the world. Across these disciplines, our teams design and deliver solutions that safeguard public health, enhance quality of life, power innovation, and drive responsible growth. Whether advancing clean water, creating healing and learning environments, engineering next‑generation facilities, or building the infrastructure that moves people and energy, our work is rooted in technical excellence and a shared sense of purpose. Our employee‑owners collaborate across specialties, combining creativity, precision, and deep expertise to solve the most complex challenges facing our clients and communities. The Layout Designer is responsible for document design within the Corporate Marketing Team, which also includes strategic pursuit proposals. This role focuses on producing high-quality, visually consistent documents that align with brand standards and project goals. This role operates in a fast-paced, deadline-driven team environment that requires strong attention to detail and the ability to manage multiple priorities. The Layout Designer must be proactive, adaptable, and able to respond quickly to changing deadlines and project needs. Flexibility and comfort with shifting workloads and varied assignments are essential. Primary Responsibilities Design and format proposals, qualifications, Standard Form 330 documents, and other marketing materials Develop and update document layouts, templates, and design guides Prepare and publish draft documents, ensuring accuracy and visual consistency Coordinate production, printing, and final delivery Perform minor editing, formatting, and photo adjustments as needed Collaborate with graphic designers, marketing coordinators, proposal managers, and leaders Demonstrate effective leadership Occasional overtime and weekend work may be needed Preferred Qualifications: 3 years of relevant experience in layout design, marketing, or a related field 3 years experience in the architecture, engineering, construction industry Strong understanding of design principles, typography, and color usage Ability to collaborate effectively and incorporate feedback in a team environment Ability to manage multiple projects, prioritize effectively, and meet deadlines Strong organizational, problem-solving, and troubleshooting skills ", "summaryDescription" : "Layout Designer at HDR. Skills: Layout design, Document formatting, Brand consistency. Design and format proposals, qualifications, Standard Form 330. Develop and update document layouts, templates, and design", "createdAt" : "2026-06-14T19:58:11.522", "lastUpdated" : "2026-06-16T02:08:31.517", "ingestTimestamp" : "2026-06-14T19:58:11.522", "mongoId" : "6a2cd32174d8ee00a0a35b51", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 75000, "salaryAnnualMax" : 105000, "salaryBand" : "75k-100k", "hasSalary" : true, "allSkills" : [ "Leadership", "Layout design", "Document formatting", "Brand consistency", "Document design", "Brand standards", "Architecture", "Engineering", "Construction industry" ], "skillCount" : 9, "jobCategory" : "product", "jobSubcategory" : "design", "seniorityLevel" : "Mid", "dataQualityScore" : 0.7777778, "_score" : 410.3399, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Engineering", "llmIndustryConfidence" : 0.95 }, { "id" : "6a2a951774d8ee00a0697839", "title" : "Mixed-Signal IC Design Engineer", "company" : "CERN", "industry" : "Research", "salary" : { "min" : 125000.0, "max" : 165000.0, "currency" : "CHF", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Mixed-Signal IC Design Engineer in Geneva, Switzerland, adjusted for the technology industry and a large research organization." }, "location" : "Geneva, GENEVA, CH", "locations" : [ "Geneva", "GENEVA", "CH" ], "timestamp" : "2026-06-14T19:36:12.782", "fingerprint" : "83d10802b32d76d310dce8f67d05b1534d1f3c7bb420e6509cc508da210357fc", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/CERN/744000131412229-mixed-signal-ic-design-engineer-ep-ese-me-2026-107-grap-", "externalId" : "744000131412229", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Geneva", "state" : "Geneva", "country" : "Switzerland", "continent" : "eu", "source" : "llm", "workMode" : "hybrid", "geo" : "46.2017559,6.1466014" } ], "locationText" : "Geneva, Geneva, Switzerland", "employmentType" : "FULL_TIME", "experienceMinYears" : 0, "experienceMaxYears" : 2, "experienceLevel" : "entry", "technicalSkills" : "CMOS, Analogue-to-digital converters, Silicon photonics, Optical receiver circuits, TIA, ADC, DAC, Control systems, Python, Bash, MATLAB, Ansys HFSS, Simulia CST", "professionalSkills" : [ "IC design", "Electronics engineering", "Particle physics detectors", "High speed links", "Detector technologies", "Communication systems" ], "hardSkillsList" : [ "Analogue circuit design", "Mixed-signal circuit design", "CMOS circuit design", "Laboratory testing", "Circuit characterisation", "Circuit validation", "Radiation qualification", "Single-event effects", "Total ionising dose", "Physical verification", "Electromagnetics simulation" ], "softSkillsList" : [ "Work independently" ], "hardSkills" : [ { "name" : "Analogue circuit design", "level" : "intermediate" }, { "name" : "Mixed-signal circuit design", "level" : "intermediate" }, { "name" : "CMOS circuit design", "level" : "intermediate" }, { "name" : "Laboratory testing", "level" : "intermediate" }, { "name" : "Circuit characterisation", "level" : "intermediate" }, { "name" : "Circuit validation", "level" : "intermediate" }, { "name" : "Radiation qualification", "level" : "intermediate" }, { "name" : "Single-event effects", "level" : "intermediate" }, { "name" : "Total ionising dose", "level" : "intermediate" }, { "name" : "Physical verification", "level" : "intermediate" }, { "name" : "Electromagnetics simulation", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Work independently" } ], "majorSkills" : "Mixed-Signal IC Design, Analogue/Custom IC Design, High-speed CMOS circuits", "majorSkillsList" : [ "Mixed-Signal IC Design", "Analogue/Custom IC Design", "High-speed CMOS circuits" ], "coreResponsibilities" : "Study architectures for analogue and mixed-signal circuits, Define architectures for analogue and mixed-signal circuits, Design CMOS circuit blocks, Verify CMOS circuit blocks, Perform laboratory testing of circuits, Perform characterisation of circuits, Perform validation of circuits, Carry out radiation qualification of manufactured devices", "teamCollaboration" : "Work independently", "domainKnowledge" : "High Energy Physics; Radiation-tolerant systems; Optical communication systems; Silicon photonics; Particle physics detectors; Analogue electronics; Mixed-signal circuits; CMOS circuits; Clock generation; Clock distribution; DLL circuits; PLL circuits; CDR circuits; Wireline drivers; Laser drivers; External modulators; Electromagnetics", "domainList" : [ "high-energy-physics", "radiation-tolerant-systems", "optical-communication-systems", "silicon-photonics", "particle-physics-detectors", "analogue-electronics", "mixed-signal-circuits", "cmos-circuits", "clock-generation", "clock-distribution", "dll-circuits", "pll-circuits", "cdr-circuits", "wireline-drivers", "laser-drivers", "external-modulators", "electromagnetics" ], "domainSpecificKnowledge" : [ "High Energy Physics", "Radiation-tolerant systems", "Optical communication systems", "Silicon photonics", "Particle physics detectors", "Analogue electronics", "Mixed-signal circuits", "CMOS circuits", "Clock generation", "Clock distribution", "DLL circuits", "PLL circuits", "CDR circuits", "Wireline drivers", "Laser drivers", "External modulators", "Electromagnetics" ], "toolProficiency" : [ "Cadence Virtuoso", "Siemens Calibre", "Cadence PVS" ], "continuousLearning" : "Language classes", "innovationCreativity" : "Prototype development; System demonstrators", "problemSolvingSkills" : "Engineering problems analysis; Simulation methods", "specialRequirements" : "Work during nights, Work during Sundays, Work during official holidays, Work in Radiation Areas, Work during nights, Sundays and official holidays, when required by the needs of the Organization", "qualificationsBasic" : "Master's degree with 2 to 6 years of post-graduation professional experience, PhD with no more than 3 years of post-graduation professional experience, National of a CERN Member or Associate Member State, Never had a CERN fellow or graduate contract before", "qualificationsPreferred" : "Experience with electromagnetics (EM) simulation tools", "remoteFriendly" : false, "workSiteFlexibility" : "Hybrid", "rawDescription" : "Join the CERN Experimental Physics Department and help develop next-generation detector technologies for future High Energy Physics experiments. As part of the High Speed Links programme, you will contribute to radiation-tolerant optical communication systems that combine custom ASICs, silicon photonics, optical modules, and FPGA platforms to enable reliable high-speed data transmission in extreme environments. We are seeking an Analogue/Custom IC Design Engineer to design and validate advanced communication ASICs and high-speed CMOS circuits for particle physics detectors. The role involves taking cutting-edge technologies from prototype development through to full system demonstrators. Your responsibilities * Study and define architectures for analogue and mixed-signal circuits that enable high-speed communication systems using silicon photonics. * Design and verify CMOS circuit blocks such as clock and data recovery (CDR) circuits, high speed clock distribution networks and high-speed analogue-to-digital converters (ADCs). * Perform laboratory testing, characterisation, and validation of circuits. * Carry out radiation qualification (single-event effects and total ionising dose) of manufactured devices. Your profile * A strong background in digital and analogue electronics, ideally in an IC design environment. * Familiarity with clock generation and distribution, including fundamentals of DLL, PLL, and CDR circuits. * The ability to solve engineering problems using a variety of analysis and simulation methods. * Hands-on experience in the design, testing and debugging of electronic circuits. * A strong team player who can also work independently. Skills * Design, simulation and layout of CMOS integrated circuits using Cadence Virtuoso. * Working knowledge of physical verification flows (DRC, LVS, PEX) using Siemens Calibre or Cadence PVS. * Knowledge of at least one of the following: optical receiver circuits, high data rate drivers (wireline, laser and/or external modulators), PLL and CDR design, TIA, ADC and DAC design, control systems. * Working knowledge of at least one programming, scripting, or data analysis language (e.g., Python, Bash, MATLAB). * Experience with electromagnetics (EM) simulation tools (e.g., Ansys HFSS, Simulia CST) is considered a plus. * Spoken and written English, with a commitment to learn French. Eligibility criteria: * You are a national of a [CERN Member or Associate Member State](https://home.cern/about/member-states). * You have a professional background in Electronics Engineering (or a related field) and have either: * a Master's degree with 2 to 6 years of post-graduation professional experience; * or a PhD with no more than 3 years of post-graduation professional experience. * You have never had a CERN fellow or graduate contract before. ## Additional Information Job closing date: 01.07.2026 at 23:59 CEST. Contract duration: 24 months, with a possible extension up to 36 months maximum. Working hours: 40 hours per week Job flexibility: Hybrid Target start date: 01-August-2026 This position involves: * Work during nights, Sundays and official holidays. * Work in Radiation Areas. * Work during nights, Sundays and official holidays, when required by the needs of the Organization. Job reference: EP-ESE-ME-2026-107-GRAP Field of work: Electrical or Electronics Engineering Benchmark job: 200050 - Electronics Engineer Global Benefits * A monthly stipend between 6372-7004 Swiss Francs per month (tax free) depending on your degree. * 30 days of paid leave per year plus 2 weeks annual closure. * Coverage by CERN’s comprehensive health insurance scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund. * Family, child and infant monthly allowances depending on your individual circumstances. * A relocation package (installation grant and travel expenses) depending on your individual circumstances. * Possibility to extend your contract up to 36 months. * On-the-job and formal training including language classes. Overview of CERN - Discover a world where the impossible is made possible! At CERN, the European Organization for Nuclear Research, we are pushing the frontiers of science and technology. Our groundbreaking work brings together not only physicists but also a diverse range of professionals from engineering, technical, scientific, and administrative fields. Together, we foster an environment where innovation and collaboration thrive. Every day, we face exciting new challenges and opportunities to contribute to cutting-edge research that shapes our understanding of the universe. We meet these challenges through the diverse perspectives within our teams, ensuring every contribution is valued and driving our shared sense of inclusion and purpose. Diversity is a core value of CERN since its foundation, and it remains central to our mission and continued success. If you are ready to be part of a dynamic, inclusive community pushing the boundaries of knowledge, CERN is the place where your curiosity and skills can thrive. Be part of our mission to uncover what lies at the heart of the universe! TAKE PART! More information about us, here:[careers.cern](https://careers.cern/)", "summaryDescription" : "Mixed-Signal IC Design Engineer at CERN. Skills: Mixed-Signal IC Design, Analogue/Custom IC Design, High-speed CMOS circuits. Study architectures for analogue and mixed-signal circuits. Define architectures for analogue and mixed-signal circuits", "postedDate" : "2026-06-10T09:43:53.000", "createdAt" : "2026-06-12T02:16:03.984", "lastUpdated" : "2026-06-14T19:36:12.782", "ingestTimestamp" : "2026-06-12T02:16:03.984", "mongoId" : "6a2a951774d8ee00a0697839", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "100k-150k", "hasSalary" : false, "allSkills" : [ "Analogue circuit design", "Mixed-signal circuit design", "CMOS circuit design", "Laboratory testing", "Circuit characterisation", "Circuit validation", "Radiation qualification", "Single-event effects", "Total ionising dose", "Physical verification", "Electromagnetics simulation", "Work independently", "Mixed-Signal IC Design", "Analogue/Custom IC Design", "High-speed CMOS circuits", "IC design", "Electronics engineering", "Particle physics detectors", "High speed links", "Detector technologies", "Communication systems", "High Energy Physics", "Radiation-tolerant systems", "Optical communication systems", "Silicon photonics", "Analogue electronics", "Mixed-signal circuits", "CMOS circuits", "Clock generation", "Clock distribution", "DLL circuits", "PLL circuits", "CDR circuits", "Wireline drivers", "Laser drivers", "External modulators", "Electromagnetics", "Cadence Virtuoso", "Siemens Calibre", "Cadence PVS" ], "skillCount" : 40, "jobCategory" : "research", "jobSubcategory" : "EP", "dataQualityScore" : 1.0, "_score" : 409.07977, "daysOld" : 4, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a2a4d4874d8ee00a05ecee2", "title" : "Mixed-Signal IC Design Engineer", "company" : "CERN", "industry" : "Research", "salary" : { "min" : 125000.0, "max" : 165000.0, "currency" : "CHF", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Mixed-Signal IC Design Engineer in Geneva, Switzerland, adjusted for the technology industry and a large research organization." }, "location" : "Geneva, GENEVA, CH", "locations" : [ "Geneva", "GENEVA", "CH" ], "timestamp" : "2026-06-14T23:54:22.820", "fingerprint" : "850dabf593b4fd58af796be42cc4a42871f325460592f66ff2e3c91f2b80d02a", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/CERN/744000131412229-mixed-signal-ic-design-engineer-ep-ese-me-2026-107-grap-", "externalId" : "744000131412229", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Geneva", "state" : "Geneva", "country" : "Switzerland", "continent" : "eu", "source" : "llm", "workMode" : "hybrid", "geo" : "46.2017559,6.1466014" } ], "locationText" : "Geneva, Geneva, Switzerland", "employmentType" : "FULL_TIME", "experienceMinYears" : 0, "experienceMaxYears" : 2, "experienceLevel" : "entry", "technicalSkills" : "CMOS, Analogue-to-digital converters, Silicon photonics, Optical receiver circuits, TIA, ADC, DAC, Control systems, Python, Bash, MATLAB, Ansys HFSS, Simulia CST", "professionalSkills" : [ "IC design", "Electronics engineering", "Particle physics detectors", "High speed links", "Detector technologies", "Communication systems" ], "hardSkillsList" : [ "Analogue circuit design", "Mixed-signal circuit design", "CMOS circuit design", "Laboratory testing", "Circuit characterisation", "Circuit validation", "Radiation qualification", "Single-event effects", "Total ionising dose", "Physical verification", "Electromagnetics simulation" ], "softSkillsList" : [ "Work independently" ], "hardSkills" : [ { "name" : "Analogue circuit design", "level" : "intermediate" }, { "name" : "Mixed-signal circuit design", "level" : "intermediate" }, { "name" : "CMOS circuit design", "level" : "intermediate" }, { "name" : "Laboratory testing", "level" : "intermediate" }, { "name" : "Circuit characterisation", "level" : "intermediate" }, { "name" : "Circuit validation", "level" : "intermediate" }, { "name" : "Radiation qualification", "level" : "intermediate" }, { "name" : "Single-event effects", "level" : "intermediate" }, { "name" : "Total ionising dose", "level" : "intermediate" }, { "name" : "Physical verification", "level" : "intermediate" }, { "name" : "Electromagnetics simulation", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Work independently" } ], "majorSkills" : "Mixed-Signal IC Design, Analogue IC Design, High-speed CMOS circuits, Radiation-tolerant optical communication", "majorSkillsList" : [ "Mixed-Signal IC Design", "Analogue IC Design", "High-speed CMOS circuits", "Radiation-tolerant optical communication" ], "coreResponsibilities" : "Study architectures for analogue circuits, Define architectures for mixed-signal circuits, Design CMOS circuit blocks, Verify CMOS circuit blocks, Perform laboratory testing, Perform characterisation, Perform validation of circuits, Carry out radiation qualification", "teamCollaboration" : "Work independently", "domainKnowledge" : "High Energy Physics; Particle physics detectors; Radiation-tolerant systems; Optical communication systems; Silicon photonics; ASICs; FPGA platforms; CMOS circuits; DLL; PLL; CDR circuits; Wireline drivers; External modulators", "domainList" : [ "high-energy-physics", "particle-physics-detectors", "radiation-tolerant-systems", "optical-communication-systems", "silicon-photonics", "asics", "fpga-platforms", "cmos-circuits", "dll", "pll", "cdr-circuits", "wireline-drivers", "external-modulators" ], "domainSpecificKnowledge" : [ "High Energy Physics", "Particle physics detectors", "Radiation-tolerant systems", "Optical communication systems", "Silicon photonics", "ASICs", "FPGA platforms", "CMOS circuits", "DLL", "PLL", "CDR circuits", "Wireline drivers", "External modulators" ], "toolProficiency" : [ "Cadence Virtuoso", "Siemens Calibre", "Cadence PVS" ], "continuousLearning" : "Language classes", "innovationCreativity" : "Prototype development; System demonstrators", "problemSolvingSkills" : "Engineering problems analysis; Simulation methods", "specialRequirements" : "Work during nights, Work during Sundays, Work during official holidays, Work in Radiation Areas, Work during nights, Sundays and official holidays, when required by the needs of the Organization", "qualificationsBasic" : "Master's degree with 2 to 6 years of post-graduation professional experience, PhD with no more than 3 years of post-graduation professional experience, National of a CERN Member or Associate Member State, Never had a CERN fellow or graduate contract before", "qualificationsPreferred" : "Experience with electromagnetics (EM) simulation tools", "remoteFriendly" : false, "workSiteFlexibility" : "Hybrid", "rawDescription" : "Join the CERN Experimental Physics Department and help develop next-generation detector technologies for future High Energy Physics experiments. As part of the High Speed Links programme, you will contribute to radiation-tolerant optical communication systems that combine custom ASICs, silicon photonics, optical modules, and FPGA platforms to enable reliable high-speed data transmission in extreme environments. We are seeking an Analogue/Custom IC Design Engineer to design and validate advanced communication ASICs and high-speed CMOS circuits for particle physics detectors. The role involves taking cutting-edge technologies from prototype development through to full system demonstrators. Your responsibilities * Study and define architectures for analogue and mixed-signal circuits that enable high-speed communication systems using silicon photonics. * Design and verify CMOS circuit blocks such as clock and data recovery (CDR) circuits, high speed clock distribution networks and high-speed analogue-to-digital converters (ADCs). * Perform laboratory testing, characterisation, and validation of circuits. * Carry out radiation qualification (single-event effects and total ionising dose) of manufactured devices. Your profile * A strong background in digital and analogue electronics, ideally in an IC design environment. * Familiarity with clock generation and distribution, including fundamentals of DLL, PLL, and CDR circuits. * The ability to solve engineering problems using a variety of analysis and simulation methods. * Hands-on experience in the design, testing and debugging of electronic circuits. * A strong team player who can also work independently. Skills * Design, simulation and layout of CMOS integrated circuits using Cadence Virtuoso. * Working knowledge of physical verification flows (DRC, LVS, PEX) using Siemens Calibre or Cadence PVS. * Knowledge of at least one of the following: optical receiver circuits, high data rate drivers (wireline, laser and/or external modulators), PLL and CDR design, TIA, ADC and DAC design, control systems. * Working knowledge of at least one programming, scripting, or data analysis language (e.g., Python, Bash, MATLAB). * Experience with electromagnetics (EM) simulation tools (e.g., Ansys HFSS, Simulia CST) is considered a plus. * Spoken and written English, with a commitment to learn French. Eligibility criteria: * You are a national of a [CERN Member or Associate Member State](https://home.cern/about/member-states). * You have a professional background in Electronics Engineering (or a related field) and have either: * a Master's degree with 2 to 6 years of post-graduation professional experience; * or a PhD with no more than 3 years of post-graduation professional experience. * You have never had a CERN fellow or graduate contract before. ## Additional Information Job closing date: 01.07.2026 at 23:59 CEST. Contract duration: 24 months, with a possible extension up to 36 months maximum. Working hours: 40 hours per week Job flexibility: Hybrid Target start date: 01-August-2026 This position involves: * Work during nights, Sundays and official holidays. * Work in Radiation Areas. * Work during nights, Sundays and official holidays, when required by the needs of the Organization. Job reference: EP-ESE-ME-2026-107-GRAP Field of work: Electrical or Electronics Engineering Benchmark job: 200050 - Electronics Engineer Global Benefits * A monthly stipend between 6372-7004 Swiss Francs per month (tax free) depending on your degree. * 30 days of paid leave per year plus 2 weeks annual closure. * Coverage by CERN’s comprehensive health insurance scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund. * Family, child and infant monthly allowances depending on your individual circumstances. * A relocation package (installation grant and travel expenses) depending on your individual circumstances. * Possibility to extend your contract up to 36 months. * On-the-job and formal training including language classes. Overview of CERN - Discover a world where the impossible is made possible! At CERN, the European Organization for Nuclear Research, we are pushing the frontiers of science and technology. Our groundbreaking work brings together not only physicists but also a diverse range of professionals from engineering, technical, scientific, and administrative fields. Together, we foster an environment where innovation and collaboration thrive. Every day, we face exciting new challenges and opportunities to contribute to cutting-edge research that shapes our understanding of the universe. We meet these challenges through the diverse perspectives within our teams, ensuring every contribution is valued and driving our shared sense of inclusion and purpose. Diversity is a core value of CERN since its foundation, and it remains central to our mission and continued success. If you are ready to be part of a dynamic, inclusive community pushing the boundaries of knowledge, CERN is the place where your curiosity and skills can thrive. Be part of our mission to uncover what lies at the heart of the universe! TAKE PART! More information about us, here:[careers.cern](https://careers.cern/)", "summaryDescription" : "Mixed-Signal IC Design Engineer at CERN. Skills: Mixed-Signal IC Design, Analogue IC Design, High-speed CMOS circuits, Radiation-tolerant optical communication. Study architectures for analogue circuits. Define architectures for mixed-signal circuits", "postedDate" : "2026-06-10T09:43:53.000", "createdAt" : "2026-06-12T00:58:25.399", "lastUpdated" : "2026-06-14T23:54:22.820", "ingestTimestamp" : "2026-06-12T00:58:25.399", "mongoId" : "6a2a4d4874d8ee00a05ecee2", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "100k-150k", "hasSalary" : false, "allSkills" : [ "Analogue circuit design", "Mixed-signal circuit design", "CMOS circuit design", "Laboratory testing", "Circuit characterisation", "Circuit validation", "Radiation qualification", "Single-event effects", "Total ionising dose", "Physical verification", "Electromagnetics simulation", "Work independently", "Mixed-Signal IC Design", "Analogue IC Design", "High-speed CMOS circuits", "Radiation-tolerant optical communication", "IC design", "Electronics engineering", "Particle physics detectors", "High speed links", "Detector technologies", "Communication systems", "High Energy Physics", "Radiation-tolerant systems", "Optical communication systems", "Silicon photonics", "ASICs", "FPGA platforms", "CMOS circuits", "DLL", "PLL", "CDR circuits", "Wireline drivers", "External modulators", "Cadence Virtuoso", "Siemens Calibre", "Cadence PVS" ], "skillCount" : 37, "jobCategory" : "research", "jobSubcategory" : "EP", "dataQualityScore" : 1.0, "_score" : 404.79193, "daysOld" : 4, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a305b00f292fd229cf58232", "title" : "Senior Signal Integrity Engineer", "company" : "Graphcore", "industry" : "Technology", "salary" : { "min" : 155000.0, "max" : 215000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior Signal Integrity Engineer in Austin, United States, adjusted for industry and company size." }, "location" : "Austin, Texas, United States", "locations" : [ "Austin", "Texas", "United States" ], "timestamp" : "2026-06-16T08:52:55.461", "fingerprint" : "92697eda6cd1f1db76185615b907de67f7127facde107fff59b8c6a1bcea114d", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/graphcore/jobs/8588019002", "externalId" : "8588019002", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Austin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.2711286,-97.7436995" } ], "locationText" : "Austin, Texas, United States", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, I2C, Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE, Python, MATLAB", "professionalSkills" : [ "Simulation correlation", "Technical communication", "Design methodology", "Channel performance", "Layout optimization", "Routing rules", "System design", "Schematic review", "Layout review", "Validation data review", "Measurement summaries", "Debug findings", "Technical recommendations" ], "hardSkillsList" : [ "Signal integrity analysis", "High-speed I/O optimization", "Low-speed I/O optimization", "Time-domain simulation", "Frequency-domain simulation", "Lab validation", "Measurement correlation", "S-parameters analysis", "Impedance profiles", "Eye diagrams", "Jitter analysis", "Timing margins", "Insertion loss", "Return loss", "Crosstalk analysis", "De-embedding", "Fixture design", "Lab automation", "Measurement methodology" ], "hardSkills" : [ { "name" : "Signal integrity analysis", "level" : "intermediate" }, { "name" : "High-speed I/O optimization", "level" : "intermediate" }, { "name" : "Low-speed I/O optimization", "level" : "intermediate" }, { "name" : "Time-domain simulation", "level" : "intermediate" }, { "name" : "Frequency-domain simulation", "level" : "intermediate" }, { "name" : "Lab validation", "level" : "intermediate" }, { "name" : "Measurement correlation", "level" : "intermediate" }, { "name" : "S-parameters analysis", "level" : "intermediate" }, { "name" : "Impedance profiles", "level" : "intermediate" }, { "name" : "Eye diagrams", "level" : "intermediate" }, { "name" : "Jitter analysis", "level" : "intermediate" }, { "name" : "Timing margins", "level" : "intermediate" }, { "name" : "Insertion loss", "level" : "intermediate" }, { "name" : "Return loss", "level" : "intermediate" }, { "name" : "Crosstalk analysis", "level" : "intermediate" }, { "name" : "De-embedding", "level" : "intermediate" }, { "name" : "Fixture design", "level" : "intermediate" }, { "name" : "Lab automation", "level" : "intermediate" }, { "name" : "Measurement methodology", "level" : "intermediate" } ], "majorSkills" : "Signal integrity, High-speed interfaces, SI/PI simulation, Lab validation", "majorSkillsList" : [ "Signal integrity", "High-speed interfaces", "SI/PI simulation", "Lab validation" ], "coreResponsibilities" : "Develop high-speed signaling solutions, Validate high-speed signaling solutions, Optimize high-speed signaling solutions, Perform end-to-end signal integrity analysis, Analyze high-speed I/O interfaces, Optimize high-speed I/O interfaces, Analyze low-speed I/O interfaces, Optimize low-speed I/O interfaces, Perform time-domain simulations, Perform frequency-domain simulations, Support lab validation, Correlate simulation results, Identify margin gaps, Debug issues, Improve design methodology, Optimize I/O channel performance, Guide board layout, Guide stack-ups, Guide routing rules, Guide system design, Review schematics, Review layouts, Review simulation results, Review validation data, Prepare validation reports, Communicate measurement summaries, Communicate debug findings, Communicate technical recommendations", "teamCollaboration" : "Cross-functional technical communication; Collaborate with silicon teams; Collaborate with package teams; Collaborate with board teams; Collaborate with connector teams; Collaborate with cable teams; Collaborate with system design teams; Work with interconnect vendors; Work with ODMs; Internal teams; Senior technical stakeholders", "domainKnowledge" : "High-speed digital systems; Blade architectures; Rack-level architectures; Compute platforms; Silicon design; Package design; Interconnect design; Board design; System design; I/O channel performance; Board layout; Stack-ups; Routing rules; Backplane hardware; Rack-level hardware; Hyperscale environments; Data center infrastructure; Cloud infrastructure; Compute hardware; Board-to-board interconnects; Cable interconnects; SI/PI performance; Thermal considerations; Mechanical considerations", "domainList" : [ "high-speed-digital-systems", "blade-architectures", "rack-level-architectures", "compute-platforms", "silicon-design", "package-design", "interconnect-design", "board-design", "system-design", "i-o-channel-performance", "board-layout", "stack-ups", "routing-rules", "backplane-hardware", "rack-level-hardware", "hyperscale-environments", "data-center-infrastructure", "cloud-infrastructure", "compute-hardware", "board-to-board-interconnects", "cable-interconnects", "si-pi-performance", "thermal-considerations", "mechanical-considerations" ], "domainSpecificKnowledge" : [ "High-speed digital systems", "Blade architectures", "Rack-level architectures", "Compute platforms", "Silicon design", "Package design", "Interconnect design", "Board design", "System design", "I/O channel performance", "Board layout", "Stack-ups", "Routing rules", "Backplane hardware", "Rack-level hardware", "Hyperscale environments", "Data center infrastructure", "Cloud infrastructure", "Compute hardware", "Board-to-board interconnects", "Cable interconnects", "SI/PI performance", "Thermal considerations", "Mechanical considerations" ], "toolProficiency" : [ "Ansys HFSS", "Keysight ADS", "Cadence Sigrity", "CST", "SPICE", "VNA", "TDR", "BERT", "Oscilloscopes", "Python", "MATLAB" ], "communicationSkills" : "Technical communication; Validation reports; Measurement summaries; Debug findings; Technical recommendations; Present technical findings", "documentationSkills" : "Validation reports", "problemSolvingSkills" : "Debug issues; Troubleshooting", "outcomesObjectives" : "Optimize I/O channel performance; Improve design methodology", "qualificationsBasic" : "Bachelor’s or Master’s degree, Experience in signal integrity, Hands-on measurement expertise, Experience measuring and analyzing S-parameters, Knowledge of high-speed interfaces, Experience with SI/PI simulation tools, Ability to correlate lab measurements, Communication skills", "qualificationsPreferred" : "Experience in hyperscale, Experience with blade architectures, Knowledge of thermal considerations, Experience with calibration, Experience using Python scripting", "workSiteFlexibility" : "Onsite", "rawDescription" : "About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design, with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication. Key Responsibilities End-to-end signal integrity analysis for blade- and rack-level system architectures. Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, I2C, etc. and related interconnects. Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE, or similar. Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes. Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology. Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance. Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions. Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware. Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Strong experience in signal integrity for high-speed digital systems. Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes. Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and crosstalk. Knowledge of high-speed interfaces such as PCIe Gen4/5/6, Ethernet, DDR, SerDes, and related I/O technologies. Experience with SI/PI simulation tools such as HFSS, ADS, Sigrity, CST, SPICE, or equivalent. Ability to correlate lab measurements with simulations and use data to guide design decisions. Strong communication skills, including the ability to produce clear validation reports, present technical findings, and work effectively across multi-functional engineering teams. Preferred Qualifications Experience in hyperscale, data center, cloud infrastructure, or advanced compute hardware environments. Experience with blade, backplane, board-to-board, cable, or rack-level interconnect architectures. Knowledge of thermal and mechanical considerations that impact SI/PI performance. Experience with calibration, de-embedding, fixture design, lab automation, or measurement methodology development. Experience using Python, MATLAB, or similar scripting languages for simulation automation, measurement automation, and data analysis. Tools / Technologies Measurement: VNA, TDR, BERT, high-speed oscilloscopes Simulation: Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE Interfaces: PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, high-speed interconnects Analysis: S-parameters, eye diagrams, jitter, timing margins, impedance control, crosstalk, insertion loss, return loss, de-embedding, measurement-to-simulation correlation Why Join Us This is an opportunity to work on complex, high-performance compute platforms while partnering with experienced technical leaders, ODMs, and interconnect vendors. You will play a key role in defining, measuring, validating, and optimizing next-generation system-level I/O performance. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.", "summaryDescription" : "Senior Signal Integrity Engineer at Graphcore. Skills: Signal integrity, High-speed interfaces, SI/PI simulation, Lab validation. Develop high-speed signaling solutions. Validate high-speed signaling solutions", "postedDate" : "2026-06-15T23:22:40.855", "createdAt" : "2026-06-15T23:22:40.855", "lastUpdated" : "2026-06-16T08:52:55.461", "ingestTimestamp" : "2026-06-15T23:22:40.855", "mongoId" : "6a305b00f292fd229cf58232", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 155000, "salaryAnnualMax" : 215000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Signal integrity analysis", "High-speed I/O optimization", "Low-speed I/O optimization", "Time-domain simulation", "Frequency-domain simulation", "Lab validation", "Measurement correlation", "S-parameters analysis", "Impedance profiles", "Eye diagrams", "Jitter analysis", "Timing margins", "Insertion loss", "Return loss", "Crosstalk analysis", "De-embedding", "Fixture design", "Lab automation", "Measurement methodology", "Signal integrity", "High-speed interfaces", "SI/PI simulation", "Simulation correlation", "Technical communication", "Design methodology", "Channel performance", "Layout optimization", "Routing rules", "System design", "Schematic review", "Layout review", "Validation data review", "Measurement summaries", "Debug findings", "Technical recommendations", "High-speed digital systems", "Blade architectures", "Rack-level architectures", "Compute platforms", "Silicon design", "Package design", "Interconnect design", "Board design", "I/O channel performance", "Board layout", "Stack-ups", "Backplane hardware", "Rack-level hardware", "Hyperscale environments", "Data center infrastructure", "Cloud infrastructure", "Compute hardware", "Board-to-board interconnects", "Cable interconnects", "SI/PI performance", "Thermal considerations", "Mechanical considerations", "Ansys HFSS", "Keysight ADS", "Cadence Sigrity", "CST", "SPICE", "VNA", "TDR", "BERT", "Oscilloscopes", "Python", "MATLAB" ], "skillCount" : 68, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "_score" : 401.51138, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a210e4874d8ee00a0af6b64", "title" : "Staff Signal and Power Integrity Engineer", "industry" : "Technology", "salary" : { "min" : 225000.0, "max" : 325000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Staff Signal and Power Integrity Engineer in Mountain View, United States, adjusted for lead seniority and technology industry." }, "location" : "[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US]", "locations" : [ "[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US]" ], "timestamp" : "2026-06-16T11:50:50.655", "fingerprint" : "8146cacc1d30c9e0df2966b3ea67ecfafd772d025f9bb897f7377e2b4e88d056", "source" : "google", "language" : "en", "externalId" : "115832583572333254", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Mountain View", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3893889,-122.0832101" } ], "locationText" : "Mountain View, California, United States", "experienceMinYears" : 8, "experienceMaxYears" : 15, "experienceLevel" : "Staff", "summaryDescription" : "Staff Signal and Power Integrity Engineer", "postedDate" : "2026-06-16T01:49:18.601", "createdAt" : "2026-06-16T01:49:18.601", "lastUpdated" : "2026-06-16T11:50:50.655", "ingestTimestamp" : "2026-06-16T01:49:18.601", "mongoId" : "6a210e4874d8ee00a0af6b64", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 225000, "salaryAnnualMax" : 325000, "salaryBand" : "200k+", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 0.5555556, "_score" : 399.38046, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "69e1043f2beec4dd3def244f", "title" : "Quantum Signal Train Engineer Internship", "company" : "Amazon Development Center U.S., Inc.", "industry" : "Hardware Development, Applied Science, Cloud Computing", "salary" : { "min" : 136000.0, "max" : 184000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Pasadena, California, USA", "locations" : [ "Pasadena, California, USA" ], "timestamp" : "2026-06-15T04:01:15.573", "fingerprint" : "502f54e028c3af7cb784f78ca2290f1a09a098cd51ea19e8a78e541d250ad2cd", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10387501/apply", "externalId" : "42d3d869-0ff8-47b5-9f6c-0854423b007d", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Pasadena", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "34.1476507,-118.1441550" } ], "locationText" : "Pasadena, California, United States", "employmentType" : "FULL_TIME", "technicalSkills" : "Analog design, Mixed-signal design, VHDL", "professionalSkills" : [ "Signal conditioning", "Control functions" ], "hardSkillsList" : [ "PCB level design", "Circuit design", "Mechanical design", "Statistical analysis", "RF/Microwave circuit theory" ], "softSkillsList" : [ "Innovation", "Curiosity" ], "hardSkills" : [ { "name" : "PCB level design", "level" : "intermediate" }, { "name" : "Circuit design", "level" : "intermediate" }, { "name" : "Mechanical design", "level" : "intermediate" }, { "name" : "Statistical analysis", "level" : "intermediate" }, { "name" : "RF/Microwave circuit theory", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Innovation" }, { "name" : "Curiosity" } ], "majorSkills" : "Analog design, Mixed-signal design", "majorSkillsList" : [ "Analog design", "Mixed-signal design" ], "coreResponsibilities" : "Design cryogenic and room temperature printed circuit board, Develop tests to validate hardware, Explore enabling control technologies", "teamCollaboration" : "Cross-functional team environment; Collaborate across diverse teams", "domainKnowledge" : "Quantum computing; Cryogenic temperatures; Op-amps; Biasing circuits; Filtering; Low-speed data converters; Microprocessors; Transmission lines; Impedance matching", "domainList" : [ "quantum-computing", "cryogenic-temperatures", "op-amps", "biasing-circuits", "filtering", "low-speed-data-converters", "microprocessors", "transmission-lines", "impedance-matching" ], "domainSpecificKnowledge" : [ "Quantum computing", "Cryogenic temperatures", "Op-amps", "Biasing circuits", "Filtering", "Low-speed data converters", "Microprocessors", "Transmission lines", "Impedance matching" ], "communicationSkills" : "Communicate effectively and respectfully", "continuousLearning" : "Ongoing events and learning experiences", "innovationCreativity" : "Passion for innovation", "specialRequirements" : "Work safely and cooperatively, Adhere to standards of excellence, Adhere to company policies, Exercise sound judgment, Effectively manage stress, Work safely and respectfully, Exhibit trustworthiness and professionalism, Safeguard business operations, Safeguard Company’s reputation", "qualificationsBasic" : "18 years of age or older, Work 40 hours/week minimum, Commit to 12 week internship maximum, Relocate to where internship is based, Bachelor's degree or above in Engineering, Technology, Science, Operations Research, Robotics, Mathematics or related fields, Hands-on lab skills, Use of oscilloscopes, Use of power supplies, Use of signal analyzers, Use of soldering equipment, Working knowledge of at least one computer aided engineering (CAE) circuit and mechanical design tool", "qualificationsPreferred" : "Designing experiments, Statistical analysis of results, Publications at top-tier peer-reviewed conferences or journals, Solid background in basic electrical circuit blocks, Previous experience with VHDL, Familiarity with RF/Microwave circuit theory", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "The Amazon Center for Quantum Computing in Pasadena, CA, is looking to hire an Applied Science intern who will specialize in hardware signal train design for quantum computing. Working alongside other scientists and engineers, you will design and validate hardware performing the control and readout functions for Amazon quantum processors, from room to cryogenic temperatures. Candidates must have a solid background in analog or mixed-signal design at the PCB level. Working effectively within a cross-functional team environment is critical. Key job responsibilities Our scientists and engineers collaborate across diverse teams and projects to offer state of the art, cost effective solutions for the control of Amazon quantum processor systems. You’ll bring a passion for innovation and collaboration to: Design cryogenic and room temperature printed circuit board based hardware, used for signal conditioning and control functions. Develop tests to validate hardware with both benchtop and cryogenic test setups with quantum devices. Explore enabling control technologies necessary for Amazon to produce commercially viable quantum computers. About the team Diverse Experiences Amazon values diverse experiences. Even if you do not meet all of the preferred qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying. Work/Life Balance We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud. Inclusive Team Culture Here at Amazon, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness. Mentorship and Career Growth We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional. Basic Qualifications: - Are 18 years of age or older - Work 40 hours/week minimum and commit to 12 week internship maximum - Can relocate to where the internship is based - Bachelor's degree or above in Engineering, Technology, Science, Operations Research, Robotics, Mathematics or related fields - Hands-on lab skills, including use of oscilloscopes, power supplies, signal analyzers, and soldering equipment. - Working knowledge of at least one computer aided engineering (CAE) circuit and mechanical design tool. Preferred Qualifications: - Experience in designing experiments and statistical analysis of results - Have publications at top-tier peer-reviewed conferences or journals - Solid background in the use of basic electrical circuit blocks such as op-amps, biasing circuits, filtering, low-speed data converters, and microprocessors. - Previous experience with VHDL. - Familiarity with RF/Microwave circuit theory, including transmission lines and impedance matching. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Pasadena - 136,000.00 - 184,000.00 USD annually", "summaryDescription" : "Quantum Signal Train Engineer Internship at Amazon Development Center U.S., Inc.. Skills: Analog design, Mixed-signal design. Design cryogenic and room temperature printed circuit board. Develop tests to validate hardware", "postedDate" : "2026-06-13T09:30:14.521", "createdAt" : "2026-06-13T09:30:14.521", "lastUpdated" : "2026-06-15T04:01:15.573", "ingestTimestamp" : "2026-06-13T09:30:14.521", "mongoId" : "69e1043f2beec4dd3def244f", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10387501/apply", "salaryAnnualMin" : 136000, "salaryAnnualMax" : 184000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "PCB level design", "Circuit design", "Mechanical design", "Statistical analysis", "RF/Microwave circuit theory", "Innovation", "Curiosity", "Analog design", "Mixed-signal design", "Signal conditioning", "Control functions", "Quantum computing", "Cryogenic temperatures", "Op-amps", "Biasing circuits", "Filtering", "Low-speed data converters", "Microprocessors", "Transmission lines", "Impedance matching" ], "skillCount" : 20, "jobCategory" : "other", "dataQualityScore" : 0.8888889, "_score" : 392.63086, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2c8c8374d8ee00a0975b5d", "title" : "Senior Signal Processing Engineer", "company" : "WHOOP", "industry" : "Sensor Intelligence", "salary" : { "min" : 150000.0, "max" : 215000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Boston, MA", "locations" : [ "Boston, MA" ], "timestamp" : "2026-06-16T06:54:43.709", "fingerprint" : "1dc53efc7a23be4a2afc3d8c4ff5361234abf473d8561d381e81f17e856c88be", "source" : "ashby", "language" : "en", "applyUrl" : "https://jobs.ashbyhq.com/whoop/07146ea6-838b-4b90-b645-4289985ebc6b/application", "externalId" : "07146ea6-838b-4b90-b645-4289985ebc6b", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Boston", "state" : "Massachusetts", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "42.3588336,-71.0578303" } ], "locationText" : "Boston, Massachusetts, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Signal processing, Embedded systems, Sensor fusion, Machine learning, Python, C++, MATLAB, ECG, IMU, Biometrics", "professionalSkills" : [ "Algorithm development", "Data analysis", "System design" ], "hardSkillsList" : [ "Algorithm implementation", "Data interpretation", "Biometric data analysis" ], "hardSkills" : [ { "name" : "Algorithm implementation", "level" : "intermediate" }, { "name" : "Data interpretation", "level" : "intermediate" }, { "name" : "Biometric data analysis", "level" : "intermediate" } ], "majorSkills" : "Signal processing, Machine learning, Embedded systems", "majorSkillsList" : [ "Signal processing", "Machine learning", "Embedded systems" ], "coreResponsibilities" : "Develop and implement signal processing algorithms, Develop and implement sensor fusion algorithms, Develop and implement machine learning algorithms, Process and analyze wearable sensor data, Optimize algorithms for embedded systems, Collaborate with hardware and software teams, Validate algorithms with real-world data, Contribute to system design and architecture", "teamCollaboration" : "Hardware teams; Software teams; Cross-functional teams", "domainKnowledge" : "Wearable sensors; Biometric data; ECG signal processing; IMU data analysis", "domainList" : [ "wearable-sensors", "biometric-data", "ecg-signal-processing", "imu-data-analysis" ], "domainSpecificKnowledge" : [ "Wearable sensors", "Biometric data", "ECG signal processing", "IMU data analysis" ], "toolProficiency" : [ "MATLAB", "Python", "C++" ], "communicationSkills" : "Technical communication", "documentationSkills" : "Algorithm documentation; Technical documentation", "problemSolvingSkills" : "Algorithm optimization; Data interpretation", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, 5+ years of experience in signal processing, Experience with embedded systems, Experience with sensor fusion algorithms, Experience with machine learning algorithms", "qualificationsPreferred" : "Master's degree or PhD, Experience with wearable sensor data, Experience with Python for data analysis, Experience with C++ for embedded systems", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "At WHOOP, we're on a mission to unlock human performance and healthspan. WHOOP empowers members to perform at a higher level through a deeper understanding of their bodies and daily lives. WHOOP is seeking a Senior Signal Processing Engineer to join the Sensor Intelligence Group (SIG), a cross-functional team collaborating across WHOOP Labs, Firmware, and Data Science. This role is central to developing next-generation sensor processing to enable foundational health features at WHOOP. You’ll develop the edge signal processing underpinning WHOOP physiological insights and coaching, ultimately delivering meaningful and personalized feedback to millions of members. RESPONSIBILITIES: - - Lead the design and development of signal processing for real-time, edge inference on consumer products - Own the full lifecycle: prototyping, validation, productionization, and continuous improvement - Evaluate commercial solutions; create demos and inform build/buy decisions - Collaborate cross-functionally with hardware, software, and product teams to bring algorithms to WHOOP members - Mentor junior engineers and contribute to a high-performance, research-to-production culture QUALIFICATIONS: - - B.S. in Electrical Engineering or related field, M.S. or PhD preferred - 5+ years of experience developing and deploying real-time sensor signal processing algorithms (e.g., physiological, audio, motion, etc.) - Demonstrated experience deploying algorithms to consumer product embedded platforms (e.g. fixed-point DSPs or MCUs) - Strong foundation in signal processing fundamentals (e.g., filtering, spectral analysis, time-frequency methods) - Experience with system-level design and optimization to maximize product battery life - Proficiency in Python or MATLAB for algorithm prototyping and with C/C++ for deployment to embedded product platforms - Excellent communication skills, including the ability to present technical results to a diverse audience BONUS QUALIFICATIONS: - - Experience developing hybrid DSP/ML systems, with a focus on signal pre-processing and/or feature extraction - Knowledge of embedded systems, RTOS, or firmware development - Deep understanding of sensor physics or sensor fusion techniques - Knowledge of microcontroller libraries for efficient signal processing (e.g. CMSIS-DSP or CMSIS-NN) This role is based in the WHOOP office located in Boston, MA. The successful candidate must be prepared to relocate if necessary to work out of the Boston, MA office. Interested in the role, but don’t meet every qualification? We encourage you to still apply! At WHOOP, we believe there is much more to a candidate than what is written on paper, and we value character as much as experience. As we continue to build a diverse and inclusive environment, we encourage anyone who is interested in this role to apply. WHOOP is an Equal Opportunity Employer and participates in E-verify https://www.e-verify.gov/ to determine employment eligibility. It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability. The WHOOP compensation philosophy is designed to attract, motivate, and retain exceptional talent by offering competitive base salaries, meaningful equity, and consistent pay practices that reflect our mission and core values. At WHOOP, we view total compensation as the combination of base salary, equity, and benefits, with equity serving as a key differentiator that aligns our employees with the long-term success of the company and allows every member of our corporate team to own part of WHOOP and share in the company’s long-term growth and success. The U.S. base salary range for this full-time position is $150,000 - $215,000 Salary ranges are determined by role, level, and location. Within each range, individual pay is based on factors such as job-related skills, experience, performance, and relevant education or training. In addition to the base salary, the successful candidate will also receive benefits and a generous equity package. These ranges may be modified in the future to reflect evolving market conditions and organizational needs. While most offers will typically fall toward the starting point of the range, total compensation will depend on the candidate’s specific qualifications, expertise, and alignment with the role’s requirements.", "summaryDescription" : "Senior Signal Processing Engineer at WHOOP. Skills: Signal processing, Machine learning, Embedded systems. Develop and implement signal processing algorithms. Develop and implement sensor fusion algorithms", "createdAt" : "2026-06-14T19:22:18.410", "lastUpdated" : "2026-06-16T06:54:43.709", "ingestTimestamp" : "2026-06-14T19:22:18.410", "mongoId" : "6a2c8c8374d8ee00a0975b5d", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 150000, "salaryAnnualMax" : 215000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Algorithm implementation", "Data interpretation", "Biometric data analysis", "Signal processing", "Machine learning", "Embedded systems", "Algorithm development", "Data analysis", "System design", "Wearable sensors", "Biometric data", "ECG signal processing", "IMU data analysis", "MATLAB", "Python", "C++" ], "skillCount" : 16, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "_score" : 390.62564, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2ccc1d74d8ee00a0a2681e", "title" : "Senior Layout Designer", "company" : "HDR", "industry" : "null", "salary" : { "min" : 115000.0, "max" : 165000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior Layout Designer in Omaha, adjusted for industry, company size, and seniority." }, "location" : "United States-Nebraska-Omaha", "locations" : [ "United States-Nebraska-Omaha" ], "timestamp" : "2026-06-16T02:30:47.400", "fingerprint" : "018e83e97087c0058bbe4ad3274e6e2605bd823efb2af31b1b7c04caa371cbd6", "source" : "taleo", "language" : "en", "applyUrl" : "https://hdr.taleo.net/careersection/ex/jobdetail.ftl?job=784033", "externalId" : "784033", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Omaha", "state" : "Nebraska", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "41.2587459,-95.9383758" } ], "locationText" : "Omaha, Nebraska, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Adobe InDesign, Microsoft Word", "professionalSkills" : [ "Document design", "Brand management", "Business development" ], "hardSkillsList" : [ "Layout design", "Document production", "File maintenance", "Document editing", "Brand guidelines" ], "hardSkills" : [ { "name" : "Layout design", "level" : "intermediate" }, { "name" : "Document production", "level" : "intermediate" }, { "name" : "File maintenance", "level" : "intermediate" }, { "name" : "Document editing", "level" : "intermediate" }, { "name" : "Brand guidelines", "level" : "intermediate" } ], "majorSkills" : "Layout design, Document production, Brand guidelines", "majorSkillsList" : [ "Layout design", "Document production", "Brand guidelines" ], "coreResponsibilities" : "Document layout for packages, Document layout for proposals, Design document templates, Design mood boards, Coordinate with graphic artists, Coordinate with layout artists, Coordinate with proposal managers, Coordinate with marketing coordinators, Assist staff with inquiries, Assist with file maintenance, Produce documents in Adobe InDesign, Produce documents in Microsoft Word, Assist in training coordinators, Train on InDesign, Edit documents, Research documents, Work with local office, Manage production of pursuits, Support growth initiatives, Create marketing collateral, Maintain inventory of pursuits, Run Brand Check of proposals, Present layout process, Conduct onboard training", "teamCollaboration" : "Team environment; Marketing staff; New employees; New team members", "toolProficiency" : [ "Adobe InDesign", "Microsoft Word" ], "documentationSkills" : "Document layout; Document templates; Marketing collateral", "specialRequirements" : "Ability to travel, Engage in person", "qualificationsBasic" : "5 years experience in architecture, 5 years experience in engineering, 5 years experience in construction industry", "qualificationsPreferred" : "Bachelor's degree business, Bachelor's degree marketing, Bachelor's degree journalism, Bachelor's degree management, Bachelor's degree graphics, Knowledge of CS standard, Ability to travel, Engage with others in person", "remoteFriendly" : false, "workSiteFlexibility" : "null", "rawDescription" : "At HDR, our employee-owners are fully engaged in creating a welcoming environment where each of us is valued and respected, a place where everyone is empowered to bring their authentic selves and novel ideas to work every day. As we foster a culture of inclusion throughout our company and within our communities, we constantly ask ourselves: What is our impact on the world? Watch Our Story: ' https://www.hdrinc.com/our-story' Each and every role throughout our organization makes a difference in our ability to change the world for the better. Read further to learn how you could help make great things possible not only in your community, but around the world. At HDR, our employee‑ownership model shapes everything we do, including how we support and care for our people. Our diverse service lines, including Water, Architecture, Building Engineering Services, Field Services, Power, Waste, Industrial, and Transportation reflect our commitment to shaping resilient, sustainable, and forward‑thinking communities around the world. Across these disciplines, our teams design and deliver solutions that safeguard public health, enhance quality of life, power innovation, and drive responsible growth. Whether advancing clean water, creating healing and learning environments, engineering next‑generation facilities, or building the infrastructure that moves people and energy, our work is rooted in technical excellence and a shared sense of purpose. Our employee‑owners collaborate across specialties, combining creativity, precision, and deep expertise to solve the most complex challenges facing our clients and communities. In the role of Senior Layout Designer, we'll count on you to: Document layout for medium to large qualifications packages and proposals, along with other documents on an as needed basis Design of document templates/mood boards Coordination with graphic artists, other layout artists, proposal managers, and marketing coordinators in a team-environment Assist department staff with layout and production inquiries and file maintenance Coordinate and/or produce documents in Adobe InDesign or Microsoft Word Assist in training other coordinators on In Design, as requested May include document editing, research, and working with the local office where the project is being managed Ability to produce visually compelling documents on brand as well as external teaming partner brands Manage production of multiple pursuits Support implementation of key growth initiatives related to pursuits Support creation of marketing collateral to support business development efforts Maintain inventory of branded pursuits used for inspiration and ideation for pursuit leaders and business development teams Able to run a Brand Check of proposals Able to present layout process to new employees (marketing staff) Able to conduct onboard training of new team members with Brand Guidelines and Basic InDesign Knowledge Lead initiatives Mentor new staff Preferred Qualifications Bachelor's degree business, marketing, journalism, management, graphics, or related field 5 years experience in the architecture, engineering, construction industry Knowledge of entire CS standard Ability to travel and engage with others in person", "summaryDescription" : "Senior Layout Designer at HDR. Skills: Layout design, Document production, Brand guidelines. Document layout for packages. Document layout for proposals", "createdAt" : "2026-06-14T19:11:59.508", "lastUpdated" : "2026-06-16T02:30:47.400", "ingestTimestamp" : "2026-06-14T19:11:59.508", "mongoId" : "6a2ccc1d74d8ee00a0a2681e", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 115000, "salaryAnnualMax" : 165000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Layout design", "Document production", "File maintenance", "Document editing", "Brand guidelines", "Document design", "Brand management", "Business development", "Adobe InDesign", "Microsoft Word" ], "skillCount" : 10, "jobCategory" : "product", "jobSubcategory" : "design", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "_score" : 383.14542, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Engineering", "llmIndustryConfidence" : 0.95 }, { "id" : "696082670937eae70e9c8a89", "title" : "Traffic Systems Specialist II or III (Signal Crew)", "company" : "TxDOT", "industry" : "Government", "salary" : { "min" : 45244.0, "max" : 81351.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "UST-Texas-Lufkin-Lufkin District Headquarters", "locations" : [ "UST-Texas-Lufkin-Lufkin District Headquarters", "Yearly", "Nonexempt,
Lufkin District Headquarters (11DISTHQ)
1805 N TIMBERLAND DRIVE
Lufkin, 75901

, Lufkin District Headquarters" ], "timestamp" : "2026-06-15T11:20:21.664", "fingerprint" : "84c83584e34cf32f6a73a114690ec1bcca105a2666a03403af4f596ed43d465d", "source" : "taleo", "language" : "en", "applyUrl" : "https://fa009.taleo.net/careersection/ex/jobdetail.ftl?job=42215", "externalId" : "42215", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Lufkin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "31.3386242,-94.7288558" } ], "locationText" : "Lufkin, Texas, United States", "employmentType" : "FULL_TIME", "softSkillsList" : [ "Problem-solving" ], "softSkills" : [ { "name" : "Problem-solving" } ], "majorSkills" : "Traffic systems, Signal operations", "majorSkillsList" : [ "Traffic systems", "Signal operations" ], "coreResponsibilities" : "Maintain traffic systems, Troubleshoot traffic systems, Repair traffic systems", "domainKnowledge" : "Intelligent transportation systems", "domainList" : [ "intelligent-transportation-systems" ], "domainSpecificKnowledge" : [ "Intelligent transportation systems" ], "continuousLearning" : "Career development; Training", "problemSolvingSkills" : "Troubleshooting", "outcomesObjectives" : "Keep roadways safe; Keep roadways efficient", "qualificationsBasic" : "Traffic Systems Specialist II or III", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Join the Team That Keeps Texas Moving! The TxDOT Lufkin District is hiring a Traffic Systems Specialist II or III based at our Lufkin District Headquarters. As a Traffic Systems Specialist, you’ll be part of a highly skilled and dedicated team responsible for maintaining, troubleshooting, and repairing cutting-edge traffic systems and technologies. From intelligent transportation systems to advanced signal operations, you’ll play a key role in keeping our roadways safe and efficient. This is more than just a job — it’s a chance to build a rewarding career with opportunities for growth, training, and advancement, all while making a real impact in your community. Why TxDOT? Competitive salary and benefits Career development and training Strong team culture and support Work that matters — every day If you're passionate about technology, problem-solving, and public service, we’d love to have you on our team! Salary Range: Traffic Systems Specialist II: (B19) $45,244 - $72,408 Traffic Systems Specialist III: (B20) $51,158 - $81,351 The Texas Department of Transportation reserves the sole right in determining the level of position based on the applicant's work experience, education, skill level, and all other appropriate factors, and based on business needs. 48,244.00 81,351.00", "summaryDescription" : "Traffic Systems Specialist II or III (Signal Crew) at TxDOT. Skills: Traffic systems, Signal operations. Maintain traffic systems. Troubleshoot traffic systems", "createdAt" : "2026-06-14T08:14:00.388", "lastUpdated" : "2026-06-15T11:20:21.664", "ingestTimestamp" : "2026-06-14T08:14:00.388", "mongoId" : "696082670937eae70e9c8a89", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 45244, "salaryAnnualMax" : 81351, "salaryBand" : "30k-50k", "hasSalary" : true, "allSkills" : [ "Problem-solving", "Traffic systems", "Signal operations", "Intelligent transportation systems" ], "skillCount" : 4, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Mid", "dataQualityScore" : 0.7777778, "_score" : 381.31784, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.92 }, { "id" : "6a219d4e74d8ee00a0c9906e", "title" : "Senior Layout Designer", "company" : "HDR", "salary" : { "min" : 115000.0, "max" : 165000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior Layout Designer in Omaha, adjusted for industry, company size, and seniority." }, "location" : "United States-Nebraska-Omaha", "locations" : [ "United States-Nebraska-Omaha" ], "timestamp" : "2026-06-16T01:20:52.788", "fingerprint" : "962e8b3b73329c4ea016d48f270b297ed566f81a4ce3122a4434c6a6afa9c211", "source" : "taleo", "language" : "en", "applyUrl" : "https://hdr.taleo.net/careersection/ex/jobdetail.ftl?job=784033", "externalId" : "784033", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Omaha", "state" : "Nebraska", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "41.2587459,-95.9383758" } ], "locationText" : "Omaha, Nebraska, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Microsoft Office, Outlook, Word, Excel, PowerPoint, Adobe Creative Cloud, InDesign", "professionalSkills" : [ "Negotiation skills" ], "hardSkillsList" : [ "Typing", "Spelling", "Proofreading" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Typing", "level" : "intermediate" }, { "name" : "Spelling", "level" : "intermediate" }, { "name" : "Proofreading", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "Layout design, Document production, Visual design", "majorSkillsList" : [ "Layout design", "Document production", "Visual design" ], "coreResponsibilities" : "Provide constructive feedback, Accept constructive criticism", "teamCollaboration" : "Teamwork", "projectManagementSkills" : [ "Project management" ], "domainKnowledge" : "Print production; Digital production", "domainList" : [ "print-production", "digital-production" ], "domainSpecificKnowledge" : [ "Print production", "Digital production" ], "toolProficiency" : [ "Microsoft Office", "Outlook", "Word", "Excel", "PowerPoint", "Adobe Creative Cloud", "InDesign" ], "communicationSkills" : "Oral communication; Written communication", "documentationSkills" : "High-quality documents", "qualificationsBasic" : "5 years relevant industry experience, Experience with technology for documents and layout, Excellent oral and written communication, Excellent typing, spelling and proofreading skills, Meticulous attention to visual design principles, fonts, and use of color, Exceptional attention to detail, Proven production of high-quality documents, Extensive knowledge of production processes, print and digital, Provide constructive feedback, Accept constructive criticism", "qualificationsPreferred" : "Demonstrated \"self-starter\", Customer service skills, Flexibility, Time management skills, Project management skills, Leadership skills, Multitasking skills, Teamwork skills, Completing projects with limited oversight", "remoteFriendly" : false, "rawDescription" : "Required Qualifications A minimum of 5 years relevant industry experience Experience with and interest in technology as it relates to documents and layout Excellent oral and written communication Excellent typing, spelling and proofreading skills Demonstrated \"self-starter\" Customer service, communication skills, flexibility, time management, project management, attention to detail, negotiation skills, leadership, multitasking and teamwork Meticulous attention to visual design principles, fonts, and use of color Exceptional attention to detail and proven production of high-quality documents Proficient in Microsoft Office applications, including Outlook, Word, Excel, and PowerPoint Proficient in Adobe Creative Cloud applications including InDesign History of completing projects with limited oversight Extensive knowledge of production processes, both print and digital Provide constructive feedback, and accept constructive criticism What We Believe HDR is our company. Together, we build on each other's life experiences and perspectives to make great things possible every day. This shapes our collaborative culture, encourages organizational trust and connects us closer to the clients and communities we serve. Our Commitment As employee owners, we all have a role in creating an inclusive environment where each of us is welcomed, valued, respected and empowered to bring our authentic selves to work every day. Our eight Employee Network Groups (Asian Pacific, Black, Hispanic/Latino(a), LGBTQ+, People with Disabilities, Veterans, Women, Young Professionals) help create a sense of belonging and foster a supportive environment where everyone is empowered to engage and contribute. Each group has an executive sponsor and is open to all employees. United States-Nebraska-Omaha", "summaryDescription" : "Senior Layout Designer at HDR. Skills: Layout design, Document production, Visual design. Provide constructive feedback. Accept constructive criticism", "createdAt" : "2026-06-14T19:42:51.141", "lastUpdated" : "2026-06-16T01:20:52.788", "ingestTimestamp" : "2026-06-14T19:42:51.141", "mongoId" : "6a219d4e74d8ee00a0c9906e", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 115000, "salaryAnnualMax" : 165000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Typing", "Spelling", "Proofreading", "Leadership", "Layout design", "Document production", "Visual design", "Negotiation skills", "Project management", "Print production", "Digital production", "Microsoft Office", "Outlook", "Word", "Excel", "PowerPoint", "Adobe Creative Cloud", "InDesign" ], "skillCount" : 18, "jobCategory" : "product", "jobSubcategory" : "design", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "_score" : 379.00644, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Engineering", "llmIndustryConfidence" : 0.95 }, { "id" : "6a2a688674d8ee00a0634769", "title" : "Principal Engineer- HIG HBM Layout", "company" : "Micron Technology", "industry" : "Technology", "salary" : { "min" : 6000000.0, "max" : 9000000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Principal Engineer in Hyderabad, India, adjusted for executive seniority and the technology industry." }, "location" : "Hyderabad - Phoenix Aquila, India", "locations" : [ "Hyderabad - Phoenix Aquila, India" ], "timestamp" : "2026-06-13T06:27:38.059", "fingerprint" : "3dd58325c471768690d3bbc23aa428a498ac9a58c68cefc88304fe8d93b1eb43", "source" : "workday", "language" : "en", "applyUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/Principal-Engineer--HIG-HBM-Layout_JR102906", "externalId" : "JR102906", "industryFunction" : { }, "locationPoint" : "17.38405,78.45636", "structuredLocations" : [ { "city" : "Hyderabad", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "17.3605890,78.4740613" } ], "locationText" : "Hyderabad, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 15, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Analog, Mixed-signal, Custom digital, HBM, Memory, ESD, EM/IR, CMOS", "professionalSkills" : [ "Layout execution", "Technical decisions", "Project planning", "Scheduling", "Task delegation", "Milestone tracking", "Product integration", "Team building", "Hiring", "Performance management" ], "hardSkillsList" : [ "Layout design", "Chip integration", "Performance estimation", "Power estimation", "Area estimation", "Layout verification", "DRC checks", "LVS checks", "Antenna checks", "Design reviews", "Automation adoption" ], "softSkillsList" : [ "Leadership", "Mentoring" ], "hardSkills" : [ { "name" : "Layout design", "level" : "intermediate" }, { "name" : "Chip integration", "level" : "intermediate" }, { "name" : "Performance estimation", "level" : "intermediate" }, { "name" : "Power estimation", "level" : "intermediate" }, { "name" : "Area estimation", "level" : "intermediate" }, { "name" : "Layout verification", "level" : "intermediate" }, { "name" : "DRC checks", "level" : "intermediate" }, { "name" : "LVS checks", "level" : "intermediate" }, { "name" : "Antenna checks", "level" : "intermediate" }, { "name" : "Design reviews", "level" : "intermediate" }, { "name" : "Automation adoption", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" }, { "name" : "Mentoring" } ], "majorSkills" : "HBM Layout, Analog Layout, Mixed-signal Layout, Full-chip integration", "majorSkillsList" : [ "HBM Layout", "Analog Layout", "Mixed-signal Layout", "Full-chip integration" ], "coreResponsibilities" : "Lead layout execution, Own full-chip technical decisions, Drive project planning, Drive project execution, Estimate area, Estimate time, Delegate tasks, Track milestones, Ensure timely delivery, Ensure quality delivery, Perform layout verification, Oversee layout verification, Ensure closure with documentation, Ensure closure with audits, Lead layout team, Mentor layout team, Guide junior engineers, Conduct design reviews, Enable capability development, Drive innovation improvements, Drive productivity improvements, Adopt AI/automation, Reduce layout effort, Improve turnaround time, Enhance quality, Collaborate with global teams, Ensure communication for alignment, Support customer needs, Support product integration needs, Align specifications, Clarify designs, Implement Micron solutions, Contribute to organizational growth, Contribute to leadership initiatives, Represent Micron in industry", "teamCollaboration" : "Global cross-functional teams; Design teams; Verification teams; IP teams; Packaging teams; Multi-functional teams; Multi-site teams", "projectManagementSkills" : [ "Project planning", "Scheduling", "Task delegation", "Milestone tracking" ], "domainKnowledge" : "Analog/mixed-signal IC layout; Advanced CMOS process; HBM products; Memory layout; IOs; PLLs; ADCs; DACs; LDOs; Bandgaps; Reference Generators; Charge Pumps; Current Mirrors; Comparators; Differential Amplifiers; Full-chip integration", "domainList" : [ "analog-mixed-signal-ic-layout", "advanced-cmos-process", "hbm-products", "memory-layout", "ios", "plls", "adcs", "dacs", "ldos", "bandgaps", "reference-generators", "charge-pumps", "current-mirrors", "comparators", "differential-amplifiers", "full-chip-integration" ], "domainSpecificKnowledge" : [ "Analog/mixed-signal IC layout", "Advanced CMOS process", "HBM products", "Memory layout", "IOs", "PLLs", "ADCs", "DACs", "LDOs", "Bandgaps", "Reference Generators", "Charge Pumps", "Current Mirrors", "Comparators", "Differential Amplifiers", "Full-chip integration" ], "toolProficiency" : [ "Cadence VLE/VXL", "Calibre DRC/LVS" ], "communicationSkills" : "Verbal communication; Written communication", "documentationSkills" : "Documentation; Audits", "innovationCreativity" : "AI/automation adoption", "specialRequirements" : "Work in multiple time zones", "qualificationsBasic" : "15+ years analog/custom layout, 4+ years developing teams, Experience leading multiple projects, Experience with Tape-out, Expertise in Cadence VLE/VXL, Expertise in Calibre DRC/LVS, Layout skills, Floor planning skills, Manual routing skills, Ability to build analog/mixed-signal layout team, Experience running Custom IC layout projects, BE or MTech in Electronic/VLSI Engineering", "qualificationsPreferred" : "Continuous development of layout team", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Role and Responsibilities** * **Lead end-to-end layout execution** of analog, mixed-signal, custom digital blocks and full-chip integration for HBM products. * **Own full-chip technical decisions** covering analog, digital, memory, ESD, EM/IR and ensure optimal performance, power, and area (PPA). * **Technical Expertise** : Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. * **Drive project planning and execution** , including area/time estimation, scheduling, task delegation, and milestone tracking across multiple concurrent programs. * **Ensure timely delivery with quality** , responsible for block-level and full-chip layouts meeting schedule commitments and quality expectations. * **Perform and oversee layout verification activities** including LVS, DRC, Antenna checks, and ensure closure with proper documentation and audits. * **Lead and mentor the layout team** , guiding junior engineers on sub-block execution, conducting design reviews, and enabling capability development. * **Drive innovation and productivity improvements** , including adoption of AI/automation to reduce layout effort, improve turnaround time, and enhance quality. * **Collaborate with global cross-functional teams** (Design, Verification, IP, Packaging) and ensure strong communication for project alignment and success. * **Support customer and product integration needs** , including specification alignment, design clarifications, and successful implementation of Micron solutions. * **Contribute to organizational growth and leadership initiatives** , including team building, hiring, performance management, and representing Micron in industry engagements. **Qualification/Requirements** * 15 + year experience in analog/custom layout in advanced CMOS process. * Minimum 4+ years developing teams and project experience. * Should have experience in leading multiple project and Tape-out. * Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must. * Must have strong skills in layout and floor planning skills and manual routing. * Strong ability to build, and continuously develop a premier analog/mixed-signal layout team * Experienced in running multiple Custom IC layout projects * Excellent verbal and written communication skills required. * Capable of working in a multi-functional, multi-site team environment in multiple time zones. **Education** BE or MTech in Electronic/VLSI Engineering. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. **About Micron Technology, Inc.** We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life _for all_. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact [hrsupport_india@micron.com](mailto:hrsupport_in@micron.com) Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "summaryDescription" : "Principal Engineer- HIG HBM Layout at Micron Technology. Skills: HBM Layout, Analog Layout, Mixed-signal Layout, Full-chip integration. Lead layout execution. Own full-chip technical decisions", "postedDate" : "2026-06-10T16:49:29.564", "createdAt" : "2026-06-11T16:49:29.495", "lastUpdated" : "2026-06-13T06:27:38.059", "ingestTimestamp" : "2026-06-11T16:49:29.495", "mongoId" : "6a2a688674d8ee00a0634769", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/Principal-Engineer--HIG-HBM-Layout_JR102906", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Layout design", "Chip integration", "Performance estimation", "Power estimation", "Area estimation", "Layout verification", "DRC checks", "LVS checks", "Antenna checks", "Design reviews", "Automation adoption", "Leadership", "Mentoring", "HBM Layout", "Analog Layout", "Mixed-signal Layout", "Full-chip integration", "Layout execution", "Technical decisions", "Project planning", "Scheduling", "Task delegation", "Milestone tracking", "Product integration", "Team building", "Hiring", "Performance management", "Analog/mixed-signal IC layout", "Advanced CMOS process", "HBM products", "Memory layout", "IOs", "PLLs", "ADCs", "DACs", "LDOs", "Bandgaps", "Reference Generators", "Charge Pumps", "Current Mirrors", "Comparators", "Differential Amplifiers", "Cadence VLE/VXL", "Calibre DRC/LVS" ], "skillCount" : 44, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 372.9241, "daysOld" : 2, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2a688774d8ee00a0634857", "title" : "Layout engineer", "company" : "Micron Technology", "industry" : "Technology", "salary" : { "min" : 1500000.0, "max" : 2500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Layout Engineer in Hyderabad, India, adjusted for the technology industry and company size." }, "location" : "Hyderabad - Phoenix Aquila, India", "locations" : [ "Hyderabad - Phoenix Aquila, India" ], "timestamp" : "2026-06-12T21:15:29.181", "fingerprint" : "aded3f03651fbc892431b80cead505c167989ea652bb03b286957bdbfd674ca5", "source" : "workday", "language" : "en", "applyUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/Layout-engineer_JR102255-1", "externalId" : "JR102255", "industryFunction" : { }, "locationPoint" : "17.38405,78.45636", "structuredLocations" : [ { "city" : "Hyderabad", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "17.3605890,78.4740613" } ], "locationText" : "Hyderabad, India", "employmentType" : "FULL_TIME", "minimumEducation" : "BE or MTech", "experienceMinYears" : 3, "experienceMaxYears" : 7, "experienceLevel" : "Mid", "technicalSkills" : "CMOS process, FinFET", "professionalSkills" : [ "Area estimation", "Time estimation", "Scheduling", "Project management" ], "hardSkillsList" : [ "Layout verification", "Chip level integration", "Analog layout build", "Physical verification" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Layout verification", "level" : "intermediate" }, { "name" : "Chip level integration", "level" : "intermediate" }, { "name" : "Analog layout build", "level" : "intermediate" }, { "name" : "Physical verification", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "Analog layout, Mixed-signal layout, Custom digital layout, Chip integration", "majorSkillsList" : [ "Analog layout", "Mixed-signal layout", "Custom digital layout", "Chip integration" ], "coreResponsibilities" : "Design critical analog blocks, Design mixed-signal blocks, Design custom digital blocks, Support full chip level integration, Perform layout verification, Perform quality check, Support documentation, Deliver block-level layouts, Demonstrate leadership skills, Plan project execution, Estimate project area, Estimate project time, Schedule project execution, Meet project scheduling, Contribute to project management, Communicate with Global engineering teams, Assure success of layout project, Explore AI-related tools, Use AI-related tools", "teamCollaboration" : "Global engineering teams", "projectManagementSkills" : [ "Planning", "Estimation", "Scheduling", "Execution" ], "domainKnowledge" : "Advanced CMOS process; Technology nodes; Analog Layout fundamentals; Memory designs", "domainList" : [ "advanced-cmos-process", "technology-nodes", "analog-layout-fundamentals", "memory-designs" ], "domainSpecificKnowledge" : [ "Advanced CMOS process", "Technology nodes", "Analog Layout fundamentals", "Memory designs" ], "toolProficiency" : [ "Cadence VLE/VXL", "Mentor Graphic Calibre" ], "communicationSkills" : "Verbal communication; Written communication", "documentationSkills" : "Support documentation", "problemSolvingSkills" : "Problem-solving", "outcomesObjectives" : "On-time delivery of layouts", "qualificationsBasic" : "3 to 7 years experience, Cadence VLE/VXL expertise, Mentor Graphic Calibre DRC/LVS expertise, Hands on experience creating layout of critical blocks, Good understanding of Analog Layout fundamentals, Understanding layout effects on circuit, Ability to understand build constraints, Ability to understand build hierarchy, Excellent problem-solving skills in physical verification", "qualificationsPreferred" : "Multiple Tape out support experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. * Role and Responsibilities * Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. * Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. * Responsible for on-time delivery of block-level layouts with acceptable quality. * Demonstrate leadership skills in planning, area/time estimation, scheduling, and execution to meet project scheduling multiple project environment. * Contribute to effective project-management. * Effectively communicating with Global engineering teams to assure the success of layout project. * **Qualification/Requirements** * **3 to 7 years ' **experience in analog/custom layout build in advanced CMOS process, in various technology nodes (Planar, FinFET ) * Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. * Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., * Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.) * Understanding layout effects on the circuit such as speed, capacitance, power and area etc. * Ability to understand build constraints and implement high-quality layouts * Ability to understand build hierarchy and different architectures for Memory designs. * Excellent problem-solving skills in physical verification of custom layout. * Multiple Tape out support experience will be an added advantage. * Excellent verbal and written communication skills * Should be proactive in exploring and using AI-related tools in day-to-day tasks. * Education * BE or MTech in Electronic/VLSI Engineering * All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. **About Micron Technology, Inc.** We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life _for all_. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact [hrsupport_india@micron.com](mailto:hrsupport_in@micron.com) Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "summaryDescription" : "Layout engineer at Micron Technology. Skills: Analog layout, Mixed-signal layout, Custom digital layout, Chip integration. Design critical analog blocks. Design mixed-signal blocks", "postedDate" : "2026-06-09T16:12:55.681", "createdAt" : "2026-06-11T16:12:55.488", "lastUpdated" : "2026-06-12T21:15:29.181", "ingestTimestamp" : "2026-06-11T16:12:55.488", "mongoId" : "6a2a688774d8ee00a0634857", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/Layout-engineer_JR102255-1", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Layout verification", "Chip level integration", "Analog layout build", "Physical verification", "Leadership", "Analog layout", "Mixed-signal layout", "Custom digital layout", "Chip integration", "Area estimation", "Time estimation", "Scheduling", "Project management", "Planning", "Estimation", "Execution", "Advanced CMOS process", "Technology nodes", "Analog Layout fundamentals", "Memory designs", "Cadence VLE/VXL", "Mentor Graphic Calibre" ], "skillCount" : 22, "jobCategory" : "engineering", "seniorityLevel" : "mid", "dataQualityScore" : 1.0, "_score" : 365.55347, "daysOld" : 3, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2b115774d8ee00a0766954", "title" : "Custom Layout Engineer", "company" : "Weekday AI", "salary" : { "min" : 200000.0, "max" : 1800000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : false }, "location" : "Hyderabad, Telangana, India", "locations" : [ "Hyderabad, Telangana, India" ], "timestamp" : "2026-06-14T23:22:35.057", "fingerprint" : "677dde81c2c6a9488ac31067c7a17bb90bdf780852f94efde395a4dea294e514", "source" : "workable", "language" : "en", "applyUrl" : "https://apply.workable.com/j/B361034655/apply", "externalId" : "B361034655", "locationPoint" : "17.38405,78.45636", "structuredLocations" : [ { "city" : "Hyderabad", "state" : "Telangana", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "17.3605890,78.4740613" } ], "locationText" : "Hyderabad, Telangana, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 4, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Analog design, Mixed-signal design, Custom digital circuits", "professionalSkills" : [ "Physical design", "Layout optimization", "Semiconductor design" ], "hardSkillsList" : [ "Layout design", "Floorplanning", "Placement", "Routing", "Matching", "Shielding", "Optimization", "Parasitic-aware layout", "Extraction", "Post-layout verification" ], "hardSkills" : [ { "name" : "Layout design", "level" : "intermediate" }, { "name" : "Floorplanning", "level" : "intermediate" }, { "name" : "Placement", "level" : "intermediate" }, { "name" : "Routing", "level" : "intermediate" }, { "name" : "Matching", "level" : "intermediate" }, { "name" : "Shielding", "level" : "intermediate" }, { "name" : "Optimization", "level" : "intermediate" }, { "name" : "Parasitic-aware layout", "level" : "intermediate" }, { "name" : "Extraction", "level" : "intermediate" }, { "name" : "Post-layout verification", "level" : "intermediate" } ], "majorSkills" : "Analog layout design, Mixed-signal layout design, Cadence Virtuoso", "majorSkillsList" : [ "Analog layout design", "Mixed-signal layout design", "Cadence Virtuoso" ], "coreResponsibilities" : "Develop custom analog layouts, Implement custom analog layouts, Develop mixed-signal layouts, Implement mixed-signal layouts, Create transistor-level layouts, Perform floorplanning, Perform device placement, Perform routing, Perform matching, Perform shielding, Optimize layouts, Ensure layout compliance, Conduct DRC, Conduct LVS, Resolve DRC issues, Resolve LVS issues, Resolve physical verification issues, Work with schematic designers, Implement layout solutions, Optimize layouts for area, Optimize layouts for performance, Optimize layouts for yield, Optimize layouts for power, Optimize layouts for manufacturability, Execute parasitic-aware layout techniques, Support extraction activities, Support post-layout verification, Collaborate with design teams, Collaborate with verification teams, Collaborate with technology teams, Maintain design documentation, Maintain layout methodologies, Maintain best practices, Support tape-out activities, Contribute to process improvements, Review layouts, Provide technical feedback, Ensure quality standards adherence", "teamCollaboration" : "Cross-functional teams; Design teams; Verification teams; Technology teams", "domainKnowledge" : "Analog layout concepts; Semiconductor device physics; Fabrication processes; Advanced process technologies", "domainList" : [ "analog-layout-concepts", "semiconductor-device-physics", "fabrication-processes", "advanced-process-technologies" ], "domainSpecificKnowledge" : [ "Analog layout concepts", "Semiconductor device physics", "Fabrication processes", "Advanced process technologies" ], "toolProficiency" : [ "Cadence Virtuoso", "VXL" ], "documentationSkills" : "Design documentation", "problemSolvingSkills" : "Analytical skills; Problem-solving skills", "qualificationsBasic" : "4+ years analog layout design, Cadence Virtuoso proficiency, DRC knowledge, LVS knowledge, Physical verification knowledge", "qualificationsPreferred" : "VXL familiarity, Layout verification tools familiarity, Debugging physical design issues familiarity", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "**This role is for one of the Weekday's clients** **Salary range: Rs 200000 - Rs 1800000 (ie INR 2-18 LPA)** Experience: 4+ yrs Location: Hyderabad Job Type: full-time We are looking for a highly skilled **Custom Layout Engineer** with strong expertise in **analog and mixed-signal layout design** to contribute to the development of advanced semiconductor products. In this role, you will be responsible for creating high-quality custom layouts for complex analog, mixed-signal, and custom digital circuits while ensuring compliance with design specifications, process requirements, and quality standards. You will work closely with circuit designers, verification engineers, and cross-functional teams to transform schematics into optimized physical layouts that meet performance, area, power, reliability, and manufacturability goals. This position is ideal for professionals who are passionate about physical design, layout optimization, and solving challenging semiconductor design problems in a fast-paced engineering environment. The role offers the opportunity to work on cutting-edge technologies, contribute to full-chip and block-level layout development, and play a critical role in delivering high-performance silicon products. **Requirements** ### Key Responsibilities * Develop and implement custom analog and mixed-signal layouts using **Cadence Virtuoso**. * Create transistor-level layouts for analog, RF, memory, and custom digital circuit blocks. * Perform floorplanning, device placement, routing, matching, shielding, and layout optimization to meet performance targets. * Ensure layouts comply with foundry design rules, process requirements, and reliability guidelines. * Conduct and resolve **DRC (Design Rule Check)** , **LVS (Layout Versus Schematic)** , and physical verification issues. * Work with schematic designers to understand circuit requirements and implement efficient layout solutions. * Optimize layouts for area, performance, yield, power consumption, and manufacturability. * Execute parasitic-aware layout techniques and support extraction and post-layout verification activities. * Collaborate with design, verification, and technology teams throughout the design lifecycle. * Maintain design documentation, layout methodologies, and best practices. * Support tape-out activities and contribute to continuous process improvements. * Review layouts, provide technical feedback, and ensure adherence to quality standards. ### What Makes You a Great Fit * 4+ years of hands-on experience in **custom analog layout design**. * Strong proficiency in **Cadence Virtuoso** and custom layout methodologies. * Solid understanding of analog layout concepts including matching, symmetry, common-centroid structures, shielding, guard rings, and parasitic minimization. * Experience working with advanced process technologies and semiconductor design flows. * Strong knowledge of **DRC** , **LVS** , and physical verification methodologies. * Familiarity with **VXL** , layout verification tools, and debugging physical design issues. * Good understanding of semiconductor device physics and fabrication processes. * Ability to interpret schematics and convert them into optimized physical layouts. * Experience working on analog, mixed-signal, RF, memory, or custom digital blocks. * Strong analytical and problem-solving skills with attention to detail. * Ability to work independently while collaborating effectively with multidisciplinary engineering teams. * Excellent communication skills and a commitment to delivering high-quality layout solutions within project timelines.", "summaryDescription" : "Custom Layout Engineer at Weekday AI. Skills: Analog layout design, Mixed-signal layout design, Cadence Virtuoso. Develop custom analog layouts. Implement custom analog layouts", "postedDate" : "2026-06-09T00:00:00.000", "createdAt" : "2026-06-12T05:09:01.110", "lastUpdated" : "2026-06-14T23:22:35.057", "ingestTimestamp" : "2026-06-12T05:09:01.110", "mongoId" : "6a2b115774d8ee00a0766954", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://apply.workable.com/j/B361034655", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Layout design", "Floorplanning", "Placement", "Routing", "Matching", "Shielding", "Optimization", "Parasitic-aware layout", "Extraction", "Post-layout verification", "Analog layout design", "Mixed-signal layout design", "Cadence Virtuoso", "Physical design", "Layout optimization", "Semiconductor design", "Analog layout concepts", "Semiconductor device physics", "Fabrication processes", "Advanced process technologies", "VXL" ], "skillCount" : 21, "seniorityLevel" : "mid", "dataQualityScore" : 1.0, "_score" : 357.5556, "daysOld" : 5, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a210e6a74d8ee00a0af766d", "title" : "Hardware Validation Manager for Networking and Signal Integrity", "industry" : "Technology", "salary" : { "min" : 175000.0, "max" : 250000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Hardware Validation Manager in Sunnyvale, United States, adjusted for manager seniority and the technology industry." }, "location" : "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]", "locations" : [ "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]" ], "timestamp" : "2026-06-16T10:57:24.927", "fingerprint" : "496a33a245bb2388dedd9ef64a7ae28bea9bcd442df0e25cf529f926b1be1356", "source" : "google", "language" : "en", "externalId" : "76685859440468678", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "experienceLevel" : "Manager", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "summaryDescription" : "Hardware Validation Manager for Networking and Signal Integrity", "postedDate" : "2026-06-16T01:48:00.546", "createdAt" : "2026-06-16T01:48:00.546", "lastUpdated" : "2026-06-16T10:57:24.927", "ingestTimestamp" : "2026-06-16T01:48:00.546", "mongoId" : "6a210e6a74d8ee00a0af766d", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 175000, "salaryAnnualMax" : 250000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Manager", "dataQualityScore" : 0.5555556, "_score" : 356.7168, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "69dde4492beec4dd3d9a32de", "title" : "Traffic Systems Technician or II- Signal Shop", "company" : "TxDOT Beaumont District", "industry" : "Government", "salary" : { "min" : 40918.0, "max" : 71055.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "UST-Texas-Beaumont-Beaumont District Headquarters", "locations" : [ "UST-Texas-Beaumont-Beaumont District Headquarters", "Yearly", "Nonexempt,
Beaumont District Headquarters (20DISTHQ)
8350 EASTEX FREEWAY
Beaumont, 77708

, Beaumont District Headquarters" ], "certifications" : [ "CDL training" ], "timestamp" : "2026-06-15T10:36:55.457", "fingerprint" : "89be3e517c4c76964826ed1aaef7adda3a390cee9b9039a7457e6ad15193d8a3", "source" : "taleo", "language" : "en", "applyUrl" : "https://fa009.taleo.net/careersection/ex/jobdetail.ftl?job=43399", "externalId" : "43399", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Beaumont", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.0829344,-94.0984277" } ], "locationText" : "Beaumont, Texas, United States", "employmentType" : "FULL_TIME", "coreResponsibilities" : "Maintain traffic systems, Troubleshoot traffic systems, Repair traffic systems, Maintain traffic technologies, Troubleshoot traffic technologies, Repair traffic technologies", "domainKnowledge" : "Traffic systems", "domainList" : [ "traffic-systems" ], "domainSpecificKnowledge" : [ "Traffic systems" ], "problemSolvingSkills" : "Troubleshooting", "specialRequirements" : "Work outdoors", "qualificationsBasic" : "Electronic systems troubleshooting, Electrical systems troubleshooting", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Do you enjoy working outdoors, away from a desk during your workday? Are you a problem solver who enjoys troubleshooting electronic and electrical systems? If so, we want to hear from you! The TxDOT Beaumont District is looking for a Traffic Systems Technician I or II based in our District Headquarters location. As a Traffic Systems Tech, you will be part of an elite team of technicians that maintain, troubleshoot, and repair the latest traffic systems and technologies, while building an exciting career. We offer company-sponsored CDL training with $0 upfront monetary commitment. Work Location: 8350 Eastex Freeway, Beaumont TX, 77708 Salary Grade: Traffic Systems Technician I: A16; $40,918 - $61,130/yearly Traffic Systems Technician II: A18; $45,521 - $71,055/yearly The Texas Department of Transportation reserves the sole right in determining the level of position based on the applicants' work experience, education, skill level and all other appropriate factors, and based on business needs 40,918.00 71,055.00", "summaryDescription" : "Traffic Systems Technician or II- Signal Shop at TxDOT Beaumont District. Maintain traffic systems. Troubleshoot traffic systems", "createdAt" : "2026-06-14T02:04:37.643", "lastUpdated" : "2026-06-15T10:36:55.457", "ingestTimestamp" : "2026-06-14T02:04:37.643", "mongoId" : "69dde4492beec4dd3d9a32de", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 40918, "salaryAnnualMax" : 71055, "salaryBand" : "30k-50k", "hasSalary" : true, "allSkills" : [ "Traffic systems", "CDL training" ], "skillCount" : 2, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Mid", "dataQualityScore" : 0.7777778, "_score" : 351.16968, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.92 }, { "id" : "69dde4492beec4dd3d9a32dd", "title" : "ITS Analyst I- Traffic Signal Crew", "company" : "TxDOT", "industry" : "Government", "salary" : { "min" : 54278.0, "max" : 87046.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "UST-Texas-Beaumont-Beaumont District Headquarters", "locations" : [ "UST-Texas-Beaumont-Beaumont District Headquarters", "Yearly", "Exempt,
Beaumont District Headquarters (20DISTHQ)
8350 EASTEX FREEWAY
Beaumont, 77708

, Beaumont District Headquarters" ], "timestamp" : "2026-06-16T00:57:09.400", "fingerprint" : "2512cf652bdc1de15e33b33959da3ebc5b89f9efebcfed09bd852df7dc1e4625", "source" : "taleo", "language" : "en", "applyUrl" : "https://fa009.taleo.net/careersection/ex/jobdetail.ftl?job=43722", "externalId" : "43722", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Beaumont", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.0829344,-94.0984277" } ], "locationText" : "Beaumont, Texas, United States", "technicalSkills" : "ITS", "professionalSkills" : [ "System design", "Traffic flow" ], "hardSkillsList" : [ "Traffic signal systems" ], "hardSkills" : [ { "name" : "Traffic signal systems", "level" : "intermediate" } ], "majorSkills" : "Intelligent Transportation Systems, Traffic signal design", "majorSkillsList" : [ "Intelligent Transportation Systems", "Traffic signal design" ], "coreResponsibilities" : "Design automated systems, Refine automated systems, Implement automated systems, Steward technology for Operations Center", "teamCollaboration" : "Public partners; Private partners", "domainKnowledge" : "Intelligent Transportation Systems", "domainList" : [ "intelligent-transportation-systems" ], "domainSpecificKnowledge" : [ "Intelligent Transportation Systems" ], "outcomesObjectives" : "Keep traffic flowing; Keep communities moving", "qualificationsBasic" : "5+ years ITS experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "TxDOT's Beaumont District is looking for an ITS Analyst I to join us in our Traffic Signal Department. If you’re driven by the challenge of shaping smarter, safer, and more connected transportation networks, this role puts you at the center of that mission. As a key contributor to our Intelligent Transportation Systems (ITS) initiatives, you’ll design, refine, and implement the automated systems that keep traffic flowing and communities moving. You’ll work independently on meaningful technical projects, collaborate with public and private partners, and help steward the technology that powers our Intelligent Transportation Operations Center. It’s a chance to turn complex data and infrastructure into real-world impact. Salary Plan/Grade: ITS Analyst I (B21): $54,278 - $87,046/yearly Physical Work Location: 8350 Eastex Freeway, Beaumont TX, 77708 54,278.00 87,046.00", "summaryDescription" : "ITS Analyst I- Traffic Signal Crew at TxDOT. Skills: Intelligent Transportation Systems, Traffic signal design. Design automated systems. Refine automated systems", "createdAt" : "2026-06-14T20:49:32.015", "lastUpdated" : "2026-06-16T00:57:09.400", "ingestTimestamp" : "2026-06-14T20:49:32.015", "mongoId" : "69dde4492beec4dd3d9a32dd", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 54278, "salaryAnnualMax" : 87046, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "Traffic signal systems", "Intelligent Transportation Systems", "Traffic signal design", "System design", "Traffic flow" ], "skillCount" : 5, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Entry", "dataQualityScore" : 0.6666667, "_score" : 346.58075, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.92 }, { "id" : "68e0a7e4ce260f92cbf8eba8", "title" : "Hardware Development Engineer/Signal Integrity", "company" : "Amazon Data Services, Inc.", "industry" : "Hardware Development, Cloud Hardware Development, Cloud Computing", "salary" : { "min" : 125700.0, "max" : 219900.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Cupertino, California, USA", "locations" : [ "Cupertino, California, USA" ], "timestamp" : "2026-06-15T07:47:09.867", "fingerprint" : "a61f2cba2532713f06564ee837f3e74248b4d0fa9b73f73b0260eadf965140dc", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3099353/apply", "externalId" : "9e4cde41-1d65-4cd2-8414-8a3fb61199e6", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Cupertino", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3228934,-122.0322895" } ], "locationText" : "Cupertino, California, United States", "employmentType" : "FULL_TIME", "technicalSkills" : "Digital circuit design, Signal integrity", "professionalSkills" : [ "System design", "Architecture development" ], "hardSkillsList" : [ "Signal integrity analysis", "PCB design techniques" ], "hardSkills" : [ { "name" : "Signal integrity analysis", "level" : "intermediate" }, { "name" : "PCB design techniques", "level" : "intermediate" } ], "majorSkills" : "Circuit board design, Signal integrity", "majorSkillsList" : [ "Circuit board design", "Signal integrity" ], "coreResponsibilities" : "Own next-generation server components, Focus on digital circuit board design, Focus on signal integrity, Architecture and development of high-speed PCB designs, Optimize high-speed interfaces, Ensure robust system performance, Design, develop, validate, and launch at large scale, Hardware design, Build systems that validate hardware quality, Monitor hardware reliability, Improve hardware reliability", "teamCollaboration" : "Interdisciplinary team of engineers", "domainKnowledge" : "Cloud computing infrastructure; Server components", "domainList" : [ "cloud-computing-infrastructure", "server-components" ], "domainSpecificKnowledge" : [ "Cloud computing infrastructure", "Server components" ], "innovationCreativity" : "System innovation", "problemSolvingSkills" : "Solve complex problems", "qualificationsBasic" : "High-speed PCB designs, Digital circuit board design, Signal integrity analysis", "qualificationsPreferred" : "Experience with server components, Experience with motherboards, Experience with graphics, Experience with accelerators, Experience with programmable hardware", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "AWS Infrastructure Services owns the design, planning, delivery, and operation of all AWS global infrastructure. In other words, we’re the people who keep the cloud running. We support all AWS data centers and all of the servers, storage, networking, power, and cooling equipment that ensure our customers have continual access to the innovation they rely on. We work on the most challenging problems, with thousands of variables impacting the supply chain — and we’re looking for talented people who want to build. You’ll join a diverse team of software, hardware, and network engineers, supply chain specialists, security experts, operations managers, and other vital roles. You’ll collaborate with people across AWS to help us deliver the highest standards for safety and security while providing seemingly infinite capacity at the lowest possible cost for our customers. And you’ll experience an inclusive culture that welcomes bold ideas and empowers you to own them to completion. Do you enjoy solving complex problems and driving influential changes? Are you curious about the systems used to run the largest cloud computing infrastructures in the world? Do you thrive in a fast paced and ever-changing environment? If you answered YES to these questions, then our team is looking for you! The AWS Board Core Design & Services team drives system innovation in the servers used by all of Amazon Web Services, including EC2, S3 and CloudFront. Our engineers solve the hardest problems that fuse software, hardware, and the cloud. We take big bets on new concepts, enabling AWS services to continue to revolutionize the industry. What you will do: As a member of the AWS Board Core Design & Services team, you will own next-generation server components with a strong focus on digital circuit board design and signal integrity. You will have demonstrated results in the architecture and development of high-speed, complex PCB designs for server components, including motherboards, graphics, accelerators, and programmable hardware. Your expertise in signal integrity analysis and advanced PCB design techniques will be crucial for optimizing high-speed interfaces and ensuring robust system performance. You will interact with an interdisciplinary team of engineers to design, develop, validate, and launch at large scale. Why it matters: Public cloud IT services represent the majority of growth in the overall IT services market and will continue to do so for several years to come. The scale of AWS creates a unique opportunity for differentiated hardware that will directly benefit customers. Why you will love it: You will build next-generation hardware that powers the cloud. You will deliver improvements for our customers and have a direct impact on our bottom line. You will be part of a growing, fast paced, and fun team. You will have ownership for the implementation of your work. Key job responsibilities As a member of the AWS Board Core Design & Services team, you will own next-generation server components with a strong focus on digital circuit board design and signal integrity. You will have demonstrated results in the architecture and development of high-speed, complex PCB designs for server components, including motherboards, graphics, accelerators, and programmable hardware. Your expertise in signal integrity analysis and advanced PCB design techniques will be crucial for optimizing high-speed interfaces and ensuring robust system performance. You will interact with an interdisciplinary team of engineers to design, develop, validate, and launch at large scale. A day in the life Hardware engineers within AWS Board Core Design & Services team could be working in a variety of areas, few examples would be: hardware design and development; building the systems that validate hardware quality in manufacturing; monitoring and improving hardware reliability in data centers and platform. We cover everything from low level hardware to embedded software and systems that operate and monitor it. There is no blueprint for how to do what we do, which encourages our engineers to identify and develop simple solutions to complex problems. We encourage durable solutions that look around corners while taking into consideration our customer needs from a cost, performance, and reliability perspective. About the team Why AWS Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses. Utility Computing (UC) AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. Inclusive Team Culture Here at AWS, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness. Work/Life Balance We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud. Mentorship and Career Growth We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional. Diverse Experiences Amazon values diverse experiences. Even if you do not meet all of the preferred qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying. Basic Qualifications: - BS Electrical/Computer Engineering (or equivalent experience) - 7+ years of experience in embedded ARM, FPGA, and CPLD applications - 7+ years of hands-on experience with high-speed PCB design, including signal integrity analysis and optimization - Strong proficiency in PCB design tools (Allegro, CAM350, or equivalent) with demonstrated ability to perform detailed PCB reviews - 7+ years of experience in high-speed interface design (DDR, PCIe, USB, etc.) with emphasis on signal integrity - Proven track record in impedance control, stack-up design, and power integrity optimization - 7+ years of experience in board root cause analysis and resolution, particularly focusing on signal integrity issues - Experience with flash, I2C, SPI, UART, and ethernet interfaces Preferred Qualifications: - Master's degree in electrical engineering, computer engineering, or equivalent - 10+ years of experience in server design for cloud or enterprise applications - Advanced expertise in: - High-speed PCB design and signal integrity analysis - Complex motherboard and peripheral component design - Multi-layer PCB stack-up optimization - Advanced routing techniques for high-speed interfaces - EMI/EMC compliance and design considerations - Power delivery network (PDN) design and analysis - Proficiency with signal integrity simulation tools (Ansys, Cadence Sigrity, or similar) - Experience in designing for reuse across multiple products - Advanced knowledge of server technologies including: - Signal integrity optimization techniques - Power optimization - Thermal considerations - Mechanical constraints in PCB design - BIOS and BMC integration - High-speed networking interfaces - Experience with impedance-controlled board design and manufacturing processes - Strong expertise in component selection considering signal integrity requirements - Experience in design for large scale applications with emphasis on signal integrity - Experience working with interdisciplinary teams to execute complex PCB designs from concept to production Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $125,700/year in our lowest geographic market up to $219,900/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits . This position will remain posted until filled. Applicants should apply via our internal or external career site.", "summaryDescription" : "Hardware Development Engineer/Signal Integrity at Amazon Data Services, Inc.. Skills: Circuit board design, Signal integrity. Own next-generation server components. Focus on digital circuit board design", "postedDate" : "2026-06-13T20:41:39.841", "createdAt" : "2026-06-13T20:41:39.841", "lastUpdated" : "2026-06-15T07:47:09.867", "ingestTimestamp" : "2026-06-13T20:41:39.841", "mongoId" : "68e0a7e4ce260f92cbf8eba8", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3099353/apply", "salaryAnnualMin" : 125700, "salaryAnnualMax" : 219900, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Signal integrity analysis", "PCB design techniques", "Circuit board design", "Signal integrity", "System design", "Architecture development", "Cloud computing infrastructure", "Server components" ], "skillCount" : 8, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "_score" : 342.55927, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "69ced86e2beec4dd3d8498d5", "title" : "Mixed Abilities-Elem - Mixed Abilities (2026-2027 School Year)", "industry" : "Education", "salary" : { "min" : 55000.0, "max" : 75000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "The estimated salary is based on the market baseline for a Mid-level Elementary School Teacher in Val Jackson Elementary School, United States, with adjustments for the education industry and full-time employment." }, "location" : "Val Jackson Elementary School", "locations" : [ "Val Jackson Elementary School", "2717 N. Woodlawn", "67220" ], "certifications" : [ "Licensed in Kansas to teach at Functional Special Education/Low Incidence Level - K-6", "Valid Kansas Driver's License" ], "timestamp" : "2026-06-15T23:11:44.940", "fingerprint" : "e6b4da3f3d18f98e22a210d2b84bbaa0c0030649c0085f30c3b03dc38da1daf0", "source" : "taleo", "language" : "en", "applyUrl" : "https://aa308.taleo.net/careersection/ex/jobdetail.ftl?job=95814", "externalId" : "95814", "industryFunction" : { }, "structuredLocations" : [ { "state" : "Kansas", "country" : "United States", "continent" : "na", "workMode" : "onsite" } ], "locationText" : "Kansas, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "majorSkills" : "Special Education, IEP development, Differentiated instruction", "majorSkillsList" : [ "Special Education", "IEP development", "Differentiated instruction" ], "coreResponsibilities" : "Plan according to state standards and student IEPs, Participate on pre-assessment teams, Initiate, schedule, and attend IEP meetings, Diagnose student needs, Structure IEP for each student, Implement IEP for each student, Define daily expectations, Structure daily expectations, Communicate daily expectations, Communicate with parents, Communicate with regular education staff, Communicate with special education staff, Communicate with other stakeholders, Report student data, Negotiate schedules, Provide differentiated instruction, Adapt course content, Adjust reading levels, Discern learning styles, Build memory and study skills, Assist students in achieving academic objectives, Assist students in achieving daily living skills, Assist students in achieving social skills, Work with students individually, Work with students in small groups, Present learning opportunities, Support regular classroom teachers, Prepare and display events, Prepare reinforcement activities, Evaluate according to state standards, Evaluate according to student IEPs, Plan assessments, Design subject-based reinforcement, Design a grading system, Collect student data, Enter student data, Report student progress, Provide a positive role model, Develop classroom structure, Teach classroom structure, Review classroom structure, Develop classroom rules, Design classroom rules, Design systems for handling behavior, Prepare physical condition of classroom, Maintain a clean classroom, Maintain an organized classroom, Keep daily records, Supervise paraprofessionals, Manage job duties, Participate in teacher committee work, Attend teacher daily lunch activities, Prepare students for travel, Escort students to special classes, Supervise bus loading, Supervise bus unloading, Attend programs and events, Perform additional duties as assigned", "teamCollaboration" : "Multi-disciplinary team; Regular education staff; Special education staff; Other stakeholders; Teacher committee work", "domainKnowledge" : "Individual Education Program (IEP); State standards; Special Education; Low Incidence Level", "domainList" : [ "individual-education-program-iep", "state-standards", "special-education", "low-incidence-level" ], "domainSpecificKnowledge" : [ "Individual Education Program (IEP)", "State standards", "Special Education", "Low Incidence Level" ], "toolProficiency" : [ "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "communicationSkills" : "Communicate with parents; Communicate with staff; Communicate with stakeholders; Communicate with administration; Communicate with students", "documentationSkills" : "Keep daily records", "specialRequirements" : "Ability to lift students, Ability to dress students, Ability to position students, Mobility, Agility, Dexterity, Focused observation, Ability to work outdoors", "qualificationsBasic" : "Bachelor of Arts or Science in Education, Licensed in Kansas to teach at Functional Special Education/Low Incidence Level - K-6, Valid Kansas Driver's License", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Job Title: Mixed Abilities-Elementary Position Function: The person filling this position plans, leads, facilitates, and provides instruction for maximum student learning in his/her least restrictive learning environment. This position follows each student's standards-based Individual Education Program (IEP) to ensure appropriate curriculum-based instruction. Essential Performance Responsibilities: Plans according to state standards and student IEPS Participates, as appropriate, on pre-assessment teams to determine necessity for comprehensive student evaluation, initiates, schedules, and attends IEP meetings; works with multi-disciplinary team to diagnose need; structures/implements IEP for each student identified Defines, structures, and communicates daily expectations according to state standards and IEP including but not limited to, course goals, objectives, learning methods, and activities Communicates with parents, regular education staff members, special education staff members, and other appropriate stakeholders on course instructional strategies and objectives, students' grasp of material, outcomes and perspectives for applications of materials learned Receives and reports student progress; in-puts student data via computer; negotiates schedules and communicates with all pertinent participants (administration, parents, staff, students, etc.) Provides differentiated instruction based on the student's individual level of functioning and preferred/necessary learning modalities Controls classroom and teaches individual behavior through classroom structure, routine, communication opportunities, and individualized behavior methods; adapts and adjusts course content and reading levels to specify skills to be taught; discerns learning styles and means of building memory and study skills; assists individual students in achieving academic, daily living, and social skills learning objectives by working with them individually and in small groups Presents various learning opportunities appropriate to each student's IEP including, but not limited to, classroom structure, multi-media, assistive technology, alternative communication opportunities, support of regular classroom teachers, and other presentations and/or opportunities inside or outside Prepares and displays events and reinforcement activities which encourage participation Evaluates according to state standards and student IEPs Plans assessments for evaluation to include, but not limited to, various diagnostic techniques; standardized survey and criterion-referenced test; teacher-developed oral and written tests; student personal indices (effort, potential, interests, memory) Designs subject-based reinforcement to follow assessments and student's learning objectives (computer lab activities, working independently or on group projects, field/community reinforcement) Designs a grading system which encourages motivation and participation; collects and enters student data in computer from charts and observations; reports progress on a regular basis as required Provides a positive role model of appropriate and respectful interactions with students and staff Develops, teaches, and reviews clear and concise classroom structure, rules, routines, procedures, and expectations individualized to student need. Designs classroom rules for student interaction (courtesy and respect for belongings, space, and ideas), self-control, working independently, and appropriately gaining the floor; designs systems for handling all the behavior (from simple infractions to severe behavior) Prepares physical condition of classroom to reflect subject matter to facilitate student learning and maintains a clean and organized classroom Keeps daily records on, but not limited to, student attendance, learning and social needs, assignments, assessments and discipline; supervises paraprofessionals. Manages all job duties with the mobility, agility, dexterity, and focused observation necessary to adequately perform the essential duties as described above Participates in teacher committee work and attends teacher meetings; daily lunch activities as assigned; prepares and/or escorts students to travel to special classes as required; supervises bus loading and unloading as required; attends programs and events related to school Additional Duties: Additional duties as assigned by supervisor Equipment: This position requires the ability to use SMART boards and iPads in addition to basic office equipment such as computers, copiers, scanners, and fax machine Travel: Limited travel may be required Physical and Mental Demands: Good physical health and ability to implement behavioral strategies as well as to lift, dress, and position students as needed for self-care and safety Works in standard office and school building environments Ability to work outdoors during outdoor student activities Additional demands upon request of Principal, Superintendent Must be able to respond rapidly in emergency situations Knowledge, Skills, and Abilities: Ability to communicate both verbally and written in order to communicate with others inside and outside of the organization for the purpose of giving and obtaining information Ability to communicate effectively with a Supervisor when their discretion is needed Ability to perform as an effective team player Ability to plan, organize, make decisions and prioritize work to meet the daily demands of the building Exhibit a professional manner and a positive attitude Use good judgment to make decisions on recurring assignments Display a significant degree of professionalism and confidentiality Ability to conform to proper standards of professional dress and appearance Knowledge of company's mission, purpose, goals and the role of every employee in achieving each of them Interrelations: Contact with personnel within the district and with customers and vendors Will be working under the direct supervision of the department supervisor in order to complete day to day tasks Will be working with a diverse population requiring the ability to handle all situations with tact and diplomacy Must understand and respond appropriately to customer needs and maintain a positive attitude with all customers and colleagues Expected to interact with all internal and external customers in a friendly, professional manner and provide quick, responsive customer service Employee Punctuality and Appearance: In order for schools to operate effectively, employees are expected to perform all assigned duties and work all scheduled hours during each designated workday, unless the employee has received approved leave Any deviation from assigned hours must have prior approval from the employee's supervisor or building administrator All employees are required to report to work dressed in a manner that reflects a positive image of USD 259 and is appropriate for their position Qualification Profile: Bachelor of Arts or Science in Education with an emphasis on Special Education Licensed in the State of Kansas to teach at the Functional Special Education/Low Incidence Level - K-6 level required Valid Kansas Driver's License required FLSA Status: Exempt", "summaryDescription" : "Mixed Abilities-Elem - Mixed Abilities (2026-2027 School Year). Skills: Special Education, IEP development, Differentiated instruction. Plan according to state standards and student IEPs. Participate on pre-assessment teams", "createdAt" : "2026-06-14T20:46:54.403", "lastUpdated" : "2026-06-15T23:11:44.940", "ingestTimestamp" : "2026-06-14T20:46:54.403", "mongoId" : "69ced86e2beec4dd3d8498d5", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 55000, "salaryAnnualMax" : 75000, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "Special Education", "IEP development", "Differentiated instruction", "Individual Education Program (IEP)", "State standards", "Low Incidence Level", "Licensed in Kansas to teach at Functional Special Education/Low Incidence Level - K-6", "Valid Kansas Driver's License", "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "skillCount" : 14, "jobCategory" : "education", "jobSubcategory" : "support", "seniorityLevel" : "Mid", "dataQualityScore" : 0.6666667, "_score" : 335.057, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Education", "llmIndustryConfidence" : 0.98 }, { "id" : "69cf3f072beec4dd3d93425e", "title" : "Sr. Signal Integrity HDE, PCIe & Signal Integrity Team", "company" : "Amazon Data Services, Inc.", "industry" : "Hardware Development, Cloud Hardware Development, Cloud Computing", "salary" : { "min" : 159000.0, "max" : 215300.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Seattle, Washington, USA", "locations" : [ "Seattle, Washington, USA" ], "timestamp" : "2026-06-15T02:20:50.081", "fingerprint" : "405cc4b9b8478786f0b62823b0c4badbe56d0e53029101bfbea6eb95cddf8a6f", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10381564/apply", "externalId" : "c86b2ca0-4829-4ca5-8530-01b32e56e0f4", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Seattle", "state" : "Washington", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "47.6038321,-122.3300620" } ], "locationText" : "Seattle, Washington, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "PCIe, DDR, USB, Allegro, CAM350, Ansys, Cadence Sigrity", "professionalSkills" : [ "Signal integrity analysis", "High-speed PCB design", "Electrical product design", "Interface design", "PCB design reviews", "Signal integrity simulation", "Power Integrity analysis", "Root cause analysis" ], "hardSkillsList" : [ "Signal integrity analysis", "High-speed PCB design", "Electrical product design", "Interface design", "PCB design reviews", "Signal integrity simulation", "Power Integrity analysis", "Root cause analysis" ], "softSkillsList" : [ "Team-driven", "Customer-obsessed" ], "hardSkills" : [ { "name" : "Signal integrity analysis", "level" : "intermediate" }, { "name" : "High-speed PCB design", "level" : "intermediate" }, { "name" : "Electrical product design", "level" : "intermediate" }, { "name" : "Interface design", "level" : "intermediate" }, { "name" : "PCB design reviews", "level" : "intermediate" }, { "name" : "Signal integrity simulation", "level" : "intermediate" }, { "name" : "Power Integrity analysis", "level" : "intermediate" }, { "name" : "Root cause analysis", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Team-driven" }, { "name" : "Customer-obsessed" } ], "majorSkills" : "Signal integrity, High-speed interfaces, PCB design", "majorSkillsList" : [ "Signal integrity", "High-speed interfaces", "PCB design" ], "coreResponsibilities" : "Own signal integrity of next-generation server components, Own signal integrity of next-generation server systems, Work on architecture of high-speed PCB designs, Work on development of high-speed PCB designs, Work on architecture of complex PCB designs, Work on development of complex PCB designs, Design server components, Design motherboards, Design graphics accelerators, Design programmable hardware, Optimize high-speed interfaces, Ensure robust system performance, Interact with interdisciplinary team of engineers, Design server hardware, Develop server hardware, Validate server hardware, Launch server hardware, Design server software, Develop server software, Validate server software, Launch server software", "teamCollaboration" : "Interdisciplinary team of engineers; People across AWS", "domainKnowledge" : "Signal integrity; High-speed interfaces; PCB design; Server hardware; Cloud computing", "domainList" : [ "signal-integrity", "high-speed-interfaces", "pcb-design", "server-hardware", "cloud-computing" ], "domainSpecificKnowledge" : [ "Signal integrity", "High-speed interfaces", "PCB design", "Server hardware", "Cloud computing" ], "toolProficiency" : [ "Allegro", "CAM350", "Ansys", "Cadence Sigrity" ], "continuousLearning" : "Ongoing events; Learning experiences; Knowledge-sharing; Mentorship", "innovationCreativity" : "Bold ideas", "problemSolvingSkills" : "Root cause analysis; Problem solving", "outcomesObjectives" : "Deliver highest standards for safety; Deliver highest standards for security; Provide seemingly infinite capacity; Provide lowest possible cost", "qualificationsBasic" : "Bachelor's degree or above in electrical engineering, computer engineering, or equivalent, 5+ years of experience performing signal integrity analysis, 5+ years of experience optimizing high-speed PCB designs for signal integrity, 10+ years of experience designing complex electrical products at volume, Experience in high-speed interface design (DDR, PCIe, USB, etc.), Experience with PCB design tools (Allegro, CAM350, or equivalent), Demonstrated ability to perform detailed PCB reviews, Experience with signal integrity simulation tools (Ansys, Cadence Sigrity, or similar)", "qualificationsPreferred" : "Master's degree or above in electrical engineering, computer engineering, or equivalent, Experience in server design for cloud or enterprise applications, Experience in Power Integrity analysis and optimization, Experience in thermal considerations, Experience in designing complex high-speed PCB design, Experience optimizing multi-layer PCB stack-up and routing, Experience in board root cause analysis and resolution, Experience focusing on signal integrity issues", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "AWS EC2 owns the design, planning, delivery, and operation of all AWS server instances. In other words, we’re the people who keep the cloud running. We support all AWS compute, storage, accelerator servers and ensure our customers have continual access to the innovation they rely on. We work on the most challenging problems, with thousands of variables impacting the supply chain — and we’re looking for talented people who want to help. You’ll join a diverse team of hardware engineers, software engineers, system engineers, technical program managers, and other vital roles. You’ll collaborate with people across AWS to help us deliver the highest standards for safety and security while providing seemingly infinite capacity at the lowest possible cost for our customers. And you’ll experience an inclusive culture that welcomes bold ideas and empowers you to own them to completion. Key job responsibilities AWS Hardware Engineering is looking for a customer-obsessed, team-driven technology leader to take our engineering of server hardware and software to the next level. As a hardware engineer on the PCIe and Signal Integrity team within the Core Components Organization, you will own the signal integrity of next-generation server components and systems. You will work on the architecture and development of high-speed, complex PCB designs for server components, including PCIe, motherboards, graphics, accelerators, and programmable hardware. Your expertise in signal integrity analysis and advanced PCB design techniques will be crucial for optimizing high-speed interfaces and ensuring robust system performance. You will interact with an interdisciplinary team of engineers to design, develop, validate, and launch a scale. At AWS we are changing the industry and want individuals who are ready for a challenge to reach beyond what is possible today. About the team Why AWS Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses. Inclusive Team Culture Here at AWS, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness. Work/Life Balance We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud. Mentorship and Career Growth We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional. Diverse Experiences Amazon values diverse experiences. Even if you do not meet all of the preferred qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying. Basic Qualifications: - Bachelor's degree or above in electrical engineering, computer engineering, or equivalent - 5+ years of experience performing signal integrity analysis and optimizing high-speed PCB designs for signal integrity. - 10+ years of experience designing complex electrical products at volume. - Experience in high-speed interface design (DDR, PCIe, USB, etc.) with emphasis on signal integrity. - Experience with PCB design tools (Allegro, CAM350, or equivalent) and demonstrated ability to perform detailed PCB reviews. - Experience with signal integrity simulation tools (Ansys, Cadence Sigrity, or similar). Preferred Qualifications: - Master's degree or above in electrical engineering, computer engineering, or equivalent - Experience in server design for cloud or enterprise applications. - Experience in Power Integrity analysis and optimization, including thermal considerations. - Experience in designing complex high-speed PCB design, optimizing multi-layer PCB stack-up and routing for high-speed interfaces. - Experience in board root cause analysis and resolution, particularly focusing on signal integrity issues. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, WA, Seattle - 159,200.00 - 215,300.00 USD annually", "summaryDescription" : "Sr. Signal Integrity HDE, PCIe & Signal Integrity Team at Amazon Data Services, Inc.. Skills: Signal integrity, High-speed interfaces, PCB design. Own signal integrity of next-generation server components. Own signal integrity of next-generation server systems", "postedDate" : "2026-06-13T12:58:07.166", "createdAt" : "2026-06-13T12:58:07.166", "lastUpdated" : "2026-06-15T02:20:50.081", "ingestTimestamp" : "2026-06-13T12:58:07.166", "mongoId" : "69cf3f072beec4dd3d93425e", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10381564/apply", "salaryAnnualMin" : 159000, "salaryAnnualMax" : 215300, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Signal integrity analysis", "High-speed PCB design", "Electrical product design", "Interface design", "PCB design reviews", "Signal integrity simulation", "Power Integrity analysis", "Root cause analysis", "Team-driven", "Customer-obsessed", "Signal integrity", "High-speed interfaces", "PCB design", "Server hardware", "Cloud computing", "Allegro", "CAM350", "Ansys", "Cadence Sigrity" ], "skillCount" : 19, "jobCategory" : "other", "dataQualityScore" : 1.0, "_score" : 334.60736, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6908583a70f0b99d58ea1279", "title" : "Junior Signal and Power integrity Engineer", "company" : "Annapurna Labs Ltd.", "industry" : "Hardware Development, Software Development, Cloud Computing", "salary" : { "min" : 140000.0, "max" : 195000.0, "currency" : "ILS", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Junior Signal and Power Integrity Engineers in Haifa, Israel, adjusted for entry-level experience and the technology industry." }, "location" : "Haifa, HA, ISR", "locations" : [ "Haifa, HA, ISR" ], "timestamp" : "2026-06-15T04:45:32.522", "fingerprint" : "cdb78d3b21cc52af2b99e5a78150e4861a6801c8735b564cc736fb5d9783087c", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3119653/apply", "externalId" : "f04ce2a6-cb54-4f86-ab68-359fb150dbd8", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Haifa", "state" : "Haifa", "country" : "Israel", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "32.8191218,34.9983856" } ], "locationText" : "Haifa, Haifa, Israel", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 0, "experienceMaxYears" : 3, "experienceLevel" : "Entry", "technicalSkills" : "PCIe, DDR, Ethernet, SI/PI simulation tools, HFSS, Sigrity, HSpice, Oscilloscopes, Spectrum analyzers, RF measurement equipment, Mixed-signal measurement equipment", "professionalSkills" : [ "Signal integrity", "Power integrity", "IC Package Design", "Electrical interfaces", "Floor-planning", "PCB routing", "Layout routing", "Electrical characterization", "Physical design", "Electromagnetic theory" ], "hardSkillsList" : [ "Signal integrity modeling", "Power integrity modeling", "High-speed interfaces", "Lab work" ], "hardSkills" : [ { "name" : "Signal integrity modeling", "level" : "intermediate" }, { "name" : "Power integrity modeling", "level" : "intermediate" }, { "name" : "High-speed interfaces", "level" : "intermediate" }, { "name" : "Lab work", "level" : "intermediate" } ], "majorSkills" : "Signal Integrity, Power Integrity, IC Package Design", "majorSkillsList" : [ "Signal Integrity", "Power Integrity", "IC Package Design" ], "coreResponsibilities" : "Work on high-speed interfaces, End-to-end solution of high-speed, Address SI/PI considerations, Optimize layout routing, Signal integrity modeling, Power integrity modeling, Perform lab work, Electrical characterization", "teamCollaboration" : "BackEnd team; System team", "domainKnowledge" : "Signal Integrity; Power Integrity; IC Package Design; Electromagnetic theory", "domainList" : [ "signal-integrity", "power-integrity", "ic-package-design", "electromagnetic-theory" ], "domainSpecificKnowledge" : [ "Signal Integrity", "Power Integrity", "IC Package Design", "Electromagnetic theory" ], "toolProficiency" : [ "HFSS", "Sigrity", "HSpice", "Oscilloscopes", "Spectrum analyzers" ], "continuousLearning" : "Comprehensive training program", "qualificationsBasic" : "BSc in Electrical Engineering, BSc in Electrical Engineering and Physics, Foundations in physics, Foundations in electromagnetics", "qualificationsPreferred" : "Communication, Electromagnetics, Signal processing, Microelectronics, Previous experience with lab equipment, Familiarity with simulation/extraction tools", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Lab’s Chip development team. The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives. The team’s work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGA’s substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes. We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain. Key job responsibilities As a SIP engineer, you will be involved in: • Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet. • End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing. • Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools. • Hands-on lab work involving oscilloscopes, spectrum analyzers, and other RF/mixed-signal measurement equipment, for advanced electrical characterization. You will undergo a comprehensive training program, providing you with the essential knowledge and skills required to succeed in this field. The work is multidisciplinary, bridging physical design, electromagnetic theory, and practical engineering challenges. Basic Qualifications: - BSc in Electrical Engineering or Electrical Engineering and Physics. Make sure to include a grade sheet with your CV, in a single PDF. - Strong foundations in physics and electromagnetics. Preferred Qualifications: - Communication, Electromagnetics, Signal processing, Microelectronics. - Previous experience with lab equipment (e.g oscilloscope, spectrum analyzer). - Familiarity with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice). Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "Junior Signal and Power integrity Engineer at Annapurna Labs Ltd.. Skills: Signal Integrity, Power Integrity, IC Package Design. Work on high-speed interfaces. End-to-end solution of high-speed", "postedDate" : "2026-06-13T11:28:42.884", "createdAt" : "2026-06-13T11:28:42.884", "lastUpdated" : "2026-06-15T04:45:32.522", "ingestTimestamp" : "2026-06-13T11:28:42.884", "mongoId" : "6908583a70f0b99d58ea1279", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3119653/apply", "salaryBand" : "100k-150k", "hasSalary" : false, "allSkills" : [ "Signal integrity modeling", "Power integrity modeling", "High-speed interfaces", "Lab work", "Signal Integrity", "Power Integrity", "IC Package Design", "Signal integrity", "Power integrity", "Electrical interfaces", "Floor-planning", "PCB routing", "Layout routing", "Electrical characterization", "Physical design", "Electromagnetic theory", "HFSS", "Sigrity", "HSpice", "Oscilloscopes", "Spectrum analyzers" ], "skillCount" : 21, "jobCategory" : "other", "dataQualityScore" : 1.0, "_score" : 333.7316, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true }, { "id" : "69fd35614c40e2acd1b31f12", "title" : "Mixed Abilities-Elem - Mixed Abilities (2026-2027 School Year)", "industry" : "Education", "salary" : { "min" : 55000.0, "max" : 85000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-seniority Elementary School Teacher in Samuel E Spaght Science and Communications Magnet Elementary School, United States, with adjustments for industry and location." }, "location" : "Samuel E Spaght Science and Communications Magnet Elementary School", "locations" : [ "Samuel E Spaght Science and Communications Magnet Elementary School", "2316 E. 10th", "67214" ], "certifications" : [ "Licensed in Kansas to teach", "Functional Special Education/Low Incidence Level - K-6 level", "Valid Kansas Driver's License" ], "timestamp" : "2026-06-16T04:15:35.008", "fingerprint" : "30537e5a1cffe590f2fe9db0728b90ab8a51ea07d3cc162284cca1a852d79161", "source" : "taleo", "language" : "en", "applyUrl" : "https://aa308.taleo.net/careersection/ex/jobdetail.ftl?job=97694", "externalId" : "97694", "industryFunction" : { }, "structuredLocations" : [ { "country" : "United States", "continent" : "na", "workMode" : "onsite" } ], "locationText" : "United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "professionalSkills" : [ "Student evaluation", "Curriculum instruction", "Behavioral strategies", "Data collection", "Progress reporting" ], "hardSkillsList" : [ "IEP development", "Differentiated instruction", "Behavior management", "Classroom structure", "Record keeping" ], "hardSkills" : [ { "name" : "IEP development", "level" : "intermediate" }, { "name" : "Differentiated instruction", "level" : "intermediate" }, { "name" : "Behavior management", "level" : "intermediate" }, { "name" : "Classroom structure", "level" : "intermediate" }, { "name" : "Record keeping", "level" : "intermediate" } ], "majorSkills" : "Student instruction, IEP development, Behavior management", "majorSkillsList" : [ "Student instruction", "IEP development", "Behavior management" ], "coreResponsibilities" : "Plan instruction for student learning, Follow student Individual Education Program (IEP), Provide curriculum-based instruction, Participate on pre-assessment teams, Initiate, schedule, and attend IEP meetings, Diagnose student needs with multi-disciplinary team, Structure and implement IEP for each student, Define, structure, and communicate daily expectations, Communicate with parents and staff, Report student data, Negotiate schedules, Provide differentiated instruction, Control classroom behavior, Adapt course content, Discern learning styles, Assist students in achieving objectives, Present learning opportunities, Prepare and display events, Evaluate according to state standards and IEPs, Plan assessments, Design subject-based reinforcement, Design a grading system, Collect and enter student data, Provide a positive role model, Develop, teach, and review classroom structure, Design classroom rules for student interaction, Design systems for handling behavior, Prepare physical condition of classroom, Maintain a clean and organized classroom, Keep daily records on student attendance, Supervise paraprofessionals, Manage job duties with mobility and agility, Participate in teacher committee work, Attend teacher daily lunch activities, Prepare and escort students to special classes, Supervise bus loading and unloading, Attend programs and events", "teamCollaboration" : "Multi-disciplinary team; Regular education staff; Special education staff; Other stakeholders; Teacher committee work", "domainKnowledge" : "Special Education; Individual Education Program (IEP); Least restrictive environment; State standards", "domainList" : [ "special-education", "individual-education-program-iep", "least-restrictive-environment", "state-standards" ], "domainSpecificKnowledge" : [ "Special Education", "Individual Education Program (IEP)", "Least restrictive environment", "State standards" ], "toolProficiency" : [ "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "communicationSkills" : "Communicate with parents; Communicate with staff; Communicate with students; Communicate with administration", "documentationSkills" : "Keep daily records; Report student data", "problemSolvingSkills" : "Diagnose student needs; Adapt course content; Handle behavior situations", "specialRequirements" : "Lift students, Dress students, Position students, Work outdoors, Mobility, Agility, Dexterity, Focused observation, Supervise bus loading/unloading", "outcomesObjectives" : "Ensure appropriate curriculum-based instruction; Achieve academic objectives; Achieve daily living objectives; Achieve social skills objectives", "qualificationsBasic" : "Bachelor of Arts or Science in Education, Special Education emphasis, Licensed in Kansas to teach, Functional Special Education/Low Incidence Level - K-6 level, Valid Kansas Driver's License", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Job Title: Mixed Abilities-Elementary Position Function: The person filling this position plans, leads, facilitates, and provides instruction for maximum student learning in his/her least restrictive learning environment. This position follows each student's standards-based Individual Education Program (IEP) to ensure appropriate curriculum-based instruction. Essential Performance Responsibilities: Plans according to state standards and student IEPS Participates, as appropriate, on pre-assessment teams to determine necessity for comprehensive student evaluation, initiates, schedules, and attends IEP meetings; works with multi-disciplinary team to diagnose need; structures/implements IEP for each student identified Defines, structures, and communicates daily expectations according to state standards and IEP including but not limited to, course goals, objectives, learning methods, and activities Communicates with parents, regular education staff members, special education staff members, and other appropriate stakeholders on course instructional strategies and objectives, students' grasp of material, outcomes and perspectives for applications of materials learned Receives and reports student progress; in-puts student data via computer; negotiates schedules and communicates with all pertinent participants (administration, parents, staff, students, etc.) Provides differentiated instruction based on the student's individual level of functioning and preferred/necessary learning modalities Controls classroom and teaches individual behavior through classroom structure, routine, communication opportunities, and individualized behavior methods; adapts and adjusts course content and reading levels to specify skills to be taught; discerns learning styles and means of building memory and study skills; assists individual students in achieving academic, daily living, and social skills learning objectives by working with them individually and in small groups Presents various learning opportunities appropriate to each student's IEP including, but not limited to, classroom structure, multi-media, assistive technology, alternative communication opportunities, support of regular classroom teachers, and other presentations and/or opportunities inside or outside Prepares and displays events and reinforcement activities which encourage participation Evaluates according to state standards and student IEPs Plans assessments for evaluation to include, but not limited to, various diagnostic techniques; standardized survey and criterion-referenced test; teacher-developed oral and written tests; student personal indices (effort, potential, interests, memory) Designs subject-based reinforcement to follow assessments and student's learning objectives (computer lab activities, working independently or on group projects, field/community reinforcement) Designs a grading system which encourages motivation and participation; collects and enters student data in computer from charts and observations; reports progress on a regular basis as required Provides a positive role model of appropriate and respectful interactions with students and staff Develops, teaches, and reviews clear and concise classroom structure, rules, routines, procedures, and expectations individualized to student need. Designs classroom rules for student interaction (courtesy and respect for belongings, space, and ideas), self-control, working independently, and appropriately gaining the floor; designs systems for handling all the behavior (from simple infractions to severe behavior) Prepares physical condition of classroom to reflect subject matter to facilitate student learning and maintains a clean and organized classroom Keeps daily records on, but not limited to, student attendance, learning and social needs, assignments, assessments and discipline; supervises paraprofessionals. Manages all job duties with the mobility, agility, dexterity, and focused observation necessary to adequately perform the essential duties as described above Participates in teacher committee work and attends teacher meetings; daily lunch activities as assigned; prepares and/or escorts students to travel to special classes as required; supervises bus loading and unloading as required; attends programs and events related to school Additional Duties: Additional duties as assigned by supervisor Equipment: This position requires the ability to use SMART boards and iPads in addition to basic office equipment such as computers, copiers, scanners, and fax machine Travel: Limited travel may be required Physical and Mental Demands: Good physical health and ability to implement behavioral strategies as well as to lift, dress, and position students as needed for self-care and safety Works in standard office and school building environments Ability to work outdoors during outdoor student activities Additional demands upon request of Principal, Superintendent Must be able to respond rapidly in emergency situations Knowledge, Skills, and Abilities: Ability to communicate both verbally and written in order to communicate with others inside and outside of the organization for the purpose of giving and obtaining information Ability to communicate effectively with a Supervisor when their discretion is needed Ability to perform as an effective team player Ability to plan, organize, make decisions and prioritize work to meet the daily demands of the building Exhibit a professional manner and a positive attitude Use good judgment to make decisions on recurring assignments Display a significant degree of professionalism and confidentiality Ability to conform to proper standards of professional dress and appearance Knowledge of company's mission, purpose, goals and the role of every employee in achieving each of them Interrelations: Contact with personnel within the district and with customers and vendors Will be working under the direct supervision of the department supervisor in order to complete day to day tasks Will be working with a diverse population requiring the ability to handle all situations with tact and diplomacy Must understand and respond appropriately to customer needs and maintain a positive attitude with all customers and colleagues Expected to interact with all internal and external customers in a friendly, professional manner and provide quick, responsive customer service Employee Punctuality and Appearance: In order for schools to operate effectively, employees are expected to perform all assigned duties and work all scheduled hours during each designated workday, unless the employee has received approved leave Any deviation from assigned hours must have prior approval from the employee's supervisor or building administrator All employees are required to report to work dressed in a manner that reflects a positive image of USD 259 and is appropriate for their position Qualification Profile: Bachelor of Arts or Science in Education with an emphasis on Special Education Licensed in the State of Kansas to teach at the Functional Special Education/Low Incidence Level - K-6 level required Valid Kansas Driver's License required FLSA Status: Exempt", "summaryDescription" : "Mixed Abilities-Elem - Mixed Abilities (2026-2027 School Year). Skills: Student instruction, IEP development, Behavior management. Plan instruction for student learning. Follow student Individual Education Program (IEP)", "createdAt" : "2026-06-14T18:51:26.006", "lastUpdated" : "2026-06-16T04:15:35.008", "ingestTimestamp" : "2026-06-14T18:51:26.006", "mongoId" : "69fd35614c40e2acd1b31f12", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 55000, "salaryAnnualMax" : 85000, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "IEP development", "Differentiated instruction", "Behavior management", "Classroom structure", "Record keeping", "Student instruction", "Student evaluation", "Curriculum instruction", "Behavioral strategies", "Data collection", "Progress reporting", "Special Education", "Individual Education Program (IEP)", "Least restrictive environment", "State standards", "Licensed in Kansas to teach", "Functional Special Education/Low Incidence Level - K-6 level", "Valid Kansas Driver's License", "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "skillCount" : 24, "jobCategory" : "education", "jobSubcategory" : "support", "seniorityLevel" : "Mid", "dataQualityScore" : 0.6666667, "_score" : 328.7206, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Education", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2ca0b774d8ee00a09a30a1", "title" : "Staff Analog Layout Engineer", "company" : "Neurophos", "industry" : "Engineering", "salary" : { "min" : 180000.0, "max" : 225000.0, "currency" : "USD", "frequency" : "Yearly" }, "location" : "San Jose, California", "locations" : [ "San Jose, California" ], "timestamp" : "2026-06-15T13:38:35.509", "fingerprint" : "fa26575cc980e9ee9f37d4a8da9573dd214cbd5b871ca444e524c48533057cac", "source" : "ashby", "language" : "en", "applyUrl" : "https://jobs.ashbyhq.com/neurophos/1d6bd8fd-ead0-4fe0-ae4a-4316d361110e/application", "externalId" : "1d6bd8fd-ead0-4fe0-ae4a-4316d361110e", "industryFunction" : { }, "structuredLocations" : [ { "city" : "San Jose", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3361663,-121.8905910" }, { "city" : "Hsinchu", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "24.8066333,120.9686833" } ], "locationText" : "San Jose, California, United States; Hsinchu, Taiwan", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "FinFET, GAA nodes", "hardSkillsList" : [ "IC layout", "Parasitic reduction", "Matching strategies", "Electromigration", "IR drop analysis" ], "hardSkills" : [ { "name" : "IC layout", "level" : "intermediate" }, { "name" : "Parasitic reduction", "level" : "intermediate" }, { "name" : "Matching strategies", "level" : "intermediate" }, { "name" : "Electromigration", "level" : "intermediate" }, { "name" : "IR drop analysis", "level" : "intermediate" } ], "majorSkills" : "Analog Layout, Deep-submicron processes, TSMC processes", "majorSkillsList" : [ "Analog Layout", "Deep-submicron processes", "TSMC processes" ], "coreResponsibilities" : "Perform custom IC layout execution, Optimize layout solutions, Deliver IP-level floor planning, Implement layout techniques, Execute block-level design sign-offs, Evaluate layout trade-offs, Implement power and clock delivery, Coordinate with designers, CAD engineers, EDA vendors", "teamCollaboration" : "Circuit designers; CAD engineers; EDA vendors", "domainKnowledge" : "TSMC N12; TSMC N3P; TSMC N2P; Deep-submicron processes; Restricted Design Rules; Electromigration; PLLs; Data Converters; ADC; DAC", "domainList" : [ "tsmc-n12", "tsmc-n3p", "tsmc-n2p", "deep-submicron-processes", "restricted-design-rules", "electromigration", "plls", "data-converters", "adc", "dac" ], "domainSpecificKnowledge" : [ "TSMC N12", "TSMC N3P", "TSMC N2P", "Deep-submicron processes", "Restricted Design Rules", "Electromigration", "PLLs", "Data Converters", "ADC", "DAC" ], "toolProficiency" : [ "Cadence Virtuoso", "Synopsys Custom Compiler", "Mentor Calibre", "Siemens ICV" ], "qualificationsBasic" : "B.S. or M.S. degree, 3-8+ years IC layout experience, Mastery of EDA tools, Deep understanding of layout techniques", "qualificationsPreferred" : "Prior tape-out success, Domain knowledge in analog/mixed signal blocks, Working knowledge of layout automation scripting", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "ABOUT NEUROPHOS The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference. We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A https://www.neurophos.com/110m-raise led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years. Join us and shape the future of computing! POSITION OVERVIEW We are seeking a seasoned Senior or Staff Analog Layout Engineer to play a vital role in developing cutting-edge full-custom electronic transceiver components that interface directly with our custom silicon photonics and are essential to our revolutionary photonic AI platform. You will develop and optimize high-performance Analog IPs tailored for TSMC’s deep-submicron processes, including N12, N3P, and N2P. You will push the boundaries of Power, Performance, and Area (PPA) while mitigating the impact of Restricted Design Rules (RDRs) and electromigration. LOCATION San Jose, CA or Hsinchu, Taiwan. Full-time onsite position. KEY RESPONSIBILITIES - Perform custom IC layout execution of high-speed analog/RF circuits. - Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions - Deliver IP-level floor planning, power planning, and signal distribution, implementing layout techniques for strict ESD and Latch-up prevention. - Execute and debug block-level design sign-offs, including DRC (Design Rule Check), LVS (Layout Versus Schematic), and RC Extraction using standard industry tools. - Evaluate layout trade-offs among area, yield, and performance; implement the power and clock delivery networks to ensure power and signal integrity. - Coordinate directly with circuit designers, CAD engineers, and EDA vendors to ensure IP design fits seamlessly into the production flow. QUALIFICATIONS - B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a closely related discipline. - 3-8+ years of professional custom or block-level IC layout experience in deep-submicron, advanced FinFET/GAA nodes (3nm, 2nm, etc.). - Mastery of industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV). - Deep understanding of deep-submicron layout techniques, parasitic reduction, matching strategies, and electro-migration (EM/IR). PREFERRED SKILLS - Prior tape-out success in TSMC N3 or N2 process nodes. - Domain knowledge in laying out high-performance analog/mixed signal blocks, such as PLLs and Data Converters (ADC/DAC). - Working knowledge of layout automation scripting languages (e.g., TCL, Perl, Python). WHAT WE OFFER This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world. BENEFITS Join a team that invests in your future and your well-being. At Neurophos, we offer: - 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions. - Unlimited PTO. No rigid vacation banks, just a focus on delivery. - 401(k) matching and stock option opportunities to ensure our success is your success. - Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance. - Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.", "summaryDescription" : "Staff Analog Layout Engineer at Neurophos. Skills: Analog Layout, Deep-submicron processes, TSMC processes. Perform custom IC layout execution. Optimize layout solutions", "createdAt" : "2026-06-14T09:34:41.234", "lastUpdated" : "2026-06-15T13:38:35.509", "ingestTimestamp" : "2026-06-14T09:34:41.234", "mongoId" : "6a2ca0b774d8ee00a09a30a1", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 180000, "salaryAnnualMax" : 225000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "IC layout", "Parasitic reduction", "Matching strategies", "Electromigration", "IR drop analysis", "Analog Layout", "Deep-submicron processes", "TSMC processes", "TSMC N12", "TSMC N3P", "TSMC N2P", "Restricted Design Rules", "PLLs", "Data Converters", "ADC", "DAC", "Cadence Virtuoso", "Synopsys Custom Compiler", "Mentor Calibre", "Siemens ICV" ], "skillCount" : 20, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 0.8888889, "_score" : 327.43018, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2d6c5a74d8ee00a0bdcec1", "title" : "Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout)", "company" : "Sandisk", "industry" : "Computer Hardware", "salary" : { "min" : 4500000.0, "max" : 7000000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout) in Bengaluru, India, adjusted for lead seniority and the technology industry." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-15T08:25:19.709", "fingerprint" : "df5107037ad3afb289cf6597132d01c666518807ab60cf0f56bdbf9c19afb10b", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000126659825-principal-engineer-asic-development-engineering-mixed-signal-ip-layout-", "externalId" : "744000126659825", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "CMOS, FinFET, DDR IO", "professionalSkills" : [ "Design principles", "Layout practices", "Methodologies" ], "hardSkillsList" : [ "Layout design", "Custom layout design", "Signal integrity", "Analog design", "IO design", "ESD mitigation", "Latch-up mitigation", "Electromigration management", "IR drop management", "Self-heating management", "Power optimization", "Performance optimization", "Area optimization" ], "hardSkills" : [ { "name" : "Layout design", "level" : "intermediate" }, { "name" : "Custom layout design", "level" : "intermediate" }, { "name" : "Signal integrity", "level" : "intermediate" }, { "name" : "Analog design", "level" : "intermediate" }, { "name" : "IO design", "level" : "intermediate" }, { "name" : "ESD mitigation", "level" : "intermediate" }, { "name" : "Latch-up mitigation", "level" : "intermediate" }, { "name" : "Electromigration management", "level" : "intermediate" }, { "name" : "IR drop management", "level" : "intermediate" }, { "name" : "Self-heating management", "level" : "intermediate" }, { "name" : "Power optimization", "level" : "intermediate" }, { "name" : "Performance optimization", "level" : "intermediate" }, { "name" : "Area optimization", "level" : "intermediate" } ], "majorSkills" : "Mixed-Signal IP Layout, Layout optimization", "majorSkillsList" : [ "Mixed-Signal IP Layout", "Layout optimization" ], "coreResponsibilities" : "Develop and optimize MSIP IC layouts, Ensure high performance and manufacturability, Collaborate with design engineers, Understand design requirements, Translate requirements into precise layouts, Debug DRC, ERC, LVS, EMIR and PERC issues, Work closely with physical design team, Integrate custom blocks into chip design, Identify and resolve layout-related issues, Provide creative solutions, Conduct design reviews, Provide technical feedback, Improve layout practices, Improve layout methodologies, Stay up-to-date industry trends, Stay up-to-date tools, Stay up-to-date technologies, Enhance layout processes", "teamCollaboration" : "Design engineers; Physical design team", "domainKnowledge" : "Analog/IO design principles; Deep sub-micron process nodes; Reliability considerations; CMOS technologies; FinFET technologies; Signal integrity issues; ESD; Latch-up; Electromigration; IR drop; Self-heating; Power, performance, area (PPA)", "domainList" : [ "analog-io-design-principles", "deep-sub-micron-process-nodes", "reliability-considerations", "cmos-technologies", "finfet-technologies", "signal-integrity-issues", "esd", "latch-up", "electromigration", "ir-drop", "self-heating", "power", "performance", "area-ppa" ], "domainSpecificKnowledge" : [ "Analog/IO design principles", "Deep sub-micron process nodes", "Reliability considerations", "CMOS technologies", "FinFET technologies", "Signal integrity issues", "ESD", "Latch-up", "Electromigration", "IR drop", "Self-heating", "Power, performance, area (PPA)" ], "toolProficiency" : [ "Cadence", "Synopsys", "Mentor Graphics", "Skill", "TCL", "SVRF" ], "problemSolvingSkills" : "Problem-solving skills; Creative solutions", "qualificationsBasic" : "8-12 years Analog/High Speed DDR IO IC layout design, Proficiency in layout tools Cadence, Synopsys, or Mentor Graphics, Hands-on custom layout design Analog and IO circuits, Expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, High speed DDR IOs, Familiarity with custom digital layout, Knowledge of signal integrity issues, Understanding of analog/IO design principles, Aware of layout techniques ESD, latch-up issues, Advanced knowledge CMOS and FinFET technologies, Experience with layout concepts reliability considerations, Experience with layout optimization PPA metrics, Excellent problem-solving skills, Attention to detail, Effective communication, Teamwork abilities", "qualificationsPreferred" : "AI knowledge/experience improve Layout development effort and QoR", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: * Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability. * Collaborate with design engineers to understand design requirements and translate them into precise layouts. * Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. * Work closely with the physical design team to integrate custom blocks into the overall chip design. * Identify and resolve layout-related issues, providing creative solutions to meet design specifications. * Conduct design reviews and provide technical feedback to improve layout practices and methodologies. * Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes * Any prior AI knowledge/experience which can improve Layout development effort and QoR is a big plus Qualifications * 8-12 years of experience in Analog/High Speed DDR IO IC layout design. * Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. * Hands-on experience with custom layout design for Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, High speed DDR IOs. * Familiarity with custom digital layout (i.e. high speed logic paths). * Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). * Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. * Aware of layout techniques to mitigate ESD, latch-up issues. * Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. * Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. * Experience with layout optimization for power, performance, and area (PPA) metrics. * Excellent problem-solving skills and attention to detail. * Effective communication and teamwork abilities. Preferred Skills: * Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. ## Qualifications Bachelor’s or Master’s degree in Electronics or Electrical Engineering ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying", "summaryDescription" : "Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout) at Sandisk. Skills: Mixed-Signal IP Layout, Layout optimization. Develop and optimize MSIP IC layouts. Ensure high performance and manufacturability", "postedDate" : "2026-05-15T09:51:21.000", "createdAt" : "2026-06-14T01:21:01.885", "lastUpdated" : "2026-06-15T08:25:19.709", "ingestTimestamp" : "2026-06-14T01:21:01.885", "mongoId" : "6a2d6c5a74d8ee00a0bdcec1", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Layout design", "Custom layout design", "Signal integrity", "Analog design", "IO design", "ESD mitigation", "Latch-up mitigation", "Electromigration management", "IR drop management", "Self-heating management", "Power optimization", "Performance optimization", "Area optimization", "Mixed-Signal IP Layout", "Layout optimization", "Design principles", "Layout practices", "Methodologies", "Analog/IO design principles", "Deep sub-micron process nodes", "Reliability considerations", "CMOS technologies", "FinFET technologies", "Signal integrity issues", "ESD", "Latch-up", "Electromigration", "IR drop", "Self-heating", "Power, performance, area (PPA)", "Cadence", "Synopsys", "Mentor Graphics", "Skill", "TCL", "SVRF" ], "skillCount" : 36, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 1.0, "_score" : 323.38947, "daysOld" : 30, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6949b14570f0b99d588271bd", "title" : "Mixed Abilities Teacher", "company" : "Allison Traditional Magnet Middle School", "industry" : "Education", "salary" : { "min" : 55000.0, "max" : 85000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Mixed Abilities Teacher in Allison Traditional Magnet Middle School, United States, adjusted for industry and seniority." }, "location" : "Allison Traditional Magnet Middle School", "locations" : [ "Allison Traditional Magnet Middle School", "221 S. Seneca", "67213" ], "certifications" : [ "Kansas teaching license" ], "timestamp" : "2026-06-15T08:26:30.944", "fingerprint" : "846f205b765395d8e45feb6ec236078c9a114466eda7d7ffff2ff324b5b94a15", "source" : "taleo", "language" : "en", "applyUrl" : "https://aa308.taleo.net/careersection/ex/jobdetail.ftl?job=42513", "externalId" : "42513", "industryFunction" : { }, "structuredLocations" : [ { "country" : "United States", "continent" : "na", "workMode" : "onsite" } ], "locationText" : "United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Master's", "professionalSkills" : [ "Curriculum development", "Instructional design", "Behavior management" ], "hardSkillsList" : [ "IEP development", "Differentiated instruction", "Behavioral strategies" ], "hardSkills" : [ { "name" : "IEP development", "level" : "intermediate" }, { "name" : "Differentiated instruction", "level" : "intermediate" }, { "name" : "Behavioral strategies", "level" : "intermediate" } ], "majorSkills" : "Special education, IEP implementation, Student instruction", "majorSkillsList" : [ "Special education", "IEP implementation", "Student instruction" ], "coreResponsibilities" : "Plan student instruction, Lead student instruction, Facilitate student instruction, Provide student instruction, Follow student IEPs, Ensure curriculum instruction, Participate on pre-assessment teams, Diagnose student needs, Structure IEPs, Implement IEPs, Diagnose student learning, Structure daily expectations, Communicate instructional strategies, Report student data, Negotiate schedules, Communicate with stakeholders, Provide differentiated instruction, Control classroom behavior, Teach individual behavior, Adapt course content, Adjust reading levels, Discern learning styles, Build memory skills, Build study skills, Assist students academically, Assist students daily living, Assist students social skills, Present learning opportunities, Support regular teachers, Prepare events, Display reinforcement activities, Evaluate student progress, Plan assessments, Design subject-based reinforcement, Design grading system, Collect student data, Enter student data, Report student progress, Provide positive role model, Develop classroom structure, Teach classroom rules, Review classroom routines, Design classroom rules, Design systems for behavior, Prepare classroom physical condition, Maintain clean classroom, Maintain organized classroom, Keep daily records, Supervise paraprofessionals, Manage job duties", "teamCollaboration" : "Multi-disciplinary team; Regular education staff; Special education staff; Diverse population", "domainKnowledge" : "Special Education; Individual Education Program (IEP); Standards-based instruction", "domainList" : [ "special-education", "individual-education-program-iep", "standards-based-instruction" ], "domainSpecificKnowledge" : [ "Special Education", "Individual Education Program (IEP)", "Standards-based instruction" ], "toolProficiency" : [ "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "communicationSkills" : "Verbal communication; Written communication", "documentationSkills" : "Daily records", "specialRequirements" : "Limited travel, Lift students, Dress students, Position students", "qualificationsBasic" : "Valid Kansas teaching license, Master's Degree in Special Education, Special Education Waiver obtained", "qualificationsPreferred" : "Prior teaching experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Job Title: Mixed Abilities Teacher Position Function: The person filling this position plans, leads, facilitates, and provides instruction for maximum student learning in his/her least restrictive learning environment. This position follows each student’s standards-based Individual Education Program (IEP) to ensure appropriate curriculum-based instruction. Essential Performance Responsibilities: Participates, as appropriate, on pre-assessment teams to determine necessity for comprehensive student evaluation; initiates, schedules, and attends IEP meetings; works with multi-disciplinary team to diagnose need; structures/implements IEP for each student identified Defines, structures, and communicates daily expectations according to state standards and IEP including, but not limited to, course goals, objectives, learning methods, and activities Communicates with parents, regular education staff members, special education staff members, and other appropriate stakeholders on course instructional strategies and objectives, students’ grasp of material, outcomes and perspectives for applications of materials learned Receives and reports student progress; in-puts student data via computer; negotiates schedules and communicates with all pertinent participants (administration, parents, staff, students, etc.) Provides differentiated instruction based on the student’s individual level of functioning and preferred/necessary learning modalities Controls classroom and teaches individual behavior through classroom structure, routine, communication opportunities, and individualized behavior methods; adapts and adjusts course content and reading levels to specify skills to be taught; discerns learning styles and means of building memory and study skills; assists individual students in achieving academic, daily living, and social skills learning objectives by working with them individually and in small groups Presents various learning opportunities appropriate to each student’s IEP including, but not limited to, classroom structure, multi-media, assistive technology, alternative communication opportunities, support of regular classroom teachers, and other presentations and/or opportunities inside or outside Prepares and displays events and reinforcement activities which encourage participation Evaluates according to state standards and student IEPs Plans assessments for evaluation to include, but not limited to, various diagnostic techniques; standardized survey and criterion-referenced test; teacher-developed oral and written tests; student personal indices (effort, potential, interests, memory) Designs subject-based reinforcement to follow assessments and student’s learning objectives (computer, lab activities, working independently or on group projects, field/community reinforcement) Designs a grading system which encourages motivation and participation; collects and enters student data in computer from charts and observations; reports progress on a regular basis as required Provides a positive role model of appropriate and respectful interactions with students and staff Develops, teaches, and reviews clear and concise classroom structure, rules, routines, procedures, and expectations individualized to student need Designs classroom rules for student interaction (courtesy and respect for belongings, space, and ideas), self-control, working independently, and appropriately gaining the floor; designs systems for handling all the behavior (from simple infractions to severe behavior) Prepares physical condition of classroom to reflect subject matter to facilitate student learning and maintains a clean and organized classroom Keeps daily records on, but not limited to, student attendance, learning and social needs, assignments, assessments and discipline; supervises paraprofessionals Manages all job duties with the mobility, agility, dexterity, and focused observation necessary to adequately perform the essential duties as described above Additional Duties: Assists with additional duties as assigned by supervisor. Equipment: This position may require the ability to use SMART boards and iPads in addition to basic office equipment such as computers, copiers, scanners, and fax machine. Must always comply with USD 259’s guidelines for equipment use. Travel: Limited travel between schools and central offices may be required. Physical and Mental Demands: Good physical health and ability to implement behavioral strategies as well as to lift, dress, and position students as needed for self-care and safety. Knowledge, Skills, and Abilities: Ability to communicate both verbally and written in order to communicate with others inside and outside of the organization for the purpose of giving and obtaining information Ability to communicate effectively with a Supervisor when their discretion is needed Ability to perform as an effective team player Ability to plan, organize, make decisions and prioritize work to meet the daily demands of the building Exhibits a professional manner and a positive attitude Uses good judgment to make decisions on recurring assignments Displays a significant degree of professionalism and confidentiality Ability to conform to proper standards of professional dress and appearance Knowledge of company’s mission, purpose, goals and the role of every employee in achieving each of them Interrelations: Contact with personnel within the district and with customers and vendors Will be working under the direct supervision of the department supervisor in order to complete day to day tasks Will be working with a diverse population requiring the ability to handle all situations with tact and diplomacy Must understand and respond appropriately to customer needs and maintain a positive attitude with all customers and colleagues Expected to interact with all internal and external customers in a friendly, professional manner and provide quick, responsive customer service Employee Punctuality and Appearance: In order for schools to operate effectively, employees are expected to perform all assigned duties and work all scheduled hours during each designated workday, unless the employee has received approved leave Any deviation from assigned hours must have prior approval from the employee’s supervisor or building administrator All employees are required to report to work dressed in a manner that reflects a positive image of USD 259 and is appropriate for their position Qualification Profile: Valid Kansas teaching license required Master’s Degree in Special Education or enrolled in a Special Education Degree Program with Plan of Study on file with District and Special Education Waiver obtained Prior teaching experience preferred FLSA Status: Exempt", "summaryDescription" : "Mixed Abilities Teacher at Allison Traditional Magnet Middle School. Skills: Special education, IEP implementation, Student instruction. Plan student instruction. Lead student instruction", "createdAt" : "2026-06-14T01:49:33.480", "lastUpdated" : "2026-06-15T08:26:30.944", "ingestTimestamp" : "2026-06-14T01:49:33.480", "mongoId" : "6949b14570f0b99d588271bd", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 55000, "salaryAnnualMax" : 85000, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "IEP development", "Differentiated instruction", "Behavioral strategies", "Special education", "IEP implementation", "Student instruction", "Curriculum development", "Instructional design", "Behavior management", "Special Education", "Individual Education Program (IEP)", "Standards-based instruction", "Kansas teaching license", "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "skillCount" : 19, "jobCategory" : "education", "jobSubcategory" : "support", "seniorityLevel" : "Mid", "dataQualityScore" : 0.7777778, "_score" : 319.22095, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Education", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2c7f4e74d8ee00a0955131", "title" : "Electrical Engineer (RF/Signal Processing Engineer)", "company" : "Analytic Services Inc", "industry" : "Government", "salary" : { "min" : 145000.0, "max" : 205000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Senior Electrical Engineer in Reston, VA, adjusted for the government industry and company size." }, "location" : "Reston, Virginia, United States", "locations" : [ "Reston", "Virginia", "United States" ], "timestamp" : "2026-06-15T08:28:54.808", "fingerprint" : "8be341cadbc3dda1b2e59a2963bf3e52b71748fd30165922219a48598d48b1e0", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/analyticservicesinc/jobs/5255444008?gh_jid=5255444008", "externalId" : "5255444008", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Reston", "state" : "Virginia", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "38.9532820,-77.3464516" } ], "locationText" : "Reston, Virginia, United States", "technicalSkills" : "RF systems, Signal processing, Microelectronics, Sensors, Electronic technologies, Electromagnetic, Electro-optical, Infrared systems, Computer engineering, Electronic engineering, Optical engineering, Power engineering, Software development, Digital signal processing, Signal detection theory", "professionalSkills" : [ "Scientific research", "Engineering research", "Technical assessments", "System characterization", "Reverse engineering", "Limitation analyses", "Vulnerability analyses", "Analytical approaches", "Analytical methodologies" ], "hardSkillsList" : [ "Electrical engineering analysis", "Research", "Design", "Testing", "Assessment activities", "Electronic systems evaluation", "Subsystem evaluation", "Component evaluation", "Electrical engineering principles", "Computer engineering principles", "Electronic engineering principles", "Optical engineering principles", "Power engineering principles", "Technical analyses production", "Engineering assessments production", "Microelectronics analysis", "Reverse engineering support", "Technical exploitation support", "System characterization support", "RF systems knowledge", "Electromagnetic technologies knowledge", "Electro-optical systems knowledge", "Infrared systems knowledge", "Software development experience" ], "hardSkills" : [ { "name" : "Electrical engineering analysis", "level" : "intermediate" }, { "name" : "Research", "level" : "intermediate" }, { "name" : "Design", "level" : "intermediate" }, { "name" : "Testing", "level" : "intermediate" }, { "name" : "Assessment activities", "level" : "intermediate" }, { "name" : "Electronic systems evaluation", "level" : "intermediate" }, { "name" : "Subsystem evaluation", "level" : "intermediate" }, { "name" : "Component evaluation", "level" : "intermediate" }, { "name" : "Electrical engineering principles", "level" : "intermediate" }, { "name" : "Computer engineering principles", "level" : "intermediate" }, { "name" : "Electronic engineering principles", "level" : "intermediate" }, { "name" : "Optical engineering principles", "level" : "intermediate" }, { "name" : "Power engineering principles", "level" : "intermediate" }, { "name" : "Technical analyses production", "level" : "intermediate" }, { "name" : "Engineering assessments production", "level" : "intermediate" }, { "name" : "Microelectronics analysis", "level" : "intermediate" }, { "name" : "Reverse engineering support", "level" : "intermediate" }, { "name" : "Technical exploitation support", "level" : "intermediate" }, { "name" : "System characterization support", "level" : "intermediate" }, { "name" : "RF systems knowledge", "level" : "intermediate" }, { "name" : "Electromagnetic technologies knowledge", "level" : "intermediate" }, { "name" : "Electro-optical systems knowledge", "level" : "intermediate" }, { "name" : "Infrared systems knowledge", "level" : "intermediate" }, { "name" : "Software development experience", "level" : "intermediate" } ], "majorSkills" : "RF systems, Signal processing, Electronic systems, Technical analysis", "majorSkillsList" : [ "RF systems", "Signal processing", "Electronic systems", "Technical analysis" ], "coreResponsibilities" : "Support defense analytical requirements, Conduct reverse engineering analyses, Evaluate system performance, Analyze electronic hardware, Perform assessments of electromagnetic systems, Perform assessments of electro-optical systems, Perform assessments of infrared systems, Develop technical reports, Develop briefings, Develop analytical products, Support facility assessments, Support vulnerability analyses, Apply electrical engineering principles, Collaborate with multidisciplinary teams, Contribute to development of analytical approaches, Contribute to development of analytical methodologies", "teamCollaboration" : "Multidisciplinary teams", "domainKnowledge" : "Foreign electronic systems; Emerging technologies; National security; Radio frequency systems; Signal processing; Microelectronics; Sensors; Guidance and control systems; Advanced electronic technologies; Electromagnetic systems; Electro-optical systems; Infrared systems; Threat environments; Computer engineering; Electronic engineering; Optical engineering; Power engineering", "domainList" : [ "foreign-electronic-systems", "emerging-technologies", "national-security", "radio-frequency-systems", "signal-processing", "microelectronics", "sensors", "guidance-and-control-systems", "advanced-electronic-technologies", "electromagnetic-systems", "electro-optical-systems", "infrared-systems", "threat-environments", "computer-engineering", "electronic-engineering", "optical-engineering", "power-engineering" ], "domainSpecificKnowledge" : [ "Foreign electronic systems", "Emerging technologies", "National security", "Radio frequency systems", "Signal processing", "Microelectronics", "Sensors", "Guidance and control systems", "Advanced electronic technologies", "Electromagnetic systems", "Electro-optical systems", "Infrared systems", "Threat environments", "Computer engineering", "Electronic engineering", "Optical engineering", "Power engineering" ], "communicationSkills" : "Technical reports; Briefings; Analytical products", "documentationSkills" : "Technical reports; Analytical products", "innovationCreativity" : "Innovative analytical approaches; Innovative analytical methodologies", "problemSolvingSkills" : "Complex technical challenges", "specialRequirements" : "Active TS/SCI clearance, CI Polygraph", "qualificationsBasic" : "Active TS/SCI clearance, CI Polygraph, Bachelor's degree in Electrical Engineering, 8 years of experience, Evaluating electronic systems, Knowledge of electrical engineering principles, Producing technical analyses", "qualificationsPreferred" : "Analyzing complex foreign electronic systems, Microelectronics and advanced electronic hardware, Supporting reverse engineering, Knowledge of RF systems, Experience with software development, Digital signal processing, Signal detection theory", "remoteFriendly" : true, "rawDescription" : "Company Overview: ANSER enhances national and homeland security by strengthening public institutions. We provide thought leadership for complex issues through independent analysis, and we deliver practical, useful solutions. ANSER values collaboration, integrity, and initiative and we are client focused in all that we do. Because we were established for the purpose of public service and not for profit, we measure our success in the impact of our service. Position Overview: ANSER is seeking an Electrical Engineer (RF/Signal Processing Engineer) to support advanced defense analysis efforts through scientific and engineering research, technical assessments, and system characterization activities. In this role, you will provide subject matter expertise on complex foreign electronic systems and emerging technologies, helping to assess capabilities, vulnerabilities, and operational impacts that inform national security decision-making. You will contribute to multidisciplinary analyses involving radio frequency (RF) systems, signal processing, microelectronics, sensors, guidance and control systems, and other advanced electronic technologies. Day-to-Day Responsibilities: Support defense analytical requirements through scientific and engineering research, technical assessments, and limitation analyses. Conduct reverse engineering analyses and technical characterizations of foreign electronic systems, subsystems, facilities, and equipment. Evaluate system performance, capabilities, vulnerabilities, and operational effectiveness of complex electronic technologies. Analyze electronic hardware, circuits, microelectronics, sensors, and associated subsystems to support intelligence and defense missions. Perform assessments of electromagnetic, electro-optical (EO), and infrared (IR) systems and their applications within current and emerging threat environments. Develop technical reports, briefings, and analytical products that communicate findings to government stakeholders and mission partners. Support facility assessments and vulnerability analyses related to foreign electronic systems and infrastructure. Apply electrical engineering principles across computer, electronic, optical, and power engineering disciplines to solve complex technical challenges. Collaborate with multidisciplinary teams to evaluate current and projected foreign technologies and their potential operational impacts. Contribute to the development of innovative analytical approaches and methodologies for assessing advanced electronic systems. Required Qualifications: Active TS/SCI clearance with Counterintelligence (CI) Polygraph. Bachelor's degree in Electrical Engineering or a related engineering discipline. Minimum of 8 years of experience performing electrical engineering analysis, research, design, testing, or assessment activities. Experience evaluating electronic systems, subsystems, or components in support of defense, intelligence, research, or engineering missions. Knowledge of electrical engineering principles and one or more related disciplines, including computer, electronic, optical, or power engineering. Experience producing technical analyses, reports, or engineering assessments for government, defense, or intelligence customers. Preferred Qualifications: Experience analyzing complex foreign electronic systems, subsystems, facilities, or equipment. Experience with microelectronics and advanced electronic hardware technologies. Experience supporting reverse engineering, technical exploitation, or system characterization efforts. Knowledge of radio frequency (RF) systems, electromagnetic technologies, electro-optical systems, or infrared systems. Experience with software development, digital signal processing, and signal detection theory. Ability to communicate complex technical concepts effectively to both technical and non-technical audiences. In compliance with the Americans with Disabilities Act (ADA), if you have a disability and would like to request an accommodation in order to apply for a position with ANSER, please call 703-416-2000 or e-mail Recruiting@anser.org ANSER is proud to be an Equal Opportunity Employer. We seek individuals from a broad variety of backgrounds with varying levels of experience who have a desire to do meaningful work. We recruit, employ, train, compensate, and promote regardless of race, color, gender, religion, national origin, ancestry, disability, age, veteran status, sexual orientation, or any other characteristic protected by law.", "summaryDescription" : "Electrical Engineer (RF/Signal Processing Engineer) at Analytic Services Inc. Skills: RF systems, Signal processing, Electronic systems, Technical analysis. Support defense analytical requirements. Conduct reverse engineering analyses", "postedDate" : "2026-06-14T04:34:21.684", "createdAt" : "2026-06-14T04:34:21.684", "lastUpdated" : "2026-06-15T08:28:54.808", "ingestTimestamp" : "2026-06-14T04:34:21.684", "mongoId" : "6a2c7f4e74d8ee00a0955131", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 145000, "salaryAnnualMax" : 205000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Electrical engineering analysis", "Research", "Design", "Testing", "Assessment activities", "Electronic systems evaluation", "Subsystem evaluation", "Component evaluation", "Electrical engineering principles", "Computer engineering principles", "Electronic engineering principles", "Optical engineering principles", "Power engineering principles", "Technical analyses production", "Engineering assessments production", "Microelectronics analysis", "Reverse engineering support", "Technical exploitation support", "System characterization support", "RF systems knowledge", "Electromagnetic technologies knowledge", "Electro-optical systems knowledge", "Infrared systems knowledge", "Software development experience", "RF systems", "Signal processing", "Electronic systems", "Technical analysis", "Scientific research", "Engineering research", "Technical assessments", "System characterization", "Reverse engineering", "Limitation analyses", "Vulnerability analyses", "Analytical approaches", "Analytical methodologies", "Foreign electronic systems", "Emerging technologies", "National security", "Radio frequency systems", "Microelectronics", "Sensors", "Guidance and control systems", "Advanced electronic technologies", "Electromagnetic systems", "Electro-optical systems", "Infrared systems", "Threat environments", "Computer engineering", "Electronic engineering", "Optical engineering", "Power engineering" ], "skillCount" : 53, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.7777778, "_score" : 318.45706, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2c6c9f74d8ee00a091a2c6", "title" : "Intern, Asset Mix", "company" : "Connor, Clark & Lunn Private Capital Ltd. ", "industry" : "Banking", "salary" : { "min" : 43000.0, "max" : 52000.0, "currency" : "CAD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Vancouver, British Columbia, Canada", "locations" : [ "Vancouver", "British Columbia", "Canada" ], "timestamp" : "2026-06-16T05:28:08.273", "fingerprint" : "0885e4ba210346af31382a63830305d5653fe4228f5c85ba029e506e51061795", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/pcm/jobs/4246783009", "externalId" : "4246783009", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Vancouver", "state" : "British Columbia", "country" : "Canada", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "49.2608724,-123.1139520" } ], "locationText" : "Vancouver, British Columbia, Canada", "employmentType" : "INTERNSHIP", "minimumEducation" : "Bachelor's", "experienceMinYears" : 0, "experienceMaxYears" : 2, "experienceLevel" : "Entry", "remoteFriendly" : false, "rawDescription" : "CC&L Private Capital Ltd. is seeking an Asset Mix Intern to join our PC AMIX team for a minimum of 4-months (September – December 2026). We offer a challenging, fast-paced work environment with opportunities to learn and growth within CC&L Private Capital Ltd. and affiliated companies. You will be a member of a collaborative, highly detailed and analytical team, responsible for executing and monitoring asset mix trades, supporting the implementation of client investment strategies, and ensuring operational accuracy across a wide range of discretionary portfolios. You will work with Portfolio Managers, Wealth Advisors, and Trading teams to deliver investment execution What You Will Do Trade Execution & Oversight Execute asset mix and cash flow trades in accordance with client SIPs (Statement of Investment Policies) Support onboarding and restructuring of client portfolios Work with various teams on reconciliations, client cash flows, pooled fund trading, trade issues, and ad hoc requests Assist in reconciling flagged accounts and tracking transitions to enhanced strategies. Manage ad-hoc requests and projects Participate in internal process improvement initiatives and documentation updates What You Bring The Asset Mix Intern position is geared towards students in their third/fourth year of an undergraduate degree with a focus on Finance, Business Administration, Economics or a related field. Or individuals early in their career who are eager to learn and gain experience. We are seeking ambitious and detailed oriented people who are interested in making an impact at CC& L. In addition to the above, the successful candidate will have: At least one previous work term in a related role Knowledge and interest in capital markets, financial concepts, and account types (RRSPs, TFSAs, LIRAs, FHSA, Taxable accounts, etc.) Proficiency in MS Suite (Outlook, Word, MS Teams), and especially Excel Strong time management and organizational skills Excellent attention to detail and ability to manage time-sensitive tasks under pressure Key Competencies: Analytical thinking and problem-solving Clear and professional communication Team-oriented with a client-first mindset Adaptability in a fast-paced, high-volume environment The salary range for this position is $43,000 - 52,000 CAD annualized. The salary range provided reflects the base salary range for this position as required by legislation. Further questions may be directed to the HR team during the interview process.   For a closer look at how you can build your career with us, we invite you to explore cclgroup.com.  CC&L Financial Group is committed to creating a diverse and inclusive environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to gender, ethnicity, religion, sexual orientation or expression, disability, or age.  Your application will be reviewed by a member of the hiring team - AI is not used in the screening, assessment or selection of applications at this time.", "summaryDescription" : "Intern, Asset Mix at Connor, Clark & Lunn Private Capital Ltd.", "postedDate" : "2026-06-14T19:59:11.400", "createdAt" : "2026-06-14T19:59:11.400", "lastUpdated" : "2026-06-16T05:28:08.273", "ingestTimestamp" : "2026-06-14T19:59:11.400", "mongoId" : "6a2c6c9f74d8ee00a091a2c6", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "30k-50k", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "finance", "jobSubcategory" : "accounting", "seniorityLevel" : "Entry", "dataQualityScore" : 0.8888889, "_score" : 317.01642, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Financial Services", "llmIndustryConfidence" : 0.95 }, { "id" : "69dde4492beec4dd3d9a3352", "title" : "Signal Timing Technician (Transportation Specialist) III, IV, or V: Traffic Signal Crew (Austin District)", "company" : "TxDOT", "industry" : "Government", "salary" : { "min" : 54278.0, "max" : 106634.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "UST-Texas-Austin-Austin District Headquarters", "locations" : [ "UST-Texas-Austin-Austin District Headquarters", "Yearly", "Nonexempt,
Austin District Headquarters (14DISTHQ)
7901 NORTH IH 35
Austin, 78753

, Austin District Headquarters" ], "timestamp" : "2026-06-15T09:00:34.571", "fingerprint" : "13c2034288a488148e7e9fb650a1a70a95ea7ac7404a77ffd640dfb4580f6de5", "source" : "taleo", "language" : "en", "applyUrl" : "https://fa009.taleo.net/careersection/ex/jobdetail.ftl?job=43166", "externalId" : "43166", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Austin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.2711286,-97.7436995" } ], "locationText" : "Austin, Texas, United States", "employmentType" : "FULL_TIME", "professionalSkills" : [ "Process management", "Cross-functional coordination", "Vendor management", "Stakeholder management", "Resource planning" ], "hardSkillsList" : [ "Traffic operations", "Highway maintenance", "Facility maintenance" ], "hardSkills" : [ { "name" : "Traffic operations", "level" : "intermediate" }, { "name" : "Highway maintenance", "level" : "intermediate" }, { "name" : "Facility maintenance", "level" : "intermediate" } ], "majorSkills" : "Transportation programs, Traffic signal systems", "majorSkillsList" : [ "Transportation programs", "Traffic signal systems" ], "coreResponsibilities" : "Provide technical expertise, Coordinate transportation programs, Oversee construction projects, Manage transportation systems, Maintain highways and facilities, Interpret guidelines and regulations, Interpret laws and policies, Interpret procedures", "teamCollaboration" : "Governmental officials; Consultants; Contractors; Private entities", "projectManagementSkills" : [ "Project planning", "Project oversight" ], "domainKnowledge" : "Transportation systems; Traffic operations; Highway maintenance", "domainList" : [ "transportation-systems", "traffic-operations", "highway-maintenance" ], "domainSpecificKnowledge" : [ "Transportation systems", "Traffic operations", "Highway maintenance" ], "qualificationsBasic" : "Technical expertise and coordination, Project planning and oversight, Development and interpretation of guidelines, Contact with governmental officials, Contact with consultants, Contact with contractors, Contact with private entities, Establish work plans and priorities, Virtually self-supervising, Direct accountability for work products", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "All Roads Lead to TxDOT! TxDOT's Austin District is looking for a Signal Timing Technician III, IV, OR V for the Traffic Signal Crew based at our Austin District Headquarters . This position provides technical expertise and coordination for transportation programs involving multiple design and advanced building construction projects, construction of transportation systems, traffic operations, and maintenance of highways and facilities. Assists with project planning and oversight, and the development and interpretation of guidelines, regulations, laws, policies, and procedures for the area of responsibility. Work requires contact with governmental officials, consultants, contractors, and private entities. Employees at this level establish their own work plans and priorities to meet established objectives, are virtually self-supervising, and assume direct accountability for work products, with issues rarely referred to the supervisor and typically handled at the time of occurrence. This position is for ONE Signal Timing Technician III, IV, or V. The Texas Department of Transportation reserves the sole right in determining the level of position based on the applicant's work experience, skill level, and all other appropriate factors, and based on business needs. Salary Plan/Grade: Signal Timing Technician III: B21:($54,278 - $87,046/yearly) Signal Timing Technician IV: B22:($57,614 - $93,138/yearly) Signal Timing Technician V: B24:($65,104- $106,634/yearly) 54,278.00 106,634.00", "summaryDescription" : "Signal Timing Technician (Transportation Specialist) III, IV, or V: Traffic Signal Crew (Austin District) at TxDOT. Skills: Transportation programs, Traffic signal systems. Provide technical expertise. Coordinate transportation programs", "createdAt" : "2026-06-14T02:06:24.761", "lastUpdated" : "2026-06-15T09:00:34.571", "ingestTimestamp" : "2026-06-14T02:06:24.761", "mongoId" : "69dde4492beec4dd3d9a3352", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 54278, "salaryAnnualMax" : 106634, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "Traffic operations", "Highway maintenance", "Facility maintenance", "Transportation programs", "Traffic signal systems", "Process management", "Cross-functional coordination", "Vendor management", "Stakeholder management", "Resource planning", "Project planning", "Project oversight", "Transportation systems" ], "skillCount" : 13, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Mid", "dataQualityScore" : 0.7777778, "_score" : 316.47534, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.92 }, { "id" : "69ce99f02beec4dd3d786090", "title" : "Mixed Abilities-Elem - Mixed Abilties Teacher (2026-2027 School Year)", "industry" : "Education", "salary" : { "min" : 55000.0, "max" : 75000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "The estimation is based on the market baseline for a mid-seniority Special Education Teacher in the United States, adjusted for the education industry." }, "location" : "Woodman Elementary School", "locations" : [ "Woodman Elementary School", "2500 Hiram", "67217" ], "certifications" : [ "Licensed in the State of Kansas", "Valid Kansas Driver's License" ], "timestamp" : "2026-06-16T03:21:02.901", "fingerprint" : "f4917ba050128d616fba954a40b811e4c0070120452b36c76ebf30cff0c565f0", "source" : "taleo", "language" : "en", "applyUrl" : "https://aa308.taleo.net/careersection/ex/jobdetail.ftl?job=95834", "externalId" : "95834", "industryFunction" : { }, "structuredLocations" : [ { "country" : "United States", "continent" : "na", "workMode" : "onsite" } ], "locationText" : "United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "professionalSkills" : [ "Curriculum-based instruction", "Behavioral strategies", "Instructional strategies" ], "hardSkillsList" : [ "IEP development", "Differentiated instruction", "Behavior management", "Record keeping", "Student assessment" ], "hardSkills" : [ { "name" : "IEP development", "level" : "intermediate" }, { "name" : "Differentiated instruction", "level" : "intermediate" }, { "name" : "Behavior management", "level" : "intermediate" }, { "name" : "Record keeping", "level" : "intermediate" }, { "name" : "Student assessment", "level" : "intermediate" } ], "majorSkills" : "Special Education, IEP implementation, Student instruction", "majorSkillsList" : [ "Special Education", "IEP implementation", "Student instruction" ], "coreResponsibilities" : "Plan instruction for student learning, Provide curriculum-based instruction, Follow student IEPs, Participate on pre-assessment teams, Determine need for student evaluation, Initiate student evaluations, Schedule student evaluations, Attend IEP meetings, Work with multi-disciplinary team, Diagnose student needs, Structure IEP for each student, Implement IEP for each student, Define daily expectations, Structure daily expectations, Communicate daily expectations, Communicate with parents, Communicate with staff, Communicate with stakeholders, Report student data, Negotiate schedules, Provide differentiated instruction, Adapt course content, Adjust reading levels, Discern learning styles, Assist students with learning objectives, Work with students individually, Work with students in small groups, Present learning opportunities, Support regular classroom teachers, Prepare events, Display reinforcement activities, Evaluate according to state standards, Plan assessments, Design subject-based reinforcement, Design grading system, Collect student data, Enter student data, Report student progress, Provide positive role model, Develop classroom structure, Teach classroom rules, Review classroom procedures, Design classroom rules, Design systems for handling behavior, Prepare physical classroom condition, Maintain clean classroom, Maintain organized classroom, Keep daily records, Supervise paraprofessionals, Manage job duties, Participate in teacher committee work, Attend teacher lunch activities, Prepare students for travel, Escort students to classes, Supervise bus loading, Supervise bus unloading, Attend school programs, Attend school events, Perform additional duties", "teamCollaboration" : "Multi-disciplinary team; Regular education staff; Special education staff; Other stakeholders; Teacher committee work", "domainKnowledge" : "Special Education; Individualized Education Program (IEP); State standards", "domainList" : [ "special-education", "individualized-education-program-iep", "state-standards" ], "domainSpecificKnowledge" : [ "Special Education", "Individualized Education Program (IEP)", "State standards" ], "toolProficiency" : [ "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "communicationSkills" : "Communicate with parents; Communicate with staff; Communicate with stakeholders; Communicate with supervisor", "documentationSkills" : "Keep daily records", "problemSolvingSkills" : "Diagnose student needs; Handle all situations", "specialRequirements" : "Lift students, Dress students, Position students, Work outdoors, Mobility, Agility, Dexterity, Focused observation", "qualificationsBasic" : "Bachelor of Arts or Science in Education, Special Education emphasis, Licensed in Kansas, Functional Special Education/Low Incidence Level - K-6, Valid Kansas Driver's License", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Job Title: Mixed Abilities-Elementary Position Function: The person filling this position plans, leads, facilitates, and provides instruction for maximum student learning in his/her least restrictive learning environment. This position follows each student's standards-based Individual Education Program (IEP) to ensure appropriate curriculum-based instruction. Essential Performance Responsibilities: Plans according to state standards and student IEPS Participates, as appropriate, on pre-assessment teams to determine necessity for comprehensive student evaluation, initiates, schedules, and attends IEP meetings; works with multi-disciplinary team to diagnose need; structures/implements IEP for each student identified Defines, structures, and communicates daily expectations according to state standards and IEP including but not limited to, course goals, objectives, learning methods, and activities Communicates with parents, regular education staff members, special education staff members, and other appropriate stakeholders on course instructional strategies and objectives, students' grasp of material, outcomes and perspectives for applications of materials learned Receives and reports student progress; in-puts student data via computer; negotiates schedules and communicates with all pertinent participants (administration, parents, staff, students, etc.) Provides differentiated instruction based on the student's individual level of functioning and preferred/necessary learning modalities Controls classroom and teaches individual behavior through classroom structure, routine, communication opportunities, and individualized behavior methods; adapts and adjusts course content and reading levels to specify skills to be taught; discerns learning styles and means of building memory and study skills; assists individual students in achieving academic, daily living, and social skills learning objectives by working with them individually and in small groups Presents various learning opportunities appropriate to each student's IEP including, but not limited to, classroom structure, multi-media, assistive technology, alternative communication opportunities, support of regular classroom teachers, and other presentations and/or opportunities inside or outside Prepares and displays events and reinforcement activities which encourage participation Evaluates according to state standards and student IEPs Plans assessments for evaluation to include, but not limited to, various diagnostic techniques; standardized survey and criterion-referenced test; teacher-developed oral and written tests; student personal indices (effort, potential, interests, memory) Designs subject-based reinforcement to follow assessments and student's learning objectives (computer lab activities, working independently or on group projects, field/community reinforcement) Designs a grading system which encourages motivation and participation; collects and enters student data in computer from charts and observations; reports progress on a regular basis as required Provides a positive role model of appropriate and respectful interactions with students and staff Develops, teaches, and reviews clear and concise classroom structure, rules, routines, procedures, and expectations individualized to student need. Designs classroom rules for student interaction (courtesy and respect for belongings, space, and ideas), self-control, working independently, and appropriately gaining the floor; designs systems for handling all the behavior (from simple infractions to severe behavior) Prepares physical condition of classroom to reflect subject matter to facilitate student learning and maintains a clean and organized classroom Keeps daily records on, but not limited to, student attendance, learning and social needs, assignments, assessments and discipline; supervises paraprofessionals. Manages all job duties with the mobility, agility, dexterity, and focused observation necessary to adequately perform the essential duties as described above Participates in teacher committee work and attends teacher meetings; daily lunch activities as assigned; prepares and/or escorts students to travel to special classes as required; supervises bus loading and unloading as required; attends programs and events related to school Additional Duties: Additional duties as assigned by supervisor Equipment: This position requires the ability to use SMART boards and iPads in addition to basic office equipment such as computers, copiers, scanners, and fax machine Travel: Limited travel may be required Physical and Mental Demands: Good physical health and ability to implement behavioral strategies as well as to lift, dress, and position students as needed for self-care and safety Works in standard office and school building environments Ability to work outdoors during outdoor student activities Additional demands upon request of Principal, Superintendent Must be able to respond rapidly in emergency situations Knowledge, Skills, and Abilities: Ability to communicate both verbally and written in order to communicate with others inside and outside of the organization for the purpose of giving and obtaining information Ability to communicate effectively with a Supervisor when their discretion is needed Ability to perform as an effective team player Ability to plan, organize, make decisions and prioritize work to meet the daily demands of the building Exhibit a professional manner and a positive attitude Use good judgment to make decisions on recurring assignments Display a significant degree of professionalism and confidentiality Ability to conform to proper standards of professional dress and appearance Knowledge of company's mission, purpose, goals and the role of every employee in achieving each of them Interrelations: Contact with personnel within the district and with customers and vendors Will be working under the direct supervision of the department supervisor in order to complete day to day tasks Will be working with a diverse population requiring the ability to handle all situations with tact and diplomacy Must understand and respond appropriately to customer needs and maintain a positive attitude with all customers and colleagues Expected to interact with all internal and external customers in a friendly, professional manner and provide quick, responsive customer service Employee Punctuality and Appearance: In order for schools to operate effectively, employees are expected to perform all assigned duties and work all scheduled hours during each designated workday, unless the employee has received approved leave Any deviation from assigned hours must have prior approval from the employee's supervisor or building administrator All employees are required to report to work dressed in a manner that reflects a positive image of USD 259 and is appropriate for their position Qualification Profile: Bachelor of Arts or Science in Education with an emphasis on Special Education Licensed in the State of Kansas to teach at the Functional Special Education/Low Incidence Level - K-6 level required Valid Kansas Driver's License required FLSA Status: Exempt", "summaryDescription" : "Mixed Abilities-Elem - Mixed Abilties Teacher (2026-2027 School Year). Skills: Special Education, IEP implementation, Student instruction. Plan instruction for student learning. Provide curriculum-based instruction", "createdAt" : "2026-06-14T18:50:14.027", "lastUpdated" : "2026-06-16T03:21:02.901", "ingestTimestamp" : "2026-06-14T18:50:14.027", "mongoId" : "69ce99f02beec4dd3d786090", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 55000, "salaryAnnualMax" : 75000, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "IEP development", "Differentiated instruction", "Behavior management", "Record keeping", "Student assessment", "Special Education", "IEP implementation", "Student instruction", "Curriculum-based instruction", "Behavioral strategies", "Instructional strategies", "Individualized Education Program (IEP)", "State standards", "Licensed in the State of Kansas", "Valid Kansas Driver's License", "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "skillCount" : 21, "jobCategory" : "education", "jobSubcategory" : "support", "seniorityLevel" : "Mid", "dataQualityScore" : 0.6666667, "_score" : 314.84308, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Education", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2c711274d8ee00a092d65c", "title" : "Staff/Senior QPU Layout Engineer", "company" : "Quantum Motion", "salary" : { "min" : 110000.0, "max" : 150000.0, "currency" : "GBP", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for a Lead Staff/Senior QPU Layout Engineer in London, United Kingdom, adjusted for seniority and industry." }, "location" : "London, GB", "locations" : [ "London", "GB" ], "timestamp" : "2026-06-16T02:37:11.824", "fingerprint" : "846530b1771480ad32f1aab495d1c87f471ee177bf68e8550eb0ed645673e25a", "source" : "personio", "language" : "en", "applyUrl" : "https://quantummotion.jobs.personio.de/job/2627177", "externalId" : "2627177", "industryFunction" : { }, "structuredLocations" : [ { "city" : "London", "country" : "United Kingdom", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "51.5074456,-0.1277653" } ], "locationText" : "London, United Kingdom", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "rawDescription" : "About The Role and Team As a Staff/Senior QPU Layout Engineer, you will drive the physical implementation and verification for a cutting-edge quantum processor platform. You’ll be a go-to expert for full-chip and block-level layouts, ensuring designs are reliable, manufacturable, and ready for tapeout. You will be hands-on with layout while also contributing to the transition from research prototypes to production using industry-standard semiconductor tools and processes.You should enjoy solving problems with solutions flexible to changing rules while maintaining engineering discipline. The role involves collaborating closely with experimentalists, device modellers, and designers, bridging research and industry-standard approaches. It is not a conventional IC layout role: our process is bespoke and evolving, requiring flexibility and strong problem-solving. However, it’s grounded in industrial tools and practices and thus best suited to those with a strong industry foundation. Our Team Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times in 2021 and 2022, and our technology breakthroughs have been featured in The Telegraph, BBC and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors, and we have recently closed our Series C funding of $160 million. We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology. Our team of 100+ is based across London, Oxford, San Sebastián and Sydney, with our primary hub in Islington (London). Functions of the Role Implement block-level and chip-level physical layouts for spin qubits in SiMOS quantum dots from concept through integration and tapeout using standard EDA tools. Drive layout work to completion using industry best practices to ensure manufacturability and scalability. Deliver layouts that meet agreed physical verification and sign-off criteria, and own tapeout readiness. Interpret EM analysis, adjusting layouts to meet reliability and integration goals. Create or adapt minimal schematics or netlists to support LVS and verification flows. Contribute to the definition and maintenance of PDKs, layout methodologies, conventions, and abstractions. Lead design reviews, tapeout planning, and technical documentation. Coach or manage layout engineers as the team grows. Collaborate closely with interdisciplinary teams, translating research intent into manufacturable layouts. Experience - Essentials Masters in Engineering, Physics, or related field, or equivalent professional experience. 6+ years leading chip layouts through tapeout in research-driven or novel technology environments. Strong proficiency with Cadence Virtuoso for full-chip and block-level layout and verification flows. Strong understanding of layout verification (DRC/LVS/ERC) using Calibre or equivalent. Experience interpreting EM simulation results to optimise layout for signal integrity and reliability. Proven ability to execute layouts evolving process nodes where formal design rules are incomplete and engineering judgment drives signoff decisions. Track record of effective cross-functional collaboration across disciplines and domains. Experience - Desirable Experience with quantum devices, CMOS process integration, and/or 3D integration. Experience developing PDKs, rule decks, or working closely with EDA teams. Scripting or automation experience (SKILL, Python, or similar). Experience managing a small team of layout engineers. Benefits Be part of a creative, world-leading team Competitive salary and share options scheme Contributory pension scheme Group private medical insurance scheme Life Assurance EEO Statement Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment or any other protected characteristics covered by the Equality Act 2010.", "summaryDescription" : "Staff/Senior QPU Layout Engineer at Quantum Motion", "createdAt" : "2026-06-14T20:27:32.728", "lastUpdated" : "2026-06-16T02:37:11.824", "ingestTimestamp" : "2026-06-14T20:27:32.728", "mongoId" : "6a2c711274d8ee00a092d65c", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "100k-150k", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 0.7777778, "_score" : 307.49585, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "69fae0334c40e2acd183027a", "title" : "Sr. Staff Layout Engineer", "company" : "Renesas Electronics", "industry" : "Semiconductors", "location" : "Toyosu, JP", "locations" : [ "Toyosu", "JP" ], "timestamp" : "2026-05-06T09:15:30.526", "fingerprint" : "800a8a57f12ec2c471d1e34793074fae9580df781d7eab69385739090f492f0e", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/RenesasElectronics/744000121670427-sr-staff-layout-engineer", "externalId" : "744000121670427", "industryFunction" : { }, "structuredLocations" : [ { "city" : "toyosu", "state" : "tokyo", "country" : "japan", "continent" : "as", "source" : "locations-index", "geo" : "35.65087,139.79163" } ], "locationText" : "toyosu, tokyo, japan", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "Virtuoso XL, Calibre DRC, LVS, PEX, VCAR, VSR, PVS, R3D", "professionalSkills" : [ "technical lead on floor planning and layout of complex mixed signal circuits and systems", "lead layout projects", "support layout team members with guidance in layout best practice", "drive identification and implementation of improvements", "lead floor planning of all levels of layout work (chip, block and cell)", "support TPL from initial feasibility work through to tape out", "Champion state-of-the-art layout techniques for matching accuracy, parasitic reduction, yield optimization and ESD robustness", "Routing and verification (DRC, ERC, Antenna & LVS) of chip, block and cell level layout", "high quality and efficient layout reviews", "Monitor, report and present recommendations for progress against project plan, key risk and any issues that arise", "ensure effective communication and alignment on block and cell requirements", "act as a mentor for less experienced layout engineers" ], "hardSkillsList" : [ "floor planning", "layout of complex mixed signal circuits and systems", "layout best practice", "parasitic reduction", "yield optimization", "ESD robustness", "Routing", "verification", "DRC", "ERC", "Antenna", "LVS" ], "softSkillsList" : [ "Ability to work both independently and part of a team", "Ability to make good judgement in selecting method/technique for obtaining solutions" ], "hardSkills" : [ { "name" : "floor planning", "level" : "intermediate" }, { "name" : "layout of complex mixed signal circuits and systems", "level" : "intermediate" }, { "name" : "layout best practice", "level" : "intermediate" }, { "name" : "parasitic reduction", "level" : "intermediate" }, { "name" : "yield optimization", "level" : "intermediate" }, { "name" : "ESD robustness", "level" : "intermediate" }, { "name" : "Routing", "level" : "intermediate" }, { "name" : "verification", "level" : "intermediate" }, { "name" : "DRC", "level" : "intermediate" }, { "name" : "ERC", "level" : "intermediate" }, { "name" : "Antenna", "level" : "intermediate" }, { "name" : "LVS", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Ability to work both independently and part of a team" }, { "name" : "Ability to make good judgement in selecting method/technique for obtaining solutions" } ], "majorSkills" : "floor planning, layout of complex mixed signal circuits and systems, Routing and verification (DRC, ERC, Antenna & LVS)", "majorSkillsList" : [ "floor planning", "layout of complex mixed signal circuits and systems", "Routing and verification (DRC, ERC, Antenna & LVS)" ], "coreResponsibilities" : "take technical lead on floor planning and layout of complex mixed signal circuits and systems, lead layout projects as appropriate, support layout team members with guidance in layout best practice, drive identification and implementation of improvements, Lead floor planning of all levels of layout work (chip, block and cell) in collaboration with TPL and relevant designers, Work as lead layout engineer on a project, supporting TPL from initial feasibility work through to tape out, Champion state-of-the-art layout techniques for matching accuracy, parasitic reduction, yield optimization and ESD robustness in any project you are responsible for, Routing and verification (DRC, ERC, Antenna & LVS) of chip, block and cell level layout, Responsible for high quality and efficient layout reviews with TPL, Layout Manager and other key stakeholders, Monitor, report and present recommendations for progress against project plan, key risk and any issues that arise, Working closely in collaboration with colleagues in design and layout to ensure effective communication and alignment on block and cell requirements, Guide a large team of engineers whilst working as lead layout engineer and act as a mentor for less experienced layout engineers", "teamCollaboration" : "lead layout projects; support layout team members with guidance in layout best practice; drive identification and implementation of improvements; lead floor planning of all levels of layout work (chip, block and cell) in collaboration with TPL and relevant designers; support TPL from initial feasibility work through to tape out; Responsible for high quality and efficient layout reviews with TPL, Layout Manager and other key stakeholders; Working closely in collaboration with colleagues in design and layout to ensure effective communication and alignment on block and cell requirements; Guide a large team of engineers whilst working as lead layout engineer and act as a mentor for less experienced layout engineers", "projectManagementSkills" : [ "lead layout projects", "Monitor, report and present recommendations for progress against project plan, key risk and any issues that arise" ], "domainKnowledge" : "complex mixed signal circuits and systems", "domainList" : [ "complex-mixed-signal-circuits-and-systems" ], "domainSpecificKnowledge" : [ "complex mixed signal circuits and systems" ], "toolProficiency" : [ "Virtuoso XL", "Calibre DRC", "LVS", "PEX", "VCAR", "VSR", "PVS", "R3D" ], "communicationSkills" : "Responsible for high quality and efficient layout reviews with TPL, Layout Manager and other key stakeholders; Monitor, report and present recommendations for progress against project plan, key risk and any issues that arise; ensure effective communication and alignment on block and cell requirements", "continuousLearning" : "support layout team members with guidance in layout best practice; drive identification and implementation of improvements; act as a mentor for less experienced layout engineers", "innovationCreativity" : "Champion state-of-the-art layout techniques", "problemSolvingSkills" : "Ability to make good judgement in selecting method/technique for obtaining solutions", "outcomesObjectives" : "yield optimization; ESD robustness; deliver on-time under tight schedule", "qualificationsBasic" : "Typically 7-10 years experience, Demonstrate expertise in the required CAD tools (Virtuoso XL/Calibre DRC, LVS & PEX/VCAR/VSR/PVS/R3D), Strong competence with various tools and procedures, reaching specialist level, Ability to make good judgement in selecting method/technique for obtaining solutions, Ability to support and mentor less experienced team members", "qualificationsPreferred" : "Results-oriented and able to deliver on-time under tight schedule, Ability to work both independently and part of a team, Ability to make good judgement in selecting method/technique for obtaining solutions, Strong competence with various tools and procedures, reaching specialist level", "remoteFriendly" : false, "workSiteFlexibility" : "Hybrid: 2 days remote, 3 days in office", "rawDescription" : "・To take technical lead on floor planning and layout of complex mixed signal circuits and systems and lead layout projects as appropriate. You will be expected to support layout team members with guidance in layout best practice, drive identification and implementation of improvements. ・Lead floor planning of all levels of layout work (chip, block and cell) in collaboration with TPL and relevant designers. ・Work as lead layout engineer on a project, supporting TPL from initial feasibility work through to tape out. ・Champion state-of-the-art layout techniques for matching accuracy, parasitic reduction, yield optimization and ESD robustness in any project you are responsible for. ・Routing and verification (DRC, ERC, Antenna & LVS) of chip, block and cell level layout. ・Responsible for high quality and efficient layout reviews with TPL, Layout Manager and other key stakeholders. Monitor, report and present recommendations for progress against project plan, key risk and any issues that arise. ・Working closely in collaboration with colleagues in design and layout to ensure effective communication and alignment on block and cell requirements. ・Guide a large team of engineers whilst working as lead layout engineer and act as a mentor for less experienced layout engineers. ## Qualifications 【MUST】・Typically 7-10 years experience ・Demonstrate expertise in the required CAD tools (Virtuoso XL/Calibre DRC, LVS & PEX/VCAR/VSR/PVS/R3D) ・Strong competence with various tools and procedures, reaching specialist level ・Ability to make good judgement in selecting method/technique for obtaining solutions ・Ability to support and mentor less experienced team members 【Nice to Have】・Results-oriented and able to deliver on-time under tight schedule ・Ability to work both independently and part of a team ・Ability to make good judgement in selecting method/technique for obtaining solutions ・Strong competence with various tools and procedures, reaching specialist level ## Additional Information ルネサスは、「To Make Our Lives Easier 」（人々の暮らしを楽“ラク”にする）というPurposeの下、組み込み半導体ソリューションを提供します。高品質とシステムレベルノウハウを兼ね備えた組み込み半導体のリーダーとして、自動車、産業、インフラ・IoT分野向けに、ハイパフォーマンスコンピューティング、組み込みプロセッシング、アナログ＆コネクティビティ、そしてパワーを含めた幅広い製品ポートフォリオを軸とした、スケーラブルで包括的なソリューションを提供しています。ルネサスは、30か国以上で22,000 人を超える多様性あふれる従業員と共に、限界に挑戦しながら、デジタライゼーションを通じてユーザエクスペリエンスを充実化させ、新たなイノベーションの時代を切り開いていきます。そして世界中の人々やコミュニティの未来のために、持続可能で省エネ効果の高いソリューションの開発に全力で取り組み、「To Make Our Lives Easier 」を実現します。ルネサスで実現できること * キャリアをスタート、そしてキャリアアップ： 4つのプロダクトグループをはじめ、さまざまな部門において技術職として、また幅広いビジネスの経験を積むことができます。ハードウェア、ソフトウェアの専門知識を深めたり、新しいことにチャレンジしたりする機会があります。 * やりがいとインパクトのある仕事をする：革新的な製品とソリューションの開発に関わることにより、世界中のお客様のニーズに応えると同時に、人々の生活をより便利で安全かつ安心なものにすることに貢献できます。 * 「ウェルビーイング」に焦点を置いた環境で最大限に能力を発揮する：ルネサスでは、リモートワーク制度などによる柔軟な勤務体制づくり、また従業員リソースグループの積極的な活動をサポートするなど、インクルーシブな職場環境構築を目指しています。従業員を第一に考えたカルチャーとグローバルなサポート体制が、入社後すぐに活躍できる環境を提供します。自分の力で成功を掴み、キャリアを築く準備はできていますか？ルネサスで一緒に未来を形づくっていきましょう。当社では、ハイブリッド勤務モデルを採用しており、従業員は週に2日間リモートワークを行うことができます。同時に、残りの日はチームとしてオフィスに集まり、協働を強化しています。出社指定日は火曜日から木曜日で、イノベーション、コラボレーション、そして継続的な学習に取り組む日としています。", "summaryDescription" : "Sr. Staff Layout Engineer at Renesas Electronics. Skills: floor planning, layout of complex mixed signal circuits and systems, Routing and verification (DRC, ERC, Antenna & LVS). take technical lead on floor planning and layout of complex mixed signal circuits and systems. lead layout projects as appropriate", "postedDate" : "2026-04-20T01:59:28.000", "createdAt" : "2026-05-06T08:58:49.529", "lastUpdated" : "2026-05-06T09:15:30.526", "ingestTimestamp" : "2026-05-06T08:58:49.529", "mongoId" : "69fae0334c40e2acd183027a", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "hasSalary" : false, "allSkills" : [ "floor planning", "layout of complex mixed signal circuits and systems", "layout best practice", "parasitic reduction", "yield optimization", "ESD robustness", "Routing", "verification", "DRC", "ERC", "Antenna", "LVS", "Ability to work both independently and part of a team", "Ability to make good judgement in selecting method/technique for obtaining solutions", "Routing and verification (DRC, ERC, Antenna & LVS)", "technical lead on floor planning and layout of complex mixed signal circuits and systems", "lead layout projects", "support layout team members with guidance in layout best practice", "drive identification and implementation of improvements", "lead floor planning of all levels of layout work (chip, block and cell)", "support TPL from initial feasibility work through to tape out", "Champion state-of-the-art layout techniques for matching accuracy, parasitic reduction, yield optimization and ESD robustness", "Routing and verification (DRC, ERC, Antenna & LVS) of chip, block and cell level layout", "high quality and efficient layout reviews", "Monitor, report and present recommendations for progress against project plan, key risk and any issues that arise", "ensure effective communication and alignment on block and cell requirements", "act as a mentor for less experienced layout engineers", "complex mixed signal circuits and systems", "Virtuoso XL", "Calibre DRC", "PEX", "VCAR", "VSR", "PVS", "R3D" ], "skillCount" : 35, "jobCategory" : "operations", "jobSubcategory" : "manufacturing", "dataQualityScore" : 0.8888889, "_score" : 307.26288, "daysOld" : 16, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Tech / AI / Software", "llmIndustryConfidence" : 1.0 }, { "id" : "6a2c946d74d8ee00a098a699", "title" : "Traffic / ITS Signal Technician", "company" : "Olsson", "industry" : "Consulting", "salary" : { "min" : 65000.0, "max" : 95000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Traffic/ITS Signal Technician in Colorado Springs, USA, adjusted for industry and company size." }, "location" : "Colorado Springs", "locations" : [ "Colorado Springs" ], "certifications" : [ "IMSA Traffic Signal Level II", "IMSA Traffic Signal Level III" ], "timestamp" : "2026-06-15T07:55:05.907", "fingerprint" : "1a82620968f88c3bfa20ae98efc9da97cecdedce2aba61e70d2a4d3b2c02a138", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/olsson/jobs/5254919008", "externalId" : "5254919008", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Colorado Springs", "state" : "Colorado", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "38.8339578,-104.8253480" } ], "locationText" : "Colorado Springs, Colorado, United States", "employmentType" : "FULL_TIME", "technicalSkills" : "ITS technology, Fiber optic network", "professionalSkills" : [ "Application engineering", "Estimating" ], "hardSkillsList" : [ "Traffic signal operations", "Repair and maintenance", "Solid-state electronics", "Electrical power systems", "Traffic control procedures", "Signal timings" ], "hardSkills" : [ { "name" : "Traffic signal operations", "level" : "intermediate" }, { "name" : "Repair and maintenance", "level" : "intermediate" }, { "name" : "Solid-state electronics", "level" : "intermediate" }, { "name" : "Electrical power systems", "level" : "intermediate" }, { "name" : "Traffic control procedures", "level" : "intermediate" }, { "name" : "Signal timings", "level" : "intermediate" } ], "majorSkills" : "Traffic signal controllers, ITS technology", "majorSkillsList" : [ "Traffic signal controllers", "ITS technology" ], "coreResponsibilities" : "Handle technical questions, Provide field services, Troubleshoot traffic management systems, Provide traffic management solutions, Maintain ITS technology understanding, Oversee installation of cabinets, Oversee turn on of cabinets, Oversee maintenance of cabinets, Oversee testing of cabinets, Support field operations, Provide optimized systems, Represent company on-site, Make critical decisions, Assist with application engineering, Assist with estimating, Configure traffic signal controllers, Integrate devices, Develop strategies for signal timings, Modify traffic signal cabinets", "teamCollaboration" : "Collaborate with engineers; Collaborate with technicians", "domainKnowledge" : "Traffic signal equipment; Mechanical principles; Electrical principles; Electronic principles; Traffic signal systems; Traffic control device installation; Traffic control device repair", "domainList" : [ "traffic-signal-equipment", "mechanical-principles", "electrical-principles", "electronic-principles", "traffic-signal-systems", "traffic-control-device-installation", "traffic-control-device-repair" ], "domainSpecificKnowledge" : [ "Traffic signal equipment", "Mechanical principles", "Electrical principles", "Electronic principles", "Traffic signal systems", "Traffic control device installation", "Traffic control device repair" ], "toolProficiency" : [ "NEMA cabinets", "CALTRANS cabinets", "ATC cabinets" ], "problemSolvingSkills" : "Troubleshooting; Providing solutions", "specialRequirements" : "70% field work, Work in diverse weather, Lift and carry 50 lbs", "qualificationsBasic" : "5-10 years experience, Interpret design plans, Knowledge of MUTCD, Valid driver's license, Lift and carry 50 lbs, IMSA Traffic Signal Level II certification, Pass IMSA Level III within 6 months", "qualificationsPreferred" : "IMSA Traffic Signal Level III certification", "workSiteFlexibility" : "Flexible", "rawDescription" : "Company Description We are Olsson. We engineer and design solutions that improve the world around us. As a company, we promise to always be responsive, transparent, and focused on results – for our people, our clients, and our company. We’re a people-centric firm, so it’s no surprise our greatest asset is our people. The impact this creates is an environment that encourages our people to grow and be creative with their talents. This approach builds a culture that is uniquely Olsson. It allows us to grow our people as we grow our business. This, in turn, creates a lasting impact on the world around us. Job Description Olsson has an exciting opportunity for a Traffic/ITS Signal Technician to join our Traffic/Technology team! This role is ideal for a candidate eager to collaborate with and provide support for traffic engineers and technicians in executing services and project work in the field. Key Responsibilities Include: Handling technical questions from clients and team members, providing field services on across diverse projects. Your role will involve both troubleshooting and providing solutions that enhance our clients' traffic management systems. Maintaining a superior hands-on understanding of ITS technology. This involves overseeing the installation, turn on, maintenance, and testing of traffic signal cabinets. You will support field operations for integration projects, providing systems that are not only operational but also optimized for performance. Representing the company on-site, where you will be making critical decisions in real-time, and assisting with application engineering and estimating. Configuring traffic signal controllers for optimal performance, integrating various devices within NEMA, CALTRANS, and ATC cabinets. Your work will extend to developing strategies for signal timings, which are key in managing traffic flow efficiently. Modifying traffic signal cabinets according to pre-engineered designs or specific customer requirements. This task requires accuracy to provide a product that adheres to standards and fulfills the operational needs of the traffic system. This role involves spending an estimated 70% of the time working in the field, often in diverse weather conditions. Qualifications You are passionate about: Working collaboratively with others. Having ownership in the work you do. Using your talents to positively affect communities. You bring to the team: Strong communication skills. Ability to contribute and work well on a team. Familiarity with programming traffic signal controllers and analyzing signal operations. Knowledge of mechanical, electrical, and electronic basic principles as applied to traffic signal equipment. Practical knowledge of fiber optic network integration for signal systems. 5-10 years of experience in traffic signal operations including the repair and maintenance of solid-state electronics and electrical power systems. Ability to interpret design plans for quality assurance in traffic system installations. Knowledge of standard traffic control procedures/guidelines relating to traffic control device installation and/or repair as set forth in the MUTCD. Valid driver's license with a good driving history. Must be able to lift and carry up to 50 lbs. IMSA Traffic Signal Level II certification. Ability to pass IMSA Traffic Signal Level III certification within 6 months. #LI-DNP Actual compensation will vary based on factors such as experience, qualifications, geographic location, skills, education, and internal equity. Colorado Pay Range $55,907—$106,000 USD Additional Information Olsson specializes in engineering and design, client advisory services, planning, field services, and environmental. Improving the world has been our mindset from the very beginning, back when Olsson first opened for business in 1956. And it will be our mindset for years to come. As an Olsson employee, you will: Receive a competitive 401(k) match Be empowered to build your career with tailored development paths Have the possibility for flexible work arrangements Engage in work that has a positive impact on communities Participate in a wellness program promoting balanced lifestyles In addition, full-time employees will receive our traditional benefits package (health care, vision, dental, paid time off, etc.) and the opportunity to participate in a bonus system that rewards performance. Olsson is an Equal Opportunity Employer. We encourage qualified minority, female, veteran, and disabled candidates to apply and be considered for open positions. We do not discriminate against any applicant for employment or any employee because of race, color, religion, national origin, sex, sexual orientation, gender identity, gender, disability, age, military status, or other protected status. Olsson understands the importance of privacy and is committed to protecting job applicants’ personal information. Pursuant to the California Consumer Privacy Act, as amended by the California Privacy Rights Act (collectively, the “CCPA”), this notice explains Olsson’s practices regarding the collection, use, and disclosure of personal information for job applicants residing in California. Please read this Notice carefully to understand our privacy practices. For more information about the types of information we collect and how we use it in connection with your general access and use of our website, please review our general California Privacy Notice here.", "summaryDescription" : "Traffic / ITS Signal Technician at Olsson. Skills: Traffic signal controllers, ITS technology. Handle technical questions. Provide field services", "postedDate" : "2026-06-14T03:45:59.571", "createdAt" : "2026-06-14T03:45:59.571", "lastUpdated" : "2026-06-15T07:55:05.907", "ingestTimestamp" : "2026-06-14T03:45:59.571", "mongoId" : "6a2c946d74d8ee00a098a699", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 65000, "salaryAnnualMax" : 95000, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "Traffic signal operations", "Repair and maintenance", "Solid-state electronics", "Electrical power systems", "Traffic control procedures", "Signal timings", "Traffic signal controllers", "ITS technology", "Application engineering", "Estimating", "Traffic signal equipment", "Mechanical principles", "Electrical principles", "Electronic principles", "Traffic signal systems", "Traffic control device installation", "Traffic control device repair", "IMSA Traffic Signal Level II", "IMSA Traffic Signal Level III", "NEMA cabinets", "CALTRANS cabinets", "ATC cabinets" ], "skillCount" : 22, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.8888889, "_score" : 304.9472, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Engineering", "llmIndustryConfidence" : 0.95 }, { "id" : "69dde3f62beec4dd3d9a0be0", "title" : "Mixed Abilities-Elem - Mixed Abilities (2026-2027 School Year)", "industry" : "Education", "salary" : { "min" : 65000.0, "max" : 95000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Elementary Special Education Teacher in the United States, adjusted for the specific city and industry." }, "location" : "Colvin Elementary School", "locations" : [ "Colvin Elementary School", "2820 S. Roosevelt", "67210" ], "certifications" : [ "Licensed in the State of Kansas", "Valid Kansas Driver's License" ], "timestamp" : "2026-06-15T09:04:19.561", "fingerprint" : "dca8b8b5b1f307ead07a3806b05df1db9c83cb4d4efe0aa7b90a069f4f3edf84", "source" : "taleo", "language" : "en", "applyUrl" : "https://aa308.taleo.net/careersection/ex/jobdetail.ftl?job=96454", "externalId" : "96454", "industryFunction" : { }, "structuredLocations" : [ { "state" : "Kansas", "country" : "United States", "continent" : "na", "workMode" : "onsite" } ], "locationText" : "Kansas, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "professionalSkills" : [ "Curriculum development", "Instructional design", "Behavior management" ], "hardSkillsList" : [ "IEP development", "Standards-based instruction", "Differentiated instruction", "Behavioral strategies", "Classroom management", "Student assessment", "Grading system design", "Record keeping" ], "softSkillsList" : [ "Professional manner", "Good judgment", "Confidentiality" ], "hardSkills" : [ { "name" : "IEP development", "level" : "intermediate" }, { "name" : "Standards-based instruction", "level" : "intermediate" }, { "name" : "Differentiated instruction", "level" : "intermediate" }, { "name" : "Behavioral strategies", "level" : "intermediate" }, { "name" : "Classroom management", "level" : "intermediate" }, { "name" : "Student assessment", "level" : "intermediate" }, { "name" : "Grading system design", "level" : "intermediate" }, { "name" : "Record keeping", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Professional manner" }, { "name" : "Good judgment" }, { "name" : "Confidentiality" } ], "majorSkills" : "Special education, IEP implementation, Student instruction", "majorSkillsList" : [ "Special education", "IEP implementation", "Student instruction" ], "coreResponsibilities" : "Plan instruction, Facilitate student learning, Provide instruction, Follow student IEPs, Ensure curriculum-based instruction, Plan according to state standards, Participate on pre-assessment teams, Initiate student evaluations, Schedule student evaluations, Attend IEP meetings, Work with multi-disciplinary team, Diagnose student needs, Structure IEPs, Implement IEPs, Define daily expectations, Structure daily expectations, Communicate daily expectations, Communicate with parents, Communicate with staff, Communicate with stakeholders, Report student data, Negotiate schedules, Provide differentiated instruction, Adapt course content, Adjust reading levels, Discern learning styles, Build memory, Build study skills, Assist students, Achieve academic objectives, Achieve daily living objectives, Achieve social skills objectives, Work with students individually, Work with students in small groups, Present learning opportunities, Support regular classroom teachers, Prepare events, Display reinforcement activities, Encourage participation, Evaluate according to state standards, Evaluate according to student IEPs, Plan assessments, Design subject-based reinforcement, Design grading system, Collect student data, Enter student data, Report student progress, Provide positive role model, Teach classroom structure, Teach classroom rules, Teach classroom routines, Teach classroom procedures, Teach classroom expectations, Design classroom rules, Design systems for handling behavior, Prepare physical classroom condition, Maintain clean classroom, Maintain organized classroom, Keep daily records, Supervise paraprofessionals, Manage job duties, Perform essential duties, Participate in teacher committee work, Attend teacher daily lunch activities, Prepare students for travel, Escort students to special classes, Supervise bus loading, Supervise bus unloading, Attend school programs, Attend school events, Perform additional duties", "teamCollaboration" : "Multi-disciplinary team; Regular education staff; Special education staff; Other stakeholders; Teacher committee work; Internal personnel; External personnel", "domainKnowledge" : "Individual Education Program (IEP); State standards; Special Education; Low Incidence Level", "domainList" : [ "individual-education-program-iep", "state-standards", "special-education", "low-incidence-level" ], "domainSpecificKnowledge" : [ "Individual Education Program (IEP)", "State standards", "Special Education", "Low Incidence Level" ], "toolProficiency" : [ "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "communicationSkills" : "Communicate with parents; Communicate with staff; Communicate with stakeholders; Communicate with supervisor; Communicate effectively", "documentationSkills" : "Keep daily records", "problemSolvingSkills" : "Make decisions; Prioritize work", "specialRequirements" : "Mobility, Agility, Dexterity, Focused observation, Lift students, Dress students, Position students, Work outdoors, Handle situations with tact, Handle situations with diplomacy", "qualificationsBasic" : "Bachelor of Arts or Science in Education, Special Education emphasis, Licensed in Kansas, Functional Special Education/Low Incidence Level - K-6 level, Valid Kansas Driver's License", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Job Title: Mixed Abilities-Elementary Position Function: The person filling this position plans, leads, facilitates, and provides instruction for maximum student learning in his/her least restrictive learning environment. This position follows each student's standards-based Individual Education Program (IEP) to ensure appropriate curriculum-based instruction. Essential Performance Responsibilities: Plans according to state standards and student IEPS Participates, as appropriate, on pre-assessment teams to determine necessity for comprehensive student evaluation, initiates, schedules, and attends IEP meetings; works with multi-disciplinary team to diagnose need; structures/implements IEP for each student identified Defines, structures, and communicates daily expectations according to state standards and IEP including but not limited to, course goals, objectives, learning methods, and activities Communicates with parents, regular education staff members, special education staff members, and other appropriate stakeholders on course instructional strategies and objectives, students' grasp of material, outcomes and perspectives for applications of materials learned Receives and reports student progress; in-puts student data via computer; negotiates schedules and communicates with all pertinent participants (administration, parents, staff, students, etc.) Provides differentiated instruction based on the student's individual level of functioning and preferred/necessary learning modalities Controls classroom and teaches individual behavior through classroom structure, routine, communication opportunities, and individualized behavior methods; adapts and adjusts course content and reading levels to specify skills to be taught; discerns learning styles and means of building memory and study skills; assists individual students in achieving academic, daily living, and social skills learning objectives by working with them individually and in small groups Presents various learning opportunities appropriate to each student's IEP including, but not limited to, classroom structure, multi-media, assistive technology, alternative communication opportunities, support of regular classroom teachers, and other presentations and/or opportunities inside or outside Prepares and displays events and reinforcement activities which encourage participation Evaluates according to state standards and student IEPs Plans assessments for evaluation to include, but not limited to, various diagnostic techniques; standardized survey and criterion-referenced test; teacher-developed oral and written tests; student personal indices (effort, potential, interests, memory) Designs subject-based reinforcement to follow assessments and student's learning objectives (computer lab activities, working independently or on group projects, field/community reinforcement) Designs a grading system which encourages motivation and participation; collects and enters student data in computer from charts and observations; reports progress on a regular basis as required Provides a positive role model of appropriate and respectful interactions with students and staff Develops, teaches, and reviews clear and concise classroom structure, rules, routines, procedures, and expectations individualized to student need. Designs classroom rules for student interaction (courtesy and respect for belongings, space, and ideas), self-control, working independently, and appropriately gaining the floor; designs systems for handling all the behavior (from simple infractions to severe behavior) Prepares physical condition of classroom to reflect subject matter to facilitate student learning and maintains a clean and organized classroom Keeps daily records on, but not limited to, student attendance, learning and social needs, assignments, assessments and discipline; supervises paraprofessionals. Manages all job duties with the mobility, agility, dexterity, and focused observation necessary to adequately perform the essential duties as described above Participates in teacher committee work and attends teacher meetings; daily lunch activities as assigned; prepares and/or escorts students to travel to special classes as required; supervises bus loading and unloading as required; attends programs and events related to school Additional Duties: Additional duties as assigned by supervisor Equipment: This position requires the ability to use SMART boards and iPads in addition to basic office equipment such as computers, copiers, scanners, and fax machine Travel: Limited travel may be required Physical and Mental Demands: Good physical health and ability to implement behavioral strategies as well as to lift, dress, and position students as needed for self-care and safety Works in standard office and school building environments Ability to work outdoors during outdoor student activities Additional demands upon request of Principal, Superintendent Must be able to respond rapidly in emergency situations Knowledge, Skills, and Abilities: Ability to communicate both verbally and written in order to communicate with others inside and outside of the organization for the purpose of giving and obtaining information Ability to communicate effectively with a Supervisor when their discretion is needed Ability to perform as an effective team player Ability to plan, organize, make decisions and prioritize work to meet the daily demands of the building Exhibit a professional manner and a positive attitude Use good judgment to make decisions on recurring assignments Display a significant degree of professionalism and confidentiality Ability to conform to proper standards of professional dress and appearance Knowledge of company's mission, purpose, goals and the role of every employee in achieving each of them Interrelations: Contact with personnel within the district and with customers and vendors Will be working under the direct supervision of the department supervisor in order to complete day to day tasks Will be working with a diverse population requiring the ability to handle all situations with tact and diplomacy Must understand and respond appropriately to customer needs and maintain a positive attitude with all customers and colleagues Expected to interact with all internal and external customers in a friendly, professional manner and provide quick, responsive customer service Employee Punctuality and Appearance: In order for schools to operate effectively, employees are expected to perform all assigned duties and work all scheduled hours during each designated workday, unless the employee has received approved leave Any deviation from assigned hours must have prior approval from the employee's supervisor or building administrator All employees are required to report to work dressed in a manner that reflects a positive image of USD 259 and is appropriate for their position Qualification Profile: Bachelor of Arts or Science in Education with an emphasis on Special Education Licensed in the State of Kansas to teach at the Functional Special Education/Low Incidence Level - K-6 level required Valid Kansas Driver's License required FLSA Status: Exempt", "summaryDescription" : "Mixed Abilities-Elem - Mixed Abilities (2026-2027 School Year). Skills: Special education, IEP implementation, Student instruction. Plan instruction. Facilitate student learning", "createdAt" : "2026-06-14T07:24:56.276", "lastUpdated" : "2026-06-15T09:04:19.561", "ingestTimestamp" : "2026-06-14T07:24:56.276", "mongoId" : "69dde3f62beec4dd3d9a0be0", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 65000, "salaryAnnualMax" : 95000, "salaryBand" : "50k-75k", "hasSalary" : true, "allSkills" : [ "IEP development", "Standards-based instruction", "Differentiated instruction", "Behavioral strategies", "Classroom management", "Student assessment", "Grading system design", "Record keeping", "Professional manner", "Good judgment", "Confidentiality", "Special education", "IEP implementation", "Student instruction", "Curriculum development", "Instructional design", "Behavior management", "Individual Education Program (IEP)", "State standards", "Special Education", "Low Incidence Level", "Licensed in the State of Kansas", "Valid Kansas Driver's License", "SMART boards", "IPads", "Computers", "Copiers", "Scanners", "Fax machine" ], "skillCount" : 29, "jobCategory" : "education", "jobSubcategory" : "support", "seniorityLevel" : "Mid", "dataQualityScore" : 0.6666667, "_score" : 304.79266, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Education", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2c91e974d8ee00a098452d", "title" : "Senior Counsel (Complex Trial)", "company" : "Tyson & Mendes LLP", "industry" : "Legal", "salary" : { "min" : 150000.0, "max" : 200000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "New York, New York, United States", "locations" : [ "New York", "New York", "United States" ], "certifications" : [ "State Bar admission" ], "timestamp" : "2026-06-16T06:38:36.069", "fingerprint" : "4d80bdd77a82f087e3f4c4308d4b54d0b5b9d99e8769fc3e7bb492305aafe079", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/tysonmendesllp/jobs/5253963008", "externalId" : "5253963008", "industryFunction" : { }, "structuredLocations" : [ { "city" : "New York", "state" : "New York", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "40.7127281,-74.0060152" } ], "locationText" : "New York, New York, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "professionalSkills" : [ "Legal analysis", "Trial strategy", "Case management" ], "hardSkillsList" : [ "Complex litigation", "Pleading drafting", "Discovery management", "Motion practice", "Trial preparation", "Legal research" ], "hardSkills" : [ { "name" : "Complex litigation", "level" : "intermediate" }, { "name" : "Pleading drafting", "level" : "intermediate" }, { "name" : "Discovery management", "level" : "intermediate" }, { "name" : "Motion practice", "level" : "intermediate" }, { "name" : "Trial preparation", "level" : "intermediate" }, { "name" : "Legal research", "level" : "intermediate" } ], "majorSkills" : "Complex trial, Litigation, Legal strategy", "majorSkillsList" : [ "Complex trial", "Litigation", "Legal strategy" ], "coreResponsibilities" : "Manage complex litigation caseload, Draft pleadings and motions, Conduct discovery, Prepare for and attend trials, Analyze legal issues, Develop case strategy, Advise clients on legal matters, Negotiate settlements", "teamCollaboration" : "Work with partners; Collaborate with associates; Coordinate with support staff", "projectManagementSkills" : [ "Case management" ], "domainKnowledge" : "Civil procedure; Evidence rules; Torts; Contracts", "domainList" : [ "civil-procedure", "evidence-rules", "torts", "contracts" ], "domainSpecificKnowledge" : [ "Civil procedure", "Evidence rules", "Torts", "Contracts" ], "toolProficiency" : [ "Westlaw", "LexisNexis", "Microsoft Office Suite" ], "communicationSkills" : "Client communication; Courtroom advocacy; Legal writing", "documentationSkills" : "Legal document drafting", "problemSolvingSkills" : "Legal problem solving", "specialRequirements" : "Occasional travel", "outcomesObjectives" : "Achieve favorable case outcomes; Manage caseload efficiently", "qualificationsBasic" : "5+ years of complex trial experience, Admission to the State Bar", "qualificationsPreferred" : "Experience with e-discovery platforms, Knowledge of Medicare Secondary Payer Act", "remoteFriendly" : true, "workSiteFlexibility" : "Flexible", "rawDescription" : "Join Tyson & Mendes – Senior Counsel, Complex Trial Teams Where Insurance Defense Meets Innovation Please note: An active bar license in the State of New York is required. At Tyson & Mendes, we don’t just litigate—we lead. As a national force in insurance defense and trial advocacy, we’re known for our bold mission to stop Nuclear Verdicts® and our results-driven approach to high-exposure litigation. We are expanding our Complex Trial Teams and seeking accomplished Senior Counsel ready to make an impact in the courtroom and beyond. If you are an experienced trial lawyer who thrives on complex, high-stakes cases, values strategy over spectacle, and wants to be part of a team that is reshaping the future of civil defense—this is your opportunity. Why Tyson & Mendes? Lead with Impact – As Senior Counsel on our Complex Trial Team, you’ll take the reins on challenging, high-value matters with the support and trust of a firm built for trial success. Elite Training + Resources – From our Trial Academy to dedicated jury research and litigation support, we equip you with everything you need to succeed at the highest level. Stability + Momentum – Join a financially strong, nationally scaled firm with an agile, no-silos culture that prioritizes long-term success over short-term wins. Authentic Inclusion – At Tyson & Mendes, diverse perspectives and lived experiences are essential to our approach, our outcomes, and our culture. Results Matter, Not Where You Work – Office-based, hybrid, or remote—we focus on performance and outcomes, not location. Who You Are You are a trial-tested litigator with a defense-first mindset and the strategic acumen to lead complex cases from start to finish. You bring gravitas in the courtroom, confidence in depositions, and clarity in client communication. You think like a tactician, mentor with purpose, and uphold the highest standards of ethics and advocacy. With a deep understanding of high-exposure civil litigation—especially in areas like catastrophic injury, wrongful death, or construction defect—you are ready to take the next step in your leadership and litigation career. Make Your Move. Be part of something bigger—join Tyson & Mendes and help shape the future of insurance defense. Apply today. We’re ready for your best. Responsibilities Lead Complex Trials: Represent clients in high-exposure and complex insurance defense cases, including cases involving catastrophic injury, wrongful death, property damage, and professional liability Case Strategy and Planning: Develop and execute case strategies, including risk assessment, discovery, motion practice, and trial preparation Client Advisement: Work closely with clients, insurance carriers, and adjusters to provide clear legal advice, case assessments, and updates on case developments Litigation Management: Oversee all stages of litigation, including pleadings, discovery, depositions, pre-trial motions, and settlement negotiations Courtroom Representation: Serve as lead counsel in jury trials, bench trials, and mediations, presenting cases effectively and persuasively Team Leadership and Mentorship: Supervise and mentor junior attorneys, paralegals, and support staff, ensuring high-quality work and compliance with best practices Collaboration with Experts: Collaborate with expert witnesses, including medical, forensic, engineering, and economic experts, to strengthen case arguments Requirements Juris Doctor (JD) from an accredited law school Active license to practice law in New York and eligibility to practice in federal courts 8+ years of experience in insurance defense litigation with a strong focus on complex trial work Demonstrated success as lead trial counsel in multiple high-stakes cases Strong knowledge of civil procedure, tort law, insurance law, and trial strategies Proven ability to manage and prioritize a large, demanding caseload with limited oversight Exceptional oral advocacy, legal writing, and negotiation skills Strong client relationship management skills with an ability to communicate complex legal strategies effectively Background in catastrophic injury, construction defect, or professional liability cases preferred Experience with e-discovery tools and case management software Membership in local or national trial lawyer associations is a plus Compensation Package The base salary for this position ranges from $150,000-$200,000 annually, depending on experience and qualifications Attorneys are eligible for an annual billable hours bonus ranging from $10,000 and then aggregating with $7,500 for every additional tier Comprehensive benefits coverage offered, including plans available at zero employee cost (average annual employer contribution for health/vision/dental/life coverage is $700-$1,700) Employees benefit from a 401(k) program that includes a 100% match on the first 3% contributed and a 50% match on the following 4-5% Student loan repayment assistance or 529 college savings plan (full-time attorneys after one year with the firm) $100-$200/month Paid parental leave at base pay Employees receive a monthly technology reimbursement of $60 Benefits Employee Assistance Program through HealthAdvocate Comprehensive in-house training and leadership development opportunities Firm Provided CLE Programs and Paid Bar License Renewal Fees Flexible vacation policy for attorneys Defined pathway to partnership Internal diversity and inclusion programs, such as the Women’s Initiative and Young Professionals Initiative Firm-wide charitable giving program Numerous social and off-site events each year to enrich your relationships with your colleagues About Tyson & Mendes Click here to learn more about the Tyson & Mendes Office! (944) The Tyson & Mendes Office - YouTube We’re one of the fastest-growing civil defense firms in the country—known for breaking the mold of the traditional law firm. Our dynamic, diverse team of trial attorneys delivers exceptional results, from landmark cases like Howell v. Hamilton Meats to numerous defense verdicts across the nation. But we don’t stop at great legal work—we invest in our people. With specialized training in our proven defense methods, clear paths to leadership, and robust professional development, we empower attorneys to grow their careers, build their personal brands, and become leaders in the field. Follow along with the firm on Twitter and LinkedIn or visit www.tysonmendes.com. Equal Opportunity Employer Notice OK, now for the legal copy (we are a law firm, after all). It is Tyson & Mendes’ policy to ensure equal employment opportunity without discrimination or harassment on the basis of race, religion, color, sex (including pregnancy, gender identity, and sexual orientation), parental status, national origin, age, disability, family medical history or genetic information, political affiliation, military service, or other non-merit-based factors. By the way, if you read all of this, congratulations – we can already tell your attention to detail is exceptional. NOTICE TO APPLICANTS/EMPLOYEES OF TYSON & MENDES: Please take notice that the Firm collects certain information about you. For more information on the Firm’s policies, please refer to the document provided here. No recruiters/agencies #li-hybrid Pay Range $150,000—$200,000 USD", "summaryDescription" : "Senior Counsel (Complex Trial) at Tyson & Mendes LLP. Skills: Complex trial, Litigation, Legal strategy. Manage complex litigation caseload. Draft pleadings and motions", "postedDate" : "2026-06-14T21:33:01.842", "createdAt" : "2026-06-14T21:33:01.842", "lastUpdated" : "2026-06-16T06:38:36.069", "ingestTimestamp" : "2026-06-14T21:33:01.842", "mongoId" : "6a2c91e974d8ee00a098452d", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 150000, "salaryAnnualMax" : 200000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Complex litigation", "Pleading drafting", "Discovery management", "Motion practice", "Trial preparation", "Legal research", "Complex trial", "Litigation", "Legal strategy", "Legal analysis", "Trial strategy", "Case management", "Civil procedure", "Evidence rules", "Torts", "Contracts", "State Bar admission", "Westlaw", "LexisNexis", "Microsoft Office Suite" ], "skillCount" : 20, "jobCategory" : "operations", "jobSubcategory" : "legal", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 297.22476, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Legal", "llmIndustryConfidence" : 0.98 }, { "id" : "69faf87d4c40e2acd1870566", "title" : "Staff Analog IC Layout Engineer", "company" : "Elevate Semiconductor", "industry" : "Semiconductors", "salary" : { "min" : 120000.0, "max" : 180000.0, "currency" : "USD", "frequency" : "yearly" }, "location" : "San Diego, California, United States", "locations" : [ "San Diego, California, United States" ], "timestamp" : "2026-05-06T11:05:06.585", "fingerprint" : "9de417d77491d443befd496a0525e4ce3a0c4e8b9545d9b6a2b2ad9076670b1b", "source" : "workable", "language" : "en", "applyUrl" : "https://apply.workable.com/j/62FE3C35F7/apply", "externalId" : "62FE3C35F7", "industryFunction" : { }, "locationPoint" : "32.71571,-117.16472", "structuredLocations" : [ { "city" : "san diego", "state" : "california", "country" : "united states", "continent" : "na", "source" : "locations-index", "geo" : "32.71571,-117.16472" } ], "locationText" : "san diego, california, united states", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor’s degree in Electrical Engineering or a related field", "experienceMinYears" : 8, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "analog CMOS circuits, mixed-signal IC layout design, LVS, DRC, Cadence, Mentor Graphics, Tanner, SKILL, Calibre scripts", "professionalSkills" : [ "IC design lifecycle", "qualification lifecycle", "manufacturing lifecycle" ], "hardSkillsList" : [ "physical layout", "floorplanning", "placement", "layout verification", "LVS (Layout vs. Schematic)", "DRC (Design Rule Checking)" ], "softSkillsList" : [ "collaboration" ], "hardSkills" : [ { "name" : "physical layout", "level" : "intermediate" }, { "name" : "floorplanning", "level" : "intermediate" }, { "name" : "placement", "level" : "intermediate" }, { "name" : "layout verification", "level" : "intermediate" }, { "name" : "LVS (Layout vs. Schematic)", "level" : "intermediate" }, { "name" : "DRC (Design Rule Checking)", "level" : "intermediate" } ], "softSkills" : [ { "name" : "collaboration" } ], "majorSkills" : "physical layout of analog and mixed-signal integrated circuits, LVS and DRC verification", "majorSkillsList" : [ "physical layout of analog and mixed-signal integrated circuits", "LVS and DRC verification" ], "coreResponsibilities" : "physical layout activities from block-level to full-chip integration, Performing physical layout of analog and mixed-signal integrated circuits at the block and chip level, Conducting floorplanning and placement of circuit components to optimize area, performance, and power, Verifying layouts using industry-standard tools for LVS (Layout vs. Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules, Troubleshooting and resolving issues related to layout verification and manufacturing", "teamCollaboration" : "Collaborate with a cross-functional team to optimize silicon design; Collaborating closely with design engineers to understand circuit specifications and ensure layout accuracy; Working with cross-functional teams, including digital design and packaging, to optimize overall chip performance", "domainKnowledge" : "analog CMOS circuits; device physics fundamentals; high-voltage; mixed-signal solutions; 65nm CMOS to 100+V BCD; STI High voltage (100V+) BCD and LDMOS processes; mixed voltage (multiple supply rails, 6 or more) domains; high speed multi Gbps circuits; ultra-high accuracy and precision circuits; high resolution data converters; BiCMOS process technology", "domainList" : [ "analog-cmos-circuits", "device-physics-fundamentals", "high-voltage", "mixed-signal-solutions", "65nm-cmos-to-100-v-bcd", "sti-high-voltage-100v-bcd-and-ldmos-processes", "mixed-voltage-multiple-supply-rails", "6-or-more-domains", "high-speed-multi-gbps-circuits", "ultra-high-accuracy-and-precision-circuits", "high-resolution-data-converters", "bicmos-process-technology" ], "domainSpecificKnowledge" : [ "analog CMOS circuits", "device physics fundamentals", "high-voltage", "mixed-signal solutions", "65nm CMOS to 100+V BCD", "STI High voltage (100V+) BCD and LDMOS processes", "mixed voltage (multiple supply rails, 6 or more) domains", "high speed multi Gbps circuits", "ultra-high accuracy and precision circuits", "high resolution data converters", "BiCMOS process technology" ], "toolProficiency" : [ "Cadence", "Mentor Graphics", "Tanner", "SKILL", "Calibre scripts" ], "continuousLearning" : "opportunities for professional growth", "innovationCreativity" : "driving innovation; advancing the cutting edge of semiconductor innovation; deliver innovative and cost-effective solutions", "problemSolvingSkills" : "Troubleshooting and resolving issues related to layout verification and manufacturing", "qualificationsBasic" : "Bachelor’s degree in Electrical Engineering or a related field, Minimum of 8 years of professional experience in analog and mixed-signal IC layout design, knowledge of analog CMOS circuits and device physics fundamentals, Solid understanding of the IC design, qualification, and manufacturing lifecycle, Hands-on experience with industry-standard EDA tools for analog and mixed-signal design (e. g. , Cadence, Mentor Graphics, Tanner), Proficiency in performing LVS and DRC verification using Cadence or Mentor tools", "qualificationsPreferred" : "Layout experience with STI High voltage (100V+) BCD and LDMOS processes, Layout experience with mixed voltage (multiple supply rails, 6 or more) domains, Layout experience with high speed multi Gbps circuits., Layout experience in ultra-high accuracy and precision circuits., Layout experience with high resolution data converters., Layout experience with BiCMOS process technology., Programming and scripting ability a plus, particularly in SKILL and Calibre scripts", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Elevate Semiconductor is at the forefront of shaping the future of semiconductor technology, driving innovation to enable the next generation of testing. We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to-market and enhanced capabilities. Our diverse product portfolio includes standard, semi-custom, and custom SKUs, all engineered for longevity and compatibility across evolving technological advancements. By focusing on low-power, high-density designs, we aim to lower the cost of testing while exceeding expectations on every project. Join us in advancing the cutting edge of semiconductor innovation! _**The Position**_ We are seeking a highly skilled Senior Analog Layout Engineer to join our team in developing state-of-the-art integrated circuits (ICs). In this role, you will handle the physical layout and verification of highly complex, high-voltage, and mixed-signal solutions using advanced process technologies, ranging from 65nm CMOS to 100+V BCD. You will collaborate with a cross-functional team to optimize silicon design, leveraging mentorship and support from senior engineers to deliver innovative and cost-effective solutions. Must be able to work onsite in San Diego,C CA. _**Responsibilities**_ As the sole Layout Design Engineer in the organization, you will take full ownership of physical layout activities from block-level to full-chip integration. Your responsibilities will include: * Performing physical layout of analog and mixed-signal integrated circuits at the block and chip level * Conducting floorplanning and placement of circuit components to optimize area, performance, and power * Verifying layouts using industry-standard tools for LVS (Layout vs. Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules * Collaborating closely with design engineers to understand circuit specifications and ensure layout accuracy * Working with cross-functional teams, including digital design and packaging, to optimize overall chip performance * Troubleshooting and resolving issues related to layout verification and manufacturing **Requirements** * Bachelor’s degree in Electrical Engineering or a related field * Minimum of **8 years of professional experience** in analog and mixed-signal IC layout design * Strong knowledge of analog CMOS circuits and device physics fundamentals * Solid understanding of the IC design, qualification, and manufacturing lifecycle * Hands-on experience with industry-standard EDA tools for analog and mixed-signal design (e.g., Cadence, Mentor Graphics, Tanner) * Proficiency in performing LVS and DRC verification using Cadence or Mentor tools _**Preferences**_ * Layout experience with STI High voltage (100V+) BCD and LDMOS processes * Layout experience with mixed voltage (multiple supply rails, 6 or more) domains * Layout experience with high speed multi Gbps circuits. * Layout experience in ultra-high accuracy and precision circuits. * Layout experience with high resolution data converters. * Layout experience with BiCMOS process technology. * Programming and scripting ability a strong plus, particularly in SKILL and Calibre scripts **Why Join Us?** At Elevate Semiconductor, you’ll be part of a dynamic team working on innovative technologies that shape the future of the semiconductor industry. We offer competitive compensation, comprehensive benefits, and opportunities for professional growth in a collaborative environment. **Apply Today!** If you are passionate about digital design and eager to contribute to groundbreaking semiconductor solutions, we want to hear from you! **Benefits** * 100% Employer Paid Health Insurance (Medical, Dental, Vision) * Unlimited Paid Time Off * Performance Bonuses * Free Lunch Catered in by Local Restaurants * Private Equity Options * Retirement Plans * Sabbatical Program * Tuition Reimbursement * Volunteer Days * Relocation Assistance * Conference Attendance Support * Biweekly Phone Stipend * Employee Assistance Program The salary range for this role is $120,000-$180,000.00. Please note: While a salary range is provided, the final compensation will depend on your experience, skill set, and how well you're able to highlight your background throughout the interview process.", "summaryDescription" : "Staff Analog IC Layout Engineer at Elevate Semiconductor. Skills: physical layout of analog and mixed-signal integrated circuits, LVS and DRC verification. physical layout activities from block-level to full-chip integration. Performing physical layout of analog and mixed-signal integrated circuits at the block and chip level", "postedDate" : "2026-04-27T00:00:00.000", "createdAt" : "2026-05-06T11:02:15.322", "lastUpdated" : "2026-05-06T11:05:06.585", "ingestTimestamp" : "2026-05-06T11:02:15.322", "mongoId" : "69faf87d4c40e2acd1870566", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://apply.workable.com/j/62FE3C35F7", "salaryAnnualMin" : 120000, "salaryAnnualMax" : 180000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "physical layout", "floorplanning", "placement", "layout verification", "LVS (Layout vs. Schematic)", "DRC (Design Rule Checking)", "collaboration", "physical layout of analog and mixed-signal integrated circuits", "LVS and DRC verification", "IC design lifecycle", "qualification lifecycle", "manufacturing lifecycle", "analog CMOS circuits", "device physics fundamentals", "high-voltage", "mixed-signal solutions", "65nm CMOS to 100+V BCD", "STI High voltage (100V+) BCD and LDMOS processes", "mixed voltage (multiple supply rails, 6 or more) domains", "high speed multi Gbps circuits", "ultra-high accuracy and precision circuits", "high resolution data converters", "BiCMOS process technology", "Cadence", "Mentor Graphics", "Tanner", "SKILL", "Calibre scripts" ], "skillCount" : 28, "jobCategory" : "other", "jobSubcategory" : "semiconductors", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 295.98807, "daysOld" : 9, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Tech / AI / Software", "llmIndustryConfidence" : 1.0 }, { "id" : "6a25313d74d8ee00a0100084", "title" : "Staff Mixed-Signal Design Engineer", "company" : "Analog Devices", "industry" : "Semiconductor", "salary" : { "min" : 9.0, "max" : 9.0, "currency" : "USD", "frequency" : "yearly" }, "location" : "United Kingdom, Newbury", "locations" : [ "United Kingdom, Newbury" ], "timestamp" : "2026-06-09T06:03:39.434", "fingerprint" : "53c4dc266366ec9e95d49c3b92f73147091ae1e338ccf2d5fd742090f4ab8c32", "source" : "workday", "language" : "en", "applyUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/United-Kingdom-Newbury/Staff-Mixed-Signal-Design-Engineer_R260354", "externalId" : "R260354", "industryFunction" : { }, "locationPoint" : "51.40148,-1.32471", "structuredLocations" : [ { "city" : "Newbury", "country" : "United Kingdom", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "51.4020243,-1.3242212" } ], "locationText" : "Newbury, United Kingdom", "employmentType" : "FULL_TIME", "minimumEducation" : "Master's", "experienceMinYears" : 7, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Mixed-signal, ADC, DAC, SerDes PHY, FinFET", "professionalSkills" : [ "Technical leadership", "Design reviews", "Product development" ], "hardSkillsList" : [ "Transistor-level design", "Data converter architectures", "SerDes PHY architectures" ], "hardSkills" : [ { "name" : "Transistor-level design", "level" : "intermediate" }, { "name" : "Data converter architectures", "level" : "intermediate" }, { "name" : "SerDes PHY architectures", "level" : "intermediate" } ], "majorSkills" : "Mixed-signal design, Integrated circuits, SoC", "majorSkillsList" : [ "Mixed-signal design", "Integrated circuits", "SoC" ], "coreResponsibilities" : "Evaluate subsystem architectures, Design transistor-level circuits, Prepare design documents, Conduct design reviews, Guide circuit layout, Guide circuit evaluation, Guide circuit test", "teamCollaboration" : "Teamwork", "domainKnowledge" : "Data converter architectures; SerDes PHY architectures; Mixed-signal design fundamentals; Integrated circuit product development", "domainList" : [ "data-converter-architectures", "serdes-phy-architectures", "mixed-signal-design-fundamentals", "integrated-circuit-product-development" ], "domainSpecificKnowledge" : [ "Data converter architectures", "SerDes PHY architectures", "Mixed-signal design fundamentals", "Integrated circuit product development" ], "communicationSkills" : "Communication skills", "documentationSkills" : "Design documents", "innovationCreativity" : "Innovative circuits", "qualificationsBasic" : "MS Electrical Engineering, 7+ years mixed-signal IC development, Deep understanding of mixed-signal fundamentals, Solid understanding of IC product development, Successful experience developing challenging mixed-signal ICs", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "**About Analog Devices** Analog Devices, Inc. (NASDAQ: _[ADI](http://finance.yahoo.com/q?s=ADI)_ ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at _[www.analog.com](https://www.analog.com/)_ and on _[LinkedIn](https://www.linkedin.com/company/analog-devices/posts/?feedView=all)_ and _[Twitter (X)](https://x.com/adi_news)_. **Staff Mixed-Signal Design Engineer** **Job Duties and Responsibilities** As a Staff Mixed-Signal Design Engineer within the Advanced Cores Group (ACG) you will work on the development of ADC, DAC, and/or SerDes PHY subsystems for highly sophisticated mixed-signal system-on-chip (SoC) integrated circuit products using FinFET wafer technologies. The Advanced Cores Group develops innovative, state of the art, high-performance circuits as often shown by presentations at premier conferences and publications in premier journals. Your work will include: * Evaluating alternative mixed-signal subsystem implementation architectures. * Designing challenging transistor-level mixed-signal integrated circuits. * Preparing effective design documents and conduct effective design reviews. * Guiding mixed-signal integrated circuit layout. * Guiding mixed-signal integrated circuit evaluation and test. **Qualifications** * MS Electrical Engineering. * 7+ years of mixed-signal integrated circuit development experience. * Strong understanding of data converter architectures and specifications and/or deep understanding of SerDes PHY architectures and specifications * Deep understanding of mixed-signal design fundamentals, design tools, and methodologies. * Solid understanding of integrated circuit product development, including design, verification, evaluation, test, and qualification. * Successful experience developing challenging mixed-signal integrated circuits for commercial applications. * Strong technical leadership, teamwork, and communication skills. _For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process._ _Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group._ Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days", "summaryDescription" : "Staff Mixed-Signal Design Engineer at Analog Devices. Skills: Mixed-signal design, Integrated circuits, SoC. Evaluate subsystem architectures. Design transistor-level circuits", "postedDate" : "2026-05-14T11:56:08.800", "createdAt" : "2026-06-07T11:56:08.704", "lastUpdated" : "2026-06-09T06:03:39.434", "ingestTimestamp" : "2026-06-07T11:56:08.704", "mongoId" : "6a25313d74d8ee00a0100084", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/United-Kingdom-Newbury/Staff-Mixed-Signal-Design-Engineer_R260354", "salaryAnnualMin" : 18720, "salaryAnnualMax" : 18720, "salaryBand" : "<30k", "hasSalary" : true, "allSkills" : [ "Transistor-level design", "Data converter architectures", "SerDes PHY architectures", "Mixed-signal design", "Integrated circuits", "SoC", "Technical leadership", "Design reviews", "Product development", "Mixed-signal design fundamentals", "Integrated circuit product development" ], "skillCount" : 11, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 295.91968, "daysOld" : 25, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Semiconductor" }, { "id" : "6a2c91e974d8ee00a0984529", "title" : "Senior Counsel (Complex Trial)", "company" : "Tyson & Mendes LLP", "industry" : "Legal", "salary" : { "min" : 160000.0, "max" : 190000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Costa Mesa, California, United States", "locations" : [ "Costa Mesa", "California", "United States" ], "certifications" : [ "Admission to the State Bar" ], "timestamp" : "2026-06-16T05:50:15.234", "fingerprint" : "bfe263799df1be5e4fcb167d2fb4a067cb51102403abc9380646717e916e8f0b", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/tysonmendesllp/jobs/5253958008", "externalId" : "5253958008", "industryFunction" : { }, "structuredLocations" : [ { "city" : "San Diego", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "hybrid", "geo" : "32.7174202,-117.1627720" } ], "locationText" : "San Diego, California, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "professionalSkills" : [ "Trial advocacy", "Legal research", "Legal writing", "Case management", "Negotiation", "Pleading drafting", "Discovery management", "Motion practice", "Client counseling", "Deposition preparation", "Witness preparation" ], "hardSkillsList" : [ "Complex trial", "Commercial litigation", "Construction defect", "Employment litigation", "Premises liability", "Product liability", "Catastrophic injury", "Medical malpractice", "Trucking litigation", "Toxic tort", "Professional liability", "Business litigation", "Appeals", "Arbitration", "Mediation" ], "hardSkills" : [ { "name" : "Complex trial", "level" : "intermediate" }, { "name" : "Commercial litigation", "level" : "intermediate" }, { "name" : "Construction defect", "level" : "intermediate" }, { "name" : "Employment litigation", "level" : "intermediate" }, { "name" : "Premises liability", "level" : "intermediate" }, { "name" : "Product liability", "level" : "intermediate" }, { "name" : "Catastrophic injury", "level" : "intermediate" }, { "name" : "Medical malpractice", "level" : "intermediate" }, { "name" : "Trucking litigation", "level" : "intermediate" }, { "name" : "Toxic tort", "level" : "intermediate" }, { "name" : "Professional liability", "level" : "intermediate" }, { "name" : "Business litigation", "level" : "intermediate" }, { "name" : "Appeals", "level" : "intermediate" }, { "name" : "Arbitration", "level" : "intermediate" }, { "name" : "Mediation", "level" : "intermediate" } ], "majorSkills" : "Complex trial, Litigation, Legal analysis", "majorSkillsList" : [ "Complex trial", "Litigation", "Legal analysis" ], "coreResponsibilities" : "Manage complex trial cases, Conduct legal research, Draft pleadings and motions, Manage discovery, Prepare for and take depositions, Prepare witnesses for testimony, Argue motions, Conduct trials, Negotiate settlements, Counsel clients, Handle appeals, Participate in arbitration, Participate in mediation", "teamCollaboration" : "Law firm teams; Clients", "projectManagementSkills" : [ "Case management" ], "domainKnowledge" : "Complex commercial litigation; Construction defect litigation; Employment litigation; Premises liability litigation; Product liability litigation; Catastrophic injury litigation; Medical malpractice litigation; Trucking litigation; Toxic tort litigation; Professional liability litigation; Business litigation; Appeals; Arbitration; Mediation", "domainList" : [ "complex-commercial-litigation", "construction-defect-litigation", "employment-litigation", "premises-liability-litigation", "product-liability-litigation", "catastrophic-injury-litigation", "medical-malpractice-litigation", "trucking-litigation", "toxic-tort-litigation", "professional-liability-litigation", "business-litigation", "appeals", "arbitration", "mediation" ], "domainSpecificKnowledge" : [ "Complex commercial litigation", "Construction defect litigation", "Employment litigation", "Premises liability litigation", "Product liability litigation", "Catastrophic injury litigation", "Medical malpractice litigation", "Trucking litigation", "Toxic tort litigation", "Professional liability litigation", "Business litigation", "Appeals", "Arbitration", "Mediation" ], "toolProficiency" : [ "Westlaw", "LexisNexis" ], "communicationSkills" : "Client counseling; Courtroom advocacy", "documentationSkills" : "Pleading drafting; Motion drafting; Discovery documents", "problemSolvingSkills" : "Legal analysis; Case strategy", "outcomesObjectives" : "Achieve favorable case outcomes; Successfully resolve client matters", "qualificationsBasic" : "5+ years of complex trial experience, Admission to the State Bar", "qualificationsPreferred" : "Experience with complex commercial litigation, Experience with construction defect litigation, Experience with employment litigation, Experience with premises liability litigation, Experience with product liability litigation, Experience with catastrophic injury litigation, Experience with medical malpractice litigation, Experience with trucking litigation, Experience with toxic tort litigation, Experience with professional liability litigation, Experience with business litigation, Experience with appeals, Experience with arbitration, Experience with mediation", "remoteFriendly" : true, "workSiteFlexibility" : "Flexible", "rawDescription" : "Join Tyson & Mendes – Senior Counsel, Complex Trial Teams Where Insurance Defense Meets Innovation Please note: An active bar license in the State of California is required. At Tyson & Mendes, we don’t just litigate—we lead. As a national force in insurance defense and trial advocacy, we’re known for our bold mission to stop Nuclear Verdicts® and our results-driven approach to high-exposure litigation. We are expanding our Complex Trial Teams and seeking accomplished Senior Counsel ready to make an impact in the courtroom and beyond. If you are an experienced trial lawyer who thrives on complex, high-stakes cases, values strategy over spectacle, and wants to be part of a team that is reshaping the future of civil defense—this is your opportunity. Why Tyson & Mendes? Lead with Impact – As Senior Counsel on our Complex Trial Team, you’ll take the reins on challenging, high-value matters with the support and trust of a firm built for trial success. Elite Training + Resources – From our Trial Academy to dedicated jury research and litigation support, we equip you with everything you need to succeed at the highest level. Stability + Momentum – Join a financially strong, nationally scaled firm with an agile, no-silos culture that prioritizes long-term success over short-term wins. Authentic Inclusion – At Tyson & Mendes, diverse perspectives and lived experiences are essential to our approach, our outcomes, and our culture. Results Matter, Not Where You Work – Office-based, hybrid, or remote—we focus on performance and outcomes, not location. Who You Are You are a trial-tested litigator with a defense-first mindset and the strategic acumen to lead complex cases from start to finish. You bring gravitas in the courtroom, confidence in depositions, and clarity in client communication. You think like a tactician, mentor with purpose, and uphold the highest standards of ethics and advocacy. With a deep understanding of high-exposure civil litigation—especially in areas like catastrophic injury, wrongful death, or construction defect—you are ready to take the next step in your leadership and litigation career. Make Your Move. Be part of something bigger—join Tyson & Mendes and help shape the future of insurance defense. Apply today. We’re ready for your best. Responsibilities Lead Complex Trials: Represent clients in high-exposure and complex insurance defense cases, including cases involving catastrophic injury, wrongful death, property damage, and professional liability. Case Strategy and Planning: Develop and execute case strategies, including risk assessment, discovery, motion practice, and trial preparation. Client Advisement: Work closely with clients, insurance carriers, and adjusters to provide clear legal advice, case assessments, and updates on case developments. Litigation Management: Oversee all stages of litigation, including pleadings, discovery, depositions, pre-trial motions, and settlement negotiations. Courtroom Representation: Serve as lead counsel in jury trials, bench trials, and mediations, presenting cases effectively and persuasively. Team Leadership and Mentorship: Supervise and mentor junior attorneys, paralegals, and support staff, ensuring high-quality work and compliance with best practices. Collaboration with Experts: Collaborate with expert witnesses, including medical, forensic, engineering, and economic experts, to strengthen case arguments. Requirements Juris Doctor (JD) from an accredited law school. Active license to practice law in the State of California and eligibility to practice in federal courts. 8+ years of experience in insurance defense litigation with a strong focus on complex trial work. Demonstrated success as lead trial counsel in multiple high-stakes cases. Strong knowledge of civil procedure, tort law, insurance law, and trial strategies. Proven ability to manage and prioritize a large, demanding caseload with limited oversight. Exceptional oral advocacy, legal writing, and negotiation skills. Strong client relationship management skills with an ability to communicate complex legal strategies effectively. Background in catastrophic injury, construction defect, or professional liability cases preferred. Experience with e-discovery tools and case management software. Membership in local or national trial lawyer associations is a plus. Compensation Package The base salary for this position ranges from $160,000-190,000 annually, depending on experience and qualifications Attorneys are eligible for an annual billable hours bonus ranging from $10,000 and then aggregating with $7,500 for every additional tier Comprehensive benefits coverage offered, including plans available at zero employee cost (average annual employer contribution for health/vision/dental/life coverage is $700-$1,700) Employees benefit from a 401(k) program that includes a 100% match on the first 3% contributed and a 50% match on the following 4-5% Employees receive a monthly technology reimbursement of $60 Student loan repayment assistance or 529 college savings plan (full-time attorneys after one year with the firm) $100-$200/month Paid parental leave at base pay Benefits Employee Assistance Program through HealthAdvocate Comprehensive in-house training and leadership development opportunities Firm Provided CLE Programs and Paid Bar License Renewal Fees Flexible vacation policy for attorneys Defined pathway to partnership Internal diversity and inclusion programs, such as the Women’s Initiative and Young Professionals Initiative Firm-wide charitable giving program Numerous social and off-site events each year to enrich your relationships with your colleagues Flexible Work Model: Remote, hybrid, or onsite options available About Tyson & Mendes Click here to learn more about the Tyson & Mendes Office! (944) The Tyson & Mendes Office - YouTube We’re one of the fastest-growing civil defense firms in the country—known for breaking the mold of the traditional law firm. Our dynamic, diverse team of trial attorneys delivers exceptional results, from landmark cases like Howell v. Hamilton Meats to numerous defense verdicts across the nation. But we don’t stop at great legal work—we invest in our people. With specialized training in our proven defense methods, clear paths to leadership, and robust professional development, we empower attorneys to grow their careers, build their personal brands, and become leaders in the field. Follow along with the firm on Twitter and LinkedIn or visit www.tysonmendes.com. Equal Opportunity Employer Notice OK, now for the legal copy (we are a law firm, after all). It is Tyson & Mendes’ policy to ensure equal employment opportunity without discrimination or harassment on the basis of race, religion, color, sex (including pregnancy, gender identity, and sexual orientation), parental status, national origin, age, disability, family medical history or genetic information, political affiliation, military service, or other non-merit-based factors. By the way, if you read all of this, congratulations – we can already tell your attention to detail is exceptional. NOTICE TO APPLICANTS/EMPLOYEES OF TYSON & MENDES: Please take notice that the Firm collects certain information about you. For more information on the Firm’s policies, please refer to the document provided here. No recruiters/agencies #li-remote Pay Range $160,000—$190,000 USD", "summaryDescription" : "Senior Counsel (Complex Trial) at Tyson & Mendes LLP. Skills: Complex trial, Litigation, Legal analysis. Manage complex trial cases. Conduct legal research", "postedDate" : "2026-06-14T21:48:11.727", "createdAt" : "2026-06-14T21:48:11.727", "lastUpdated" : "2026-06-16T05:50:15.234", "ingestTimestamp" : "2026-06-14T21:48:11.727", "mongoId" : "6a2c91e974d8ee00a0984529", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 160000, "salaryAnnualMax" : 190000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Complex trial", "Commercial litigation", "Construction defect", "Employment litigation", "Premises liability", "Product liability", "Catastrophic injury", "Medical malpractice", "Trucking litigation", "Toxic tort", "Professional liability", "Business litigation", "Appeals", "Arbitration", "Mediation", "Litigation", "Legal analysis", "Trial advocacy", "Legal research", "Legal writing", "Case management", "Negotiation", "Pleading drafting", "Discovery management", "Motion practice", "Client counseling", "Deposition preparation", "Witness preparation", "Complex commercial litigation", "Construction defect litigation", "Premises liability litigation", "Product liability litigation", "Catastrophic injury litigation", "Medical malpractice litigation", "Toxic tort litigation", "Professional liability litigation", "Admission to the State Bar", "Westlaw", "LexisNexis" ], "skillCount" : 39, "jobCategory" : "operations", "jobSubcategory" : "legal", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 294.87888, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Legal", "llmIndustryConfidence" : 0.98 }, { "id" : "6a2cfb4774d8ee00a0aa2bb3", "title" : "Sr Complex Billing Analyst", "company" : "Chariot Energy", "industry" : "Retail", "salary" : { "min" : 80000.0, "max" : 110000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Houston, Texas, United States", "locations" : [ "Houston", "Texas", "United States" ], "timestamp" : "2026-06-15T12:14:42.333", "fingerprint" : "f108cd72f630c34a7a8246e8ec57a600b2a49dd6ca0ddc94a858bea33b32cb0f", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/chariotenergy/jobs/4284053009", "externalId" : "4284053009", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Houston", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "29.7589382,-95.3676974" } ], "locationText" : "Houston, Texas, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Billing systems", "professionalSkills" : [ "Process management", "Cross-functional coordination", "Vendor management", "Stakeholder management", "Operational metrics", "Resource planning", "Continuous improvement", "Revenue assurance", "Process optimization", "Automation strategies", "Contract management", "Cash flow improvement", "Dispute resolution", "Compliance protocols", "Business relationships" ], "hardSkillsList" : [ "Statistical analysis", "Negotiation skills", "Conflict resolution skills" ], "softSkillsList" : [ "Analytical skills", "Stakeholder engagement", "Effective communication", "Agility" ], "hardSkills" : [ { "name" : "Statistical analysis", "level" : "intermediate" }, { "name" : "Negotiation skills", "level" : "intermediate" }, { "name" : "Conflict resolution skills", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Analytical skills" }, { "name" : "Stakeholder engagement" }, { "name" : "Effective communication" }, { "name" : "Agility" } ], "majorSkills" : "Complex billing, Retail energy market, ERCOT regulations", "majorSkillsList" : [ "Complex billing", "Retail energy market", "ERCOT regulations" ], "coreResponsibilities" : "Develop billing strategies, Implement billing strategies, Manage billing strategies, Monitor revenue performance, Analyze revenue performance, Identify trends, Identify areas for improvement, Utilize data and analytics, Analyze trends in data, Analyze patterns in data, Drive decision-making, Adjust strategy, Provide insights, Provide recommendations, Oversee billing process, Ensure accuracy, Ensure timeliness, Oversee client contracts, Account for contract elements, Develop strategies to improve cash flow, Reduce DSO, Review product structure, Investigate product structure, Recommend action on product structure, Ensure compliance with policies, Ensure compliance with procedures, Ensure compliance with regulations, Manage revenue performance, Maintain revenue performance, Report revenue performance, Action dispute resolution process, Mitigate customer disputes, Negotiate customer disputes, Ensure customer disputes resolution, Document root cause, Manage compliance protocols, Adhere to compliance protocols, Establish controls, Bridge identified gaps, Identify account issues, Resolve account issues, Display attention to detail, Adhere to Retail Market Guide, Understand regulation changes, Formulate solutions to comply, Establish business relationships, Maintain business relationships, Deliver on KPIs", "teamCollaboration" : "Cross-functional teams; Internal customers; Key stakeholders", "domainKnowledge" : "Retail energy market; Deregulated environments; ERCOT regulations; PJM; NYISO; NEPOOL; Public Utility Commissions", "domainList" : [ "retail-energy-market", "deregulated-environments", "ercot-regulations", "pjm", "nyiso", "nepool", "public-utility-commissions" ], "domainSpecificKnowledge" : [ "Retail energy market", "Deregulated environments", "ERCOT regulations", "PJM", "NYISO", "NEPOOL", "Public Utility Commissions" ], "toolProficiency" : [ "MS Office Suite" ], "communicationSkills" : "Verbal communication; Written communication", "innovationCreativity" : "Process optimization; Automation", "problemSolvingSkills" : "Problem-solving; Analytical skills; Data analysis", "outcomesObjectives" : "Ensure billing accuracy; Ensure billing efficiency; Achieve revenue assurance; Enhance billing operations effectiveness; Achieve financial health; Improve customer satisfaction", "qualificationsBasic" : "Bachelor's degree or 2 years supervisor experience, 5 years operations experience, Experience in deregulated energy market, Familiarity with complex billing structure, Proficiency in financial software, Proficiency in MS Office Suite, Ability to work under pressure, Ability to meet deadlines, Eligible to work in USA", "qualificationsPreferred" : "Expert-level knowledge of ERCOT regulations, Advanced billing systems knowledge", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "COMPANY OVERVIEW Chariot Energy, is an affiliate company of Hanwha Energy USA and ultimately Hanwha Group, a FORTUNE Global 500 firm that is among the eight largest business enterprises in South Korea. Hanwha Energy USA designs, builds and manages solar power plant solutions. The company brings a decade of global leadership in solar PV to North America, combining best-of-world technology, processes, and partnerships to deliver utility-grade solar PV solutions customized for local energy markets. Hanwha Energy USA offers the full spectrum of PV solutions – from power plant development, design, construction, operations, and maintenance. With proven capabilities across the solar value chain, Hanwha Energy USA minimizes uncertainty and risk, and helps customers achieve a higher return on their investment in solar energy. Hanwha Energy USA has recently embarked to enter the energy retail market in deregulated markets throughout North America. Chariot Energy is a retail energy provider based in Houston, Texas. We offer electricity to homes and businesses, and it is our goal to provide products and services our customers love and an unmatched experience that is missing in today’s retail energy market. Hanwha Energy USA has set out to have Chariot Energy become one of the leading energy retail providers (by RCE count) within 5-years of Chariot Energy’s launch. POSITION OVERVIEW We are seeking a highly skilled and proactive Senior Complex Billing Analyst to join our innovative and fast-paced organization. As a key leader within the billing operations team, the Senior Complex Billing Analyst will play a pivotal role in ensuring the accuracy and efficiency of our complex billing processes related to Large Commercial and Industrial accounts, which are integral to the company’s revenue assurance and operational success. This position requires an individual with a deep understanding of the retail energy market, especially within deregulated environments, and an expert-level knowledge of ERCOT regulations and advanced billing systems. In this role, you will be responsible for managing all aspects of billing, from developing and executing strategies that drive billing accuracy and compliance, to identifying opportunities for process optimization and automation. You will work closely with cross-functional teams to resolve billing issues, ensure compliance with industry regulations, and lead initiatives that enhance the overall effectiveness of the billing operations. The ideal candidate will not only bring extensive experience in managing complex billing structures but will also have a forward-thinking mindset, capable of anticipating challenges and proactively designing solutions. With a strong focus on process improvements, you will be empowered to make strategic decisions that directly impact on our financial health and customer satisfaction. Your ability to problem solve, innovate, and drive efficiency will be crucial in ensuring the success of our billing operations and contributing to the organization’s broader financial and operational goals. This position is based in Houston, and the ideal candidate will be within commutable distance to the Houston office location. The position will be located outside the Chariot Energy Houston office. RESPONSIBILITIES Develop, implement and manage effective billing strategies, policies and procedures for residential, commercial and industrial accounts. Monitor and analyze revenue performance metrics, identifying trends and areas for improvement. Utilize data and analytics to analyze trends and patterns in data, driving decision-making and strategy adjustments, and providing insights and recommendations to senior management. Oversee the end-to-end billing process to ensure accuracy and timeliness. Oversee all aspects of client contracts assigned ensuring all elements are properly accounted for in CE systems during setup and invoicing/billing processes Develop and implement strategies to improve cash flow and reduce DSO (Days Sales Outstanding). Review, investigate, and recommend action on product structure and market insights Ensure compliance with company policies and procedures, as well as legal and regulatory requirements. Manage, maintain, and report on revenue performance to management. Action the dispute resolution process from end to end, by proactively mitigating customer disputes, negotiating and ensuring customer disputes to resolution and document root cause. Manage and adhere to compliance protocols as outlined by the Public Utility Commissions and other government entities. Establish controls to bridge identified gaps between other business stakeholders. Proactively identify and resolve existing and potential future account issues in a timely and accurate fashion by displaying an acute attention to detail. Adhere to Retail Market Guide protocols as set forth by ERCOT, PJM, NYISO and NEPOOL. Take the lead when changes and proposed regulations occur to understand potential gaps to current processes and formulate solutions to comply. Establish and maintain positive business relationships with internal customers and key stakeholders in the revenue process. Achieve excellence by delivering on key performance indicators (KPI’s). REQUIRED COMPETENCIES Analytical- Proven problem-solving capability with strong analytical skills including statistical analysis, Stakeholder Engagement– Understands the importance of seeking out relationships and working with others toward a shared goal. Effective Communication- Strong verbal and written communication skills. Agility- Demonstrate willingness to modify position as needed to meet the needs of the business. REQUIRED QUALIFICATIONS Bachelor’s degree in business or related areas from an accredited four-year university OR minimum two years previous supervisor experience in Complex Billing Operations can substitute for a degree. Minimum of 5 years’ operations experience in back-office operations (i.e., customer set up, Complex billing, contract management, customer relations). Experience in the deregulated energy market, primarily ERCOT, PJM, NYISO and NEPOOL. Familiarity with complex billing structure. Strong analytical and problem-solving abilities to identify trends, analyze data, and make informed decisions. Proven negotiation and conflict resolution skills. Proven experience managing revenue generation for customers in the commercial/industrial/retail energy markets. Strong analytical and problem-solving abilities. Strong communication and interpersonal skills. Proficiency in financial software and MS Office Suite. Ability to work effectively under pressure and meet deadlines. Eligible to work in the USA for any employer without sponsorship. COMPENSATION: $80,000 - $110,000 salary Attention external recruitment firms, we will not accept any unsolicited resumes at this time. Please do not contact any internal member of our company to discuss the position or to solicit candidates. Chariot Energy provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, national origin, age, disability, or genetics. www.mychariotenergy.com", "summaryDescription" : "Sr Complex Billing Analyst at Chariot Energy. Skills: Complex billing, Retail energy market, ERCOT regulations. Develop billing strategies. Implement billing strategies", "postedDate" : "2026-06-14T05:38:13.664", "createdAt" : "2026-06-14T05:38:13.664", "lastUpdated" : "2026-06-15T12:14:42.333", "ingestTimestamp" : "2026-06-14T05:38:13.664", "mongoId" : "6a2cfb4774d8ee00a0aa2bb3", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 80000, "salaryAnnualMax" : 110000, "salaryBand" : "75k-100k", "hasSalary" : true, "allSkills" : [ "Statistical analysis", "Negotiation skills", "Conflict resolution skills", "Analytical skills", "Stakeholder engagement", "Effective communication", "Agility", "Complex billing", "Retail energy market", "ERCOT regulations", "Process management", "Cross-functional coordination", "Vendor management", "Stakeholder management", "Operational metrics", "Resource planning", "Continuous improvement", "Revenue assurance", "Process optimization", "Automation strategies", "Contract management", "Cash flow improvement", "Dispute resolution", "Compliance protocols", "Business relationships", "Deregulated environments", "PJM", "NYISO", "NEPOOL", "Public Utility Commissions", "MS Office Suite" ], "skillCount" : 31, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 294.46454, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Energy", "llmIndustryConfidence" : 0.95 }, { "id" : "6a2a875c74d8ee00a067e020", "title" : "Senior Engineer, Mixed Signal Design Engineering", "company" : "Analog Devices, Inc.", "salary" : { "min" : 11.0, "max" : 11.0, "currency" : "USD", "frequency" : "yearly" }, "location" : "US, AZ, Chandler, East Elliot", "locations" : [ "US, AZ, Chandler, East Elliot", "United States of America" ], "timestamp" : "2026-06-13T08:03:13.886", "fingerprint" : "f936e51b1de15190f9601540384b4019f4cf6a534a58177879ba527b678a4ba7", "source" : "workday", "language" : "en", "applyUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/US-AZ-Chandler-East-Elliot/Senior-Engineer--Mixed-Signal-Design-Engineering_R263319-1", "externalId" : "R263319", "locationPoint" : "31.20864,31.63528", "structuredLocations" : [ { "city" : "Chandler", "state" : "Arizona", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "hybrid", "geo" : "33.3062031,-111.8411850" } ], "locationText" : "Chandler, Arizona, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Analog circuit design, CADENCE, SPICE", "professionalSkills" : [ "Product development lifecycle", "Circuit design", "Chip floor planning", "Physical implementation", "Lab evaluation", "Performance debugging", "Project planning" ], "hardSkillsList" : [ "Circuit analysis", "Simulation", "Verification", "Evaluation", "Performance targets" ], "hardSkills" : [ { "name" : "Circuit analysis", "level" : "intermediate" }, { "name" : "Simulation", "level" : "intermediate" }, { "name" : "Verification", "level" : "intermediate" }, { "name" : "Evaluation", "level" : "intermediate" }, { "name" : "Performance targets", "level" : "intermediate" } ], "majorSkills" : "Mixed Signal Design, Analog Design, IC Design", "majorSkillsList" : [ "Mixed Signal Design", "Analog Design", "IC Design" ], "coreResponsibilities" : "Perform analog and mixed signal circuit analysis, Design mixed-signal products, Simulate mixed-signal products, Verify mixed-signal products, Evaluate mixed-signal products, Support design of mixed-signal products, Integrate design blocks into systems, Drive product development lifecycle, Define product requirements, Execute circuit design, Identify design issues, Recommend design solutions, Apply design techniques, Apply verification techniques, Produce efficient designs, Meet functional objectives, Meet power objectives, Meet timing objectives, Function as chip lead, Lead analog designer, Lead digital designer, Perform chip floor planning, Guide layout engineers, Evaluate physical implementation, Ensure physical design meets metrics, Perform lab evaluation, Debug integrated circuit performance, Derive block level performance targets, Work with cross functional teams, Define project goals, Define project feasibility, Define project timelines, Follow up on quality issues, Document design reviews, Present design reviews, Document evaluation reviews, Present evaluation reviews", "teamCollaboration" : "Cross functional team; Project planning teams; Layout engineers; Peer review; Stakeholder groups", "domainKnowledge" : "Mixed-Signal Power IC design; RF IC design; Analog/Mixed-Signal IC design", "domainList" : [ "mixed-signal-power-ic-design", "rf-ic-design", "analog-mixed-signal-ic-design" ], "domainSpecificKnowledge" : [ "Mixed-Signal Power IC design", "RF IC design", "Analog/Mixed-Signal IC design" ], "toolProficiency" : [ "CADENCE", "SPICE" ], "communicationSkills" : "Technical presentations", "documentationSkills" : "Design documentation; Evaluation documentation", "problemSolvingSkills" : "Debugging", "qualificationsBasic" : "Master's degree in EE, Electronics, or CE, 2 years experience as Mixed Signal or EE, Demonstrated Expertise in new mixed signal product development, Demonstrated Expertise analyzing transistor level circuit designs, Demonstrated Expertise in Mixed-Signal Power IC design, Demonstrated Expertise in RF IC design, Demonstrated Expertise in General purpose Analog/Mixed-Signal IC design, Demonstrated Expertise simulating complex analog IC designs, Demonstrated Expertise preparing technical presentations", "remoteFriendly" : true, "workSiteFlexibility" : "Hybrid", "rawDescription" : "**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). **Employer:** Analog Devices, Inc. **Job Title:** Senior Engineer, Mixed Signal Design Engineering **Job Requisition:** 1010.1286.9 / R263319 **Job Location:** Chandler, Arizona **Job Type:** Full Time **Rate of Pay:** $114,234 - $166,668 per year [multiple openings] **Duties:** Perform analog and mixed signal circuit analysis, design, simulation, verification, and evaluation supporting the design of mixed-signal products and the successful integration of design blocks into larger mixed-signal systems. Drive the product development lifecycle, including defining product requirements, executing circuit design, identifying issues, and recommending solutions. Apply formal design and verification techniques, tools, and methodologies to produce efficient designs which meet specified functional, power, or timing objectives. Function as the chip lead and lead analog or digital designer for projects and perform chip floor planning to guide layout engineers during physical implementation. Evaluate the physical implementation of design blocks by layout engineers to ensure physical design meets design, performance, and reliability metrics. Perform lab evaluation and debugging of performance issues of integrated circuits. Derive block level performance targets from higher-level design specifications. Work with cross functional team and project planning teams to define project goals, feasibility and timelines. Drive follow-up on quality issues involving customer returns, QA failures, and test coverage issues. Document and present design and evaluation review documentation for peer review or before stakeholder groups. Partial telecommute benefit available (2 days/week work from home). **Requirements:** Must have a Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or closely related technical discipline (willing to accept foreign education equivalent) and two (2) years of experience as a Mixed Signal or Electrical Engineer or related occupation performing integrated circuit development. Must also possess the following (quantitative experience requirements not applicable to this section): * Demonstrated Expertise (DE) participating in all phases of new mixed signal product development (architecture selection, debugging, implementation, evaluation). * DE analyzing functionality and behavior of transistor level circuit designs. * DE in one of the applicable design areas: Mixed-Signal Power IC design, RF IC design, General purpose Analog/Mixed-Signal IC design. * DE simulating and evaluating complex technical analog blocks and IC designs using CADENCE and SPICE-type simulation tools. * DE preparing and delivering technical materials and presentations before internal and external audiences and stakeholders. **Contact:** Eligible for employee referral program. Apply online at and Reference Position Number: R263319. _For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process._ _Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group._ _EEO is the Law:[Notice of Applicant Rights Under the Law](https://www1.eeoc.gov/employers/upload/eeoc_self_print_poster.pdf)._ Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days", "summaryDescription" : "Senior Engineer, Mixed Signal Design Engineering at Analog Devices, Inc.. Skills: Mixed Signal Design, Analog Design, IC Design. Perform analog and mixed signal circuit analysis. Design mixed-signal products", "postedDate" : "2026-06-08T16:13:41.604", "createdAt" : "2026-06-11T16:13:41.565", "lastUpdated" : "2026-06-13T08:03:13.886", "ingestTimestamp" : "2026-06-11T16:13:41.565", "mongoId" : "6a2a875c74d8ee00a067e020", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/US-AZ-Chandler-East-Elliot/Senior-Engineer--Mixed-Signal-Design-Engineering_R263319-1", "salaryAnnualMin" : 22880, "salaryAnnualMax" : 22880, "salaryBand" : "<30k", "hasSalary" : true, "allSkills" : [ "Circuit analysis", "Simulation", "Verification", "Evaluation", "Performance targets", "Mixed Signal Design", "Analog Design", "IC Design", "Product development lifecycle", "Circuit design", "Chip floor planning", "Physical implementation", "Lab evaluation", "Performance debugging", "Project planning", "Mixed-Signal Power IC design", "RF IC design", "Analog/Mixed-Signal IC design", "CADENCE", "SPICE" ], "skillCount" : 20, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 293.95786, "daysOld" : 4, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a25313d74d8ee00a0100080", "title" : "Staff Mixed-Signal Design Engineer", "company" : "Analog Devices", "industry" : "Semiconductor", "salary" : { "min" : 9.0, "max" : 9.0, "currency" : "USD", "frequency" : "yearly" }, "location" : "Ireland, Limerick", "locations" : [ "Ireland, Limerick" ], "timestamp" : "2026-06-09T17:56:42.661", "fingerprint" : "9b374856e8bfd6f02c37e06bd5e154999f35571bda92644d87415402e73f3b47", "source" : "workday", "language" : "en", "applyUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/Ireland-Limerick/Staff-Mixed-Signal-Design-Engineer_R260359", "externalId" : "R260359", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Limerick", "country" : "Ireland", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "52.6612520,-8.6301239" } ], "locationText" : "Limerick, Ireland", "employmentType" : "FULL_TIME", "minimumEducation" : "Master's", "experienceMinYears" : 7, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "Mixed-signal, ADC, DAC, SerDes PHY, FinFET", "professionalSkills" : [ "Technical leadership", "Design reviews", "Product development" ], "hardSkillsList" : [ "Transistor-level design", "Integrated circuit design" ], "hardSkills" : [ { "name" : "Transistor-level design", "level" : "intermediate" }, { "name" : "Integrated circuit design", "level" : "intermediate" } ], "majorSkills" : "Mixed-signal design, Integrated circuits, ADC, DAC", "majorSkillsList" : [ "Mixed-signal design", "Integrated circuits", "ADC", "DAC" ], "coreResponsibilities" : "Evaluate alternative mixed-signal subsystem implementation architectures, Design transistor-level mixed-signal integrated circuits, Prepare design documents, Conduct design reviews, Guide mixed-signal integrated circuit layout, Guide mixed-signal integrated circuit evaluation, Guide mixed-signal integrated circuit test", "domainKnowledge" : "Data converter architectures; SerDes PHY architectures; Mixed-signal design fundamentals; Integrated circuit product development", "domainList" : [ "data-converter-architectures", "serdes-phy-architectures", "mixed-signal-design-fundamentals", "integrated-circuit-product-development" ], "domainSpecificKnowledge" : [ "Data converter architectures", "SerDes PHY architectures", "Mixed-signal design fundamentals", "Integrated circuit product development" ], "documentationSkills" : "Design documents", "qualificationsBasic" : "MS Electrical Engineering, 7+ years mixed-signal IC development, Deep understanding of mixed-signal design fundamentals, Solid understanding of IC product development, Successful experience developing challenging mixed-signal ICs for commercial applications", "qualificationsPreferred" : "understanding of data converter architectures and specifications, deep understanding of SerDes PHY architectures and specifications", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "**About Analog Devices** Analog Devices, Inc. (NASDAQ: _[ADI](http://finance.yahoo.com/q?s=ADI)_ ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at _[www.analog.com](https://www.analog.com/)_ and on _[LinkedIn](https://www.linkedin.com/company/analog-devices/posts/?feedView=all)_ and _[Twitter (X)](https://x.com/adi_news)_. **Staff Mixed-Signal Design Engineer** **Job Duties and Responsibilities** As a Staff Mixed-Signal Design Engineer within the Advanced Cores Group (ACG) you will work on the development of ADC, DAC, and/or SerDes PHY subsystems for highly sophisticated mixed-signal system-on-chip (SoC) integrated circuit products using FinFET wafer technologies. The Advanced Cores Group develops innovative, state of the art, high-performance circuits as often shown by presentations at premier conferences and publications in premier journals. Your work will include: * Evaluating alternative mixed-signal subsystem implementation architectures. * Designing challenging transistor-level mixed-signal integrated circuits. * Preparing effective design documents and conduct effective design reviews. * Guiding mixed-signal integrated circuit layout. * Guiding mixed-signal integrated circuit evaluation and test. **Qualifications** * MS Electrical Engineering. * 7+ years of mixed-signal integrated circuit development experience. * Strong understanding of data converter architectures and specifications and/or deep understanding of SerDes PHY architectures and specifications * Deep understanding of mixed-signal design fundamentals, design tools, and methodologies. * Solid understanding of integrated circuit product development, including design, verification, evaluation, test, and qualification. * Successful experience developing challenging mixed-signal integrated circuits for commercial applications. * Strong technical leadership, teamwork, and communication skills. _For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process._ _Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group._ Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days", "summaryDescription" : "Staff Mixed-Signal Design Engineer at Analog Devices. Skills: Mixed-signal design, Integrated circuits, ADC, DAC. Evaluate alternative mixed-signal subsystem implementation architectures. Design transistor-level mixed-signal integrated circuits", "postedDate" : "2026-05-14T12:24:53.837", "createdAt" : "2026-06-07T12:24:53.784", "lastUpdated" : "2026-06-09T17:56:42.661", "ingestTimestamp" : "2026-06-07T12:24:53.784", "mongoId" : "6a25313d74d8ee00a0100080", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/Ireland-Limerick/Staff-Mixed-Signal-Design-Engineer_R260359", "salaryAnnualMin" : 18720, "salaryAnnualMax" : 18720, "salaryBand" : "<30k", "hasSalary" : true, "allSkills" : [ "Transistor-level design", "Integrated circuit design", "Mixed-signal design", "Integrated circuits", "ADC", "DAC", "Technical leadership", "Design reviews", "Product development", "Data converter architectures", "SerDes PHY architectures", "Mixed-signal design fundamentals", "Integrated circuit product development" ], "skillCount" : 13, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 292.0134, "daysOld" : 26, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Semiconductor" }, { "id" : "6a1a4ed558b93c861e7e125a", "title" : "Staff Mixed-Signal Design Engineer", "company" : "Analog Devices, Inc.", "industry" : "semiconductor", "salary" : { "min" : 9.0, "max" : 9.0, "currency" : "USD", "frequency" : "yearly" }, "location" : "Ireland, Cork", "locations" : [ "Ireland, Cork" ], "timestamp" : "2026-05-30T06:22:54.011", "fingerprint" : "de3a2a9af5844f1736bd57dc00c72824fd5c83fa365bd33d6dfb69d9935b8b01", "source" : "workday", "language" : "en", "applyUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/Ireland-Cork/Staff-Mixed-Signal-Design-Engineer_R260356", "externalId" : "R260356", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Cork", "country" : "Ireland", "continent" : "eu", "source" : "llm", "workMode" : "onsite" } ], "locationText" : "Cork, Ireland", "employmentType" : "FULL_TIME", "minimumEducation" : "MS Electrical Engineering", "experienceMinYears" : 7, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "ADC, DAC, SerDes PHY, FinFET wafer technologies, mixed-signal integrated circuits", "professionalSkills" : [ "technical leadership", "teamwork", "communication skills" ], "hardSkillsList" : [ "mixed-signal design", "data converter architectures", "SerDes PHY architectures", "integrated circuit development" ], "hardSkills" : [ { "name" : "mixed-signal design", "level" : "intermediate" }, { "name" : "data converter architectures", "level" : "intermediate" }, { "name" : "SerDes PHY architectures", "level" : "intermediate" }, { "name" : "integrated circuit development", "level" : "intermediate" } ], "majorSkills" : "Mixed-Signal Design, Integrated Circuits, ADC, DAC", "majorSkillsList" : [ "Mixed-Signal Design", "Integrated Circuits", "ADC", "DAC" ], "coreResponsibilities" : "Evaluate alternative mixed-signal subsystem implementation architectures, Design challenging transistor-level mixed-signal integrated circuits, Prepare effective design documents, Conduct effective design reviews, Guide mixed-signal integrated circuit layout, Guide mixed-signal integrated circuit evaluation and test", "domainKnowledge" : "data converter architectures; SerDes PHY architectures; mixed-signal design fundamentals; integrated circuit product development", "domainList" : [ "data-converter-architectures", "serdes-phy-architectures", "mixed-signal-design-fundamentals", "integrated-circuit-product-development" ], "domainSpecificKnowledge" : [ "data converter architectures", "SerDes PHY architectures", "mixed-signal design fundamentals", "integrated circuit product development" ], "toolProficiency" : [ "design tools" ], "communicationSkills" : "communication skills", "documentationSkills" : "design documents", "innovationCreativity" : "innovative; state of the art; high-performance circuits", "specialRequirements" : "export licensing approval", "qualificationsBasic" : "MS Electrical Engineering, 7+ years of mixed-signal integrated circuit development experience, understanding of data converter architectures and specifications, deep understanding of SerDes PHY architectures and specifications, Deep understanding of mixed-signal design fundamentals, design tools, methodologies, Solid understanding of integrated circuit product development, design, verification, evaluation, test, qualification, Successful experience developing challenging mixed-signal integrated circuits for commercial applications", "remoteFriendly" : false, "rawDescription" : "**About Analog Devices** Analog Devices, Inc. (NASDAQ: _[ADI](http://finance.yahoo.com/q?s=ADI)_ ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at _[www.analog.com](https://www.analog.com/)_ and on _[LinkedIn](https://www.linkedin.com/company/analog-devices/posts/?feedView=all)_ and _[Twitter (X)](https://x.com/adi_news)_. **Staff Mixed-Signal Design Engineer** **Job Duties and Responsibilities** As a Staff Mixed-Signal Design Engineer within the Advanced Cores Group (ACG) you will work on the development of ADC, DAC, and/or SerDes PHY subsystems for highly sophisticated mixed-signal system-on-chip (SoC) integrated circuit products using FinFET wafer technologies. The Advanced Cores Group develops innovative, state of the art, high-performance circuits as often shown by presentations at premier conferences and publications in premier journals. Your work will include: * Evaluating alternative mixed-signal subsystem implementation architectures. * Designing challenging transistor-level mixed-signal integrated circuits. * Preparing effective design documents and conduct effective design reviews. * Guiding mixed-signal integrated circuit layout. * Guiding mixed-signal integrated circuit evaluation and test. **Qualifications** * MS Electrical Engineering. * 7+ years of mixed-signal integrated circuit development experience. * Strong understanding of data converter architectures and specifications and/or deep understanding of SerDes PHY architectures and specifications * Deep understanding of mixed-signal design fundamentals, design tools, and methodologies. * Solid understanding of integrated circuit product development, including design, verification, evaluation, test, and qualification. * Successful experience developing challenging mixed-signal integrated circuits for commercial applications. * Strong technical leadership, teamwork, and communication skills. _For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process._ _Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group._ Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days", "summaryDescription" : "Staff Mixed-Signal Design Engineer at Analog Devices, Inc.. Skills: Mixed-Signal Design, Integrated Circuits, ADC, DAC. Evaluate alternative mixed-signal subsystem implementation architectures. Design challenging transistor-level mixed-signal integrated circuits", "postedDate" : "2026-05-15T06:12:30.410", "createdAt" : "2026-05-30T06:12:30.387", "lastUpdated" : "2026-05-30T06:22:54.011", "ingestTimestamp" : "2026-05-30T06:12:30.387", "mongoId" : "6a1a4ed558b93c861e7e125a", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/Ireland-Cork/Staff-Mixed-Signal-Design-Engineer_R260356", "salaryAnnualMin" : 18720, "salaryAnnualMax" : 18720, "salaryBand" : "<30k", "hasSalary" : true, "allSkills" : [ "mixed-signal design", "data converter architectures", "SerDes PHY architectures", "integrated circuit development", "Mixed-Signal Design", "Integrated Circuits", "ADC", "DAC", "technical leadership", "teamwork", "communication skills", "mixed-signal design fundamentals", "integrated circuit product development", "design tools" ], "skillCount" : 14, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 291.4578, "daysOld" : 15, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "semiconductor" }, { "id" : "69e1043f2beec4dd3def2457", "title" : "Signal/Power Integrity Eng", "company" : "Annapurna Labs", "industry" : "Hardware Development, Cloud Hardware Development, Cloud Computing", "salary" : { "min" : 136000.0, "max" : 184000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Austin, Texas, USA", "locations" : [ "Austin, Texas, USA" ], "timestamp" : "2026-06-15T03:50:20.760", "fingerprint" : "566047304ced0b38e02b9b94960a679a7f877934f1acca05f7f6570e470415ab", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10387645/apply", "externalId" : "49b632bd-65e3-4792-8cd6-d532cec57972", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Austin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.2711286,-97.7436995" } ], "locationText" : "Austin, Texas, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 3, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "technicalSkills" : "Hspice, Sigrity, HFSS, Microwave Studio, SerDes, Single-ended signal, Parallel bus", "professionalSkills" : [ "Signal integrity", "Power integrity", "Design leadership", "Data analysis" ], "hardSkillsList" : [ "Transmission line theory", "Electromagnetics", "Simulation tools", "PCB design", "Power delivery systems", "EMIR simulation" ], "softSkillsList" : [ "Innovation", "Mentoring" ], "hardSkills" : [ { "name" : "Transmission line theory", "level" : "intermediate" }, { "name" : "Electromagnetics", "level" : "intermediate" }, { "name" : "Simulation tools", "level" : "intermediate" }, { "name" : "PCB design", "level" : "intermediate" }, { "name" : "Power delivery systems", "level" : "intermediate" }, { "name" : "EMIR simulation", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Innovation" }, { "name" : "Mentoring" } ], "majorSkills" : "Signal integrity, Power integrity, ASIC design, High-speed digital design", "majorSkillsList" : [ "Signal integrity", "Power integrity", "ASIC design", "High-speed digital design" ], "coreResponsibilities" : "Define machine learning ASICs, Design machine learning ASICs, Validate machine learning ASICs, Participate in SI related topics, Create customized platforms, Solve challenging technical problems, Influence product decisions", "teamCollaboration" : "Collaborate across diverse teams; Cross-functional collaboration skills", "domainKnowledge" : "Machine learning ASICs; Advanced packaging technologies; PCB design; Power delivery systems; SOC power; High-speed digital design", "domainList" : [ "machine-learning-asics", "advanced-packaging-technologies", "pcb-design", "power-delivery-systems", "soc-power", "high-speed-digital-design" ], "domainSpecificKnowledge" : [ "Machine learning ASICs", "Advanced packaging technologies", "PCB design", "Power delivery systems", "SOC power", "High-speed digital design" ], "toolProficiency" : [ "Hspice", "Cadence", "HFSS", "Redhawk 3DIC", "Voltus" ], "continuousLearning" : "Knowledge-sharing; Mentorship", "innovationCreativity" : "Innovation; Innovative solutions", "problemSolvingSkills" : "Solve challenging technical problems", "outcomesObjectives" : "Create customized platforms; Deliver results that help customers change the world", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, 3+ years of experience using time domain and frequency domain tools, 3+ years of experience with PCB, Package, interposers, 3+ years of experience in Transmission line theory and Electromagnetics", "qualificationsPreferred" : "Master's degree in Electrical Engineering, Experience with die capacitors, Experience with SOC power, Experience with 3D/2.5D EMIR simulation tools, 5+ years of experience with high speed scopes and probing techniques", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter’s world leading technology. Key job responsibilities Our engineers collaborate across diverse teams, projects, and environments to have a firsthand impact on our global customer base. You’ll bring a passion for innovation, data, and hardware knowledge. You'll also solve challenging technical problems, often ones not solved before, at every layer of the design. This Signal Integrity Engineering role combines technical expertise with strategic design leadership. The ideal candidate will bring 3+ years of experience in signal and power integrity, with hands-on expertise in simulation tools like Hspice, Cadence, and HFSS. The role involves working with advanced packaging technologies, PCB design, and power delivery systems. Additional experience with die capacitors, SOC power, and 3D/2.5D EMIR simulation tools would be valuable. The position offers direct impact on product quality through innovative solutions for complex signal integrity challenges, requiring both technical depth and cross-functional collaboration skills. The engineer will work in a dynamic environment, influencing product decisions while solving cutting-edge challenges in high-speed digital design. A day in the life About the team Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future. Diverse Experiences AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying. About AWS Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses. Inclusive Team Culture Here at AWS, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness. Work/Life Balance We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud. Mentorship & Career Growth We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional. Basic Qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Systems Engineering, or related fields - - 3+ years of experience using time domain and frequency domain tools: Hspice, Sigrity, HFSS, or Microwave Studio - - 3+ years of experience with PCB, Package, interposers (COWOS) and Silicon Technologies - - 3 + years of experience in Transmission line theory and Electromagnetics and its application in SerDes, Single-ended signal and parallel bus interfaces. Preferred Qualifications: - Master's degree in Electrical Engineering - Experience with die capacitors, DTC caps and IPD caps - Experience with SOC power, integrated power Module - Experience with 3D/2.5D EMIR simulation tools: Redhawk 3DIC or Voltus - 5 + years of experience with high speed scopes and probing techniques Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, TX, Austin - 136,000.00 - 184,000.00 USD annually", "summaryDescription" : "Signal/Power Integrity Eng at Annapurna Labs. Skills: Signal integrity, Power integrity, ASIC design, High-speed digital design. Define machine learning ASICs. Design machine learning ASICs", "postedDate" : "2026-06-13T17:23:38.634", "createdAt" : "2026-06-13T17:23:38.634", "lastUpdated" : "2026-06-15T03:50:20.760", "ingestTimestamp" : "2026-06-13T17:23:38.634", "mongoId" : "69e1043f2beec4dd3def2457", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10387645/apply", "salaryAnnualMin" : 136000, "salaryAnnualMax" : 184000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Transmission line theory", "Electromagnetics", "Simulation tools", "PCB design", "Power delivery systems", "EMIR simulation", "Innovation", "Mentoring", "Signal integrity", "Power integrity", "ASIC design", "High-speed digital design", "Design leadership", "Data analysis", "Machine learning ASICs", "Advanced packaging technologies", "SOC power", "Hspice", "Cadence", "HFSS", "Redhawk 3DIC", "Voltus" ], "skillCount" : 22, "jobCategory" : "other", "dataQualityScore" : 1.0, "_score" : 291.24765, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a216dec74d8ee00a0c0c56c", "title" : "Layout Engineer, DEG Layout", "company" : "Micron Technology", "industry" : "Technology", "salary" : { "min" : 1500000.0, "max" : 2500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Layout Engineer in Hyderabad, India, adjusted for the technology industry and company size." }, "location" : "Hyderabad - Phoenix Aquila, India", "locations" : [ "Hyderabad - Phoenix Aquila, India" ], "timestamp" : "2026-06-05T07:36:36.477", "fingerprint" : "e90ac3f891dad54932b089aaa087493603c8662938a9f032c4b552fef5b43abc", "source" : "workday", "language" : "en", "applyUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/Layout-Engineer--DEG-Layout_JR97413", "externalId" : "JR97413", "industryFunction" : { }, "locationPoint" : "17.38405,78.45636", "structuredLocations" : [ { "city" : "Hyderabad", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "17.3605890,78.4740613" } ], "locationText" : "Hyderabad, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 3, "experienceMaxYears" : 7, "experienceLevel" : "Mid", "technicalSkills" : "CMOS process, Analog layout, Mixed-signal layout", "professionalSkills" : [ "Area estimation", "Time estimation", "Project management" ], "hardSkillsList" : [ "Layout verification", "LVS/DRC/Antenna", "Quality check", "Physical verification" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Layout verification", "level" : "intermediate" }, { "name" : "LVS/DRC/Antenna", "level" : "intermediate" }, { "name" : "Quality check", "level" : "intermediate" }, { "name" : "Physical verification", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "Layout Design, Analog Layout, Mixed-signal Layout", "majorSkillsList" : [ "Layout Design", "Analog Layout", "Mixed-signal Layout" ], "coreResponsibilities" : "Design critical analog blocks, Design mixed-signal blocks, Design custom digital blocks, Support full chip level integration, Perform layout verification, Perform quality check, Support documentation, Deliver block-level layouts, Plan projects, Estimate area, Estimate time, Schedule execution, Contribute to project-management, Communicate with Global engineering teams", "teamCollaboration" : "Peer teams; Global footprint; Global engineering teams", "projectManagementSkills" : [ "Scheduling", "Execution" ], "domainKnowledge" : "Analog layout fundamentals; Advanced CMOS process; DRAM chip design; High Bandwidth Memory", "domainList" : [ "analog-layout-fundamentals", "advanced-cmos-process", "dram-chip-design", "high-bandwidth-memory" ], "domainSpecificKnowledge" : [ "Analog layout fundamentals", "Advanced CMOS process", "DRAM chip design", "High Bandwidth Memory" ], "toolProficiency" : [ "Cadence VLE/VXL", "Mentor Graphic Calibre" ], "communicationSkills" : "Verbal communication; Written communication", "continuousLearning" : "Exploring AI-related tools", "problemSolvingSkills" : "Problem-solving", "outcomesObjectives" : "On-time delivery of layouts", "qualificationsBasic" : "3 to 7 years analog/custom layout design, Advanced CMOS process experience, Cadence VLE/VXL expertise, Mentor Graphic Calibre DRC/LVS expertise, Hands on experience creating layout of critical blocks, Good understanding of Analog Layout fundamentals, Understanding layout effects on circuit, Ability to understand design constraints, Ability to understand design hierarchy, Excellent problem-solving skills in physical verification, BE or MTech in Electronic/VLSI Engineering", "qualificationsPreferred" : "Multiple Tape out support experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s DPG-IPDEV Team in Bangalore, India. DPG-IPDEV team is responsible for developing world-class analog and mixed signal IPs used in every modern DRAM chip produced in Micron. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule milestones in multiple project environment. • Contribute to effective project-management. • Effectively communicating with Global engineering teams to assure the success of layout project. **Qualification/Requirements** • **3 to 7 years ' **experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., • Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.) • Understanding layout effects on the circuit such as speed, capacitance, power and area etc. • Ability to understand design constraints and implement high-quality layouts • Ability to understand design hierarchy and different architectures for Memory designs. • Excellent problem-solving skills in physical verification of custom layout. • Multiple Tape out support experience will be an added advantage. • Excellent verbal and written communication skills. * Should be proactive in exploring more AI-related tools in day-to-day tasks. Education BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. **About Micron Technology, Inc.** We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life _for all_. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact [hrsupport_india@micron.com](mailto:hrsupport_in@micron.com) Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "summaryDescription" : "Layout Engineer, DEG Layout at Micron Technology. Skills: Layout Design, Analog Layout, Mixed-signal Layout. Design critical analog blocks. Design mixed-signal blocks", "postedDate" : "2026-05-07T18:09:04.859", "createdAt" : "2026-06-04T18:09:04.783", "lastUpdated" : "2026-06-05T07:36:36.477", "ingestTimestamp" : "2026-06-04T18:09:04.783", "mongoId" : "6a216dec74d8ee00a0c0c56c", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/Layout-Engineer--DEG-Layout_JR97413", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Layout verification", "LVS/DRC/Antenna", "Quality check", "Physical verification", "Leadership", "Layout Design", "Analog Layout", "Mixed-signal Layout", "Area estimation", "Time estimation", "Project management", "Scheduling", "Execution", "Analog layout fundamentals", "Advanced CMOS process", "DRAM chip design", "High Bandwidth Memory", "Cadence VLE/VXL", "Mentor Graphic Calibre" ], "skillCount" : 19, "jobCategory" : "engineering", "seniorityLevel" : "mid", "dataQualityScore" : 1.0, "_score" : 289.0074, "daysOld" : 28, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a305733f292fd229cf3549b", "title" : "Senior AML/KYC Onboarding Analyst, Funds & Complex Structures", "company" : "iBanFirst", "industry" : "FinTech", "salary" : { "min" : 55000.0, "max" : 75000.0, "currency" : "EUR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Senior AML/KYC Onboarding Analyst in FinTech in Paris, France, adjusted for seniority and company size." }, "location" : "Paris, Paris, France", "locations" : [ "Paris", "Paris", "France", "Luxembourg", "Luxembourg" ], "timestamp" : "2026-06-16T08:42:10.782", "fingerprint" : "b1f51f80173cae76b9cccef46c9568a510a484488397ffe02b77be0fc6befdce", "source" : "greenhouse", "language" : "fr", "applyUrl" : "https://job-boards.eu.greenhouse.io/ibanfirst/jobs/4897541101", "externalId" : "4897541101", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Paris", "country" : "France", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "48.8534951,2.3483915" } ], "locationText" : "Paris, France", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "professionalSkills" : [ "Due diligence", "Risk assessment" ], "hardSkillsList" : [ "AML", "KYC", "Onboarding" ], "hardSkills" : [ { "name" : "AML", "level" : "intermediate" }, { "name" : "KYC", "level" : "intermediate" }, { "name" : "Onboarding", "level" : "intermediate" } ], "majorSkills" : "AML/KYC, Funds onboarding, Complex structures", "majorSkillsList" : [ "AML/KYC", "Funds onboarding", "Complex structures" ], "coreResponsibilities" : "Perform due diligence, Onboard clients, Analyze client information, Document conclusions clearly, Challenge information, Make links between information, Support sales teams proactively, Write structured KYC reports in English", "teamCollaboration" : "Sales teams; Compliance teams; CSSF interlocutors; European team", "domainKnowledge" : "Funds; Complex structures; AML/KYC; CSSF reporting", "domainList" : [ "funds", "complex-structures", "aml-kyc", "cssf-reporting" ], "domainSpecificKnowledge" : [ "Funds", "Complex structures", "AML/KYC", "CSSF reporting" ], "communicationSkills" : "Written reports; Oral communication", "documentationSkills" : "KYC reports", "problemSolvingSkills" : "Analytical skills", "qualificationsBasic" : "5+ years experience in AML/KYC, Fluent English and French", "qualificationsPreferred" : "Experience with funds or complex structures in other European jurisdictions, Knowledge of CSSF regulatory reporting", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Qui sommes-nous ? iBanFirst est une fintech européenne en pleine croissance qui révolutionne les paiements internationaux pour les PME. Fondée en 2016, notre plateforme permet aux SMM (Small vous trouvez des solutions et accompagnez les équipes commerciales de manière proactive Rigueur et esprit analytique — vous challengez les informations, faites les liens et documentez vos conclusions avec clarté Autonomie et esprit entrepreneurial — vous êtes à l'aise dans une configuration où vous êtes la première recrue Due Diligence sur place ; vous faites avancer les choses sans attendre Excellent(e) communicant(e) — à l'écrit (rapports KYC structurés et clairs en anglais) comme à l'oral (Sales, Compliance, interlocuteurs CSSF) Esprit d'équipe — vous restez connecté(e) à l'équipe en Europe et contribuez activement au partage de connaissances Anglais et français courants — les deux sont indispensables Atouts supplémentaires : Expérience sur des fonds ou structures complexes dans d'autres juridictions européennes (France, Irlande, Pays-Bas…) Connaissance des dispositifs de reporting réglementaire de la CSSF Diplôme en Banque, Finance, Droit, Conformité, Économie ou domaine connexe Ce que nous offrons CDI Lieu : Luxembourg ou Paris Présence bureau : Présentiel majoritaire Avantages : \uD83D\uDCCD Paris Carte restaurant Swile Assurance santé AXA Prise en charge du titre de transport (50%) Abonnement Gymlib (WellPass) Participation aux événements d'entreprise : séminaires d'équipe, soirées et activités sociales régulières \uD83D\uDCCD Luxembourg Tickets restaurant Edenred Abonnement téléphonique Participation aux événements d'entreprise : séminaires d'équipe, soirées et activités sociales régulières Pourquoi c'est une belle opportunité : Construisez quelque chose qui n'existe pas encore — le Luxembourg est un nouveau chapitre stratégique pour iBanFirst ; vous serez l'un(e) des premiers membres de l'équipe locale et laisserez une empreinte durable Des dossiers techniques et à haute valeur ajoutée — fonds, PE, FIA, structures de titrisation ; un travail intellectuellement riche qui développe une vraie expertise chaque jour Autonomie sur le terrain — vous êtes la référence Due Diligence au Luxembourg, avec tout le soutien d'une équipe de 24 personnes en Europe derrière vous Trajectoire de carrière rapide — à mesure que le bureau de Luxembourg grandit, votre rôle évolue avec lui ; le management d'une équipe locale est un horizon naturel Travaillez dans l'un des premiers hubs financiers d'Europe — exposition quotidienne à l'écosystème des fonds luxembourgeois, à la CSSF et aux grandes institutions financières Environnement international — une équipe réellement multiculturelle répartie dans 14 bureaux européens Notre processus de recrutement Entretien de screening avec Malorie (Talent Acquisition Specialist) — 30 minutes – visio — Objectif : fit général, parcours, motivation, salaire, disponibilités Entretien approfondi avec Sabin (Team Lead KYC) + Sylvain (Team Lead Periodic Review) — 1 heure – visio ou présentiel — Objectif : expertise AML/KYC, connaissance des fonds luxembourgeois, orientation business, fit équipe Entretien final avec Yoann (Due Diligence Manager) + Peggy (Head of Regulatory Affairs) — 1 heure – visio ou présentiel — Objectif : alignement stratégique, validation de l'expertise réglementaire, fit avec l'équipe luxembourgeoise", "summaryDescription" : "Senior AML/KYC Onboarding Analyst, Funds & Complex Structures at iBanFirst. Skills: AML/KYC, Funds onboarding, Complex structures. Perform due diligence. Onboard clients", "postedDate" : "2026-06-15T23:20:24.655", "createdAt" : "2026-06-15T23:20:24.655", "lastUpdated" : "2026-06-16T08:42:10.782", "ingestTimestamp" : "2026-06-15T23:20:24.655", "mongoId" : "6a305733f292fd229cf3549b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "50k-75k", "hasSalary" : false, "allSkills" : [ "AML", "KYC", "Onboarding", "AML/KYC", "Funds onboarding", "Complex structures", "Due diligence", "Risk assessment", "Funds", "CSSF reporting" ], "skillCount" : 10, "jobCategory" : "finance", "jobSubcategory" : "accounting", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 287.57474, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "FinTech", "llmIndustryConfidence" : 0.95 }, { "id" : "6a21d8b774d8ee00a0d1d94a", "title" : "Senior Mixed Signal Design Engineer", "company" : "NVIDIA", "industry" : "Technology", "salary" : { "min" : 136000.0, "max" : 264500.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "US, CA, Santa Clara", "locations" : [ "US, CA, Santa Clara", "United States of America" ], "timestamp" : "2026-06-05T09:31:29.753", "fingerprint" : "6b107c4889f731a361604ec8d724ae3a5581e272226247c8bf7e101c19142c2f", "source" : "workday", "language" : "en", "applyUrl" : "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mixed-Signal-Design-Engineer_JR2018909", "externalId" : "JR2018909", "industryFunction" : { }, "locationPoint" : "45.16105,12.2989", "structuredLocations" : [ { "city" : "Santa Clara", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.2333253,-121.6846349" } ], "locationText" : "Santa Clara, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Master's", "experienceMinYears" : 2, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "CMOS, FINFET, Spectre, Hspice, Cadence, Finesim, XA", "professionalSkills" : [ "Circuit design", "System performance", "Silicon characterization", "Floorplan", "High-speed routing", "Post-silicon bring-up", "Debugging skills", "Analytical skills" ], "hardSkillsList" : [ "Analog design", "Mixed signal design", "Circuit verification", "Behavioral modeling", "Noise analysis", "Loop stability analysis", "Monte-carlo analysis" ], "hardSkills" : [ { "name" : "Analog design", "level" : "intermediate" }, { "name" : "Mixed signal design", "level" : "intermediate" }, { "name" : "Circuit verification", "level" : "intermediate" }, { "name" : "Behavioral modeling", "level" : "intermediate" }, { "name" : "Noise analysis", "level" : "intermediate" }, { "name" : "Loop stability analysis", "level" : "intermediate" }, { "name" : "Monte-carlo analysis", "level" : "intermediate" } ], "majorSkills" : "Mixed Signal Design, Analog Circuits, High Speed Interfaces", "majorSkillsList" : [ "Mixed Signal Design", "Analog Circuits", "High Speed Interfaces" ], "coreResponsibilities" : "Develop high speed interfaces, Implement high speed interfaces, Develop analog circuits, Implement analog circuits, Define circuit requirements, Complete design from schematic, Complete design from layout, Complete design from verification, Conduct schematic design, Take ownership for architecture, Take ownership for transistor design, Take ownership for verification, Optimize circuit to meet specifications, Work closely with layout engineers, Provide detailed floorplan, Provide guidance for matching, Provide guidance for high-speed routings, Support post-silicon bring-up, Support debugging", "teamCollaboration" : "Diverse team; Layout engineers", "domainKnowledge" : "Deep-submicron CMOS; FINFET process; High speed interfaces; Analog circuits; Mixed signal circuits", "domainList" : [ "deep-submicron-cmos", "finfet-process", "high-speed-interfaces", "analog-circuits", "mixed-signal-circuits" ], "domainSpecificKnowledge" : [ "Deep-submicron CMOS", "FINFET process", "High speed interfaces", "Analog circuits", "Mixed signal circuits" ], "toolProficiency" : [ "Spectre", "Hspice", "Cadence virtuoso", "Cadence IC design" ], "innovationCreativity" : "State of the art technology; Unique technology; Innovative integrated circuit designs", "problemSolvingSkills" : "Debugging; Analytical skills", "outcomesObjectives" : "Move the needle", "qualificationsBasic" : "Master's or PhD in Electrical Engineering, 2 years analog design experience, CMOS Analog / Mixed Signal Circuit Design Experience, Experience with design and verification tools, Experience crafting test bench environments, Behavioral modeling of analog and digital circuits, Debugging and analytical skills, Analog simulation for noise analysis, Analog simulation for loop stability analysis, Analog simulation for ac/dc/tran analysis, Analog simulation for monte-carlo analysis", "qualificationsPreferred" : "Interpersonal skills, Ability to work as a great teammate", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice and join us today! This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle! We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. **What you 'll be doing:** * Develop and implement high speed interfaces and analog circuits. You will have hands on experience taking innovative integrated circuit designs at data rates of 25Gbps and higher from concept through silicon characterization. * Help by defining circuit requirements and complete design from schematic, layout, and verification to characterization. * Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. * Take ownership for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. * Optimize circuit to meet the specifications for system performance. * Work closely with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. * Provide support for post-silicon bring-up and debugging. **What we need to see:** * Master and/or PhD of Science in Electrical Engineering, Computer Engineering or related field with strong analog design background (or equivalent experience) * 2 years analog design experience in industry * CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) * Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) * Experience in crafting test bench environments for component and top level circuit verification * Behavioral modeling of analog and digital circuits * Strong debugging and analytical skills * Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. * Strong interpersonal skills and ability & desire to work as a great teammate are huge plus. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and [benefits](https://www.nvidia.com/en-us/benefits/). Applications for this job will be accepted at least until June 7, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.", "summaryDescription" : "Senior Mixed Signal Design Engineer at NVIDIA. Skills: Mixed Signal Design, Analog Circuits, High Speed Interfaces. Develop high speed interfaces. Implement high speed interfaces", "postedDate" : "2026-06-03T23:52:02.420", "createdAt" : "2026-06-04T23:52:02.382", "lastUpdated" : "2026-06-05T09:31:29.753", "ingestTimestamp" : "2026-06-04T23:52:02.382", "mongoId" : "6a21d8b774d8ee00a0d1d94a", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mixed-Signal-Design-Engineer_JR2018909", "salaryAnnualMin" : 136000, "salaryAnnualMax" : 264500, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Analog design", "Mixed signal design", "Circuit verification", "Behavioral modeling", "Noise analysis", "Loop stability analysis", "Monte-carlo analysis", "Mixed Signal Design", "Analog Circuits", "High Speed Interfaces", "Circuit design", "System performance", "Silicon characterization", "Floorplan", "High-speed routing", "Post-silicon bring-up", "Debugging skills", "Analytical skills", "Deep-submicron CMOS", "FINFET process", "High speed interfaces", "Analog circuits", "Mixed signal circuits", "Spectre", "Hspice", "Cadence virtuoso", "Cadence IC design" ], "skillCount" : 27, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 287.28305, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2a688774d8ee00a0634841", "title" : "Principal Engineer: Mixed Signal Design (m/f/d)", "company" : "Micron Technology", "industry" : "Technology", "salary" : { "min" : 135000.0, "max" : 195000.0, "currency" : "EUR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Principal Engineer in Munich, Germany, adjusted for executive seniority and the technology industry." }, "location" : "Munich (MDC), Germany", "locations" : [ "Munich (MDC), Germany" ], "timestamp" : "2026-06-12T17:32:01.185", "fingerprint" : "9543394da46476241e72fd16b15462f05cfa49d6237dcfc87228a44a6f068c4a", "source" : "workday", "language" : "en", "applyUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Munich-MDC-Germany/Principal-Engineer--Mixed-Signal-Design--m-f-d-_JR91508", "externalId" : "JR91508", "industryFunction" : { }, "locationPoint" : "48.13743,11.57549", "structuredLocations" : [ { "city" : "Munich", "country" : "Germany", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "48.1371079,11.5753822" } ], "locationText" : "Munich, Germany", "employmentType" : "FULL_TIME", "minimumEducation" : "Master's", "experienceMinYears" : 10, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "DRAM, GDDR, DDR, Spice, Primesim, SystemVerilog, Design Compiler, PrimeTime, Xcelium, Spyglass, Python, TCL, Claude Code, Atlassian toolchain", "professionalSkills" : [ "Mixed signal design", "High-speed signaling", "DRAM design", "Interface definition", "Behavior definition", "Functional requirements", "Full-chip integration", "Silicon bring-up", "Design validation" ], "hardSkillsList" : [ "Transistor level design", "Gate level design", "RTL level design", "Functional verification", "Gate-level verification" ], "softSkillsList" : [ "Analytical skills" ], "hardSkills" : [ { "name" : "Transistor level design", "level" : "intermediate" }, { "name" : "Gate level design", "level" : "intermediate" }, { "name" : "RTL level design", "level" : "intermediate" }, { "name" : "Functional verification", "level" : "intermediate" }, { "name" : "Gate-level verification", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Analytical skills" } ], "majorSkills" : "Mixed Signal Design, DRAM Design, Semiconductor Physics", "majorSkillsList" : [ "Mixed Signal Design", "DRAM Design", "Semiconductor Physics" ], "coreResponsibilities" : "Design digital blocks, Design mixed signal blocks, Define interface requirements, Define behavior requirements, Define functional requirements, Collaborate with block owners, Ensure full-chip integration, Develop testbenches, Perform functional verification, Perform gate-level verification, Support silicon bring-up, Support design validation activities, Use AI-driven tools", "teamCollaboration" : "Cross-functional teams; International engineering environment", "domainKnowledge" : "Semiconductor physics; Digital circuit design; Mixed-signal circuit design; High-performance DRAM; Memory products", "domainList" : [ "semiconductor-physics", "digital-circuit-design", "mixed-signal-circuit-design", "high-performance-dram", "memory-products" ], "domainSpecificKnowledge" : [ "Semiconductor physics", "Digital circuit design", "Mixed-signal circuit design", "High-performance DRAM", "Memory products" ], "toolProficiency" : [ "Spice", "Primesim", "SystemVerilog", "Design Compiler", "PrimeTime", "Xcelium", "Spyglass", "Python", "TCL", "Claude Code", "Atlassian toolchain" ], "innovationCreativity" : "Individual creative freedom", "problemSolvingSkills" : "Analytical skills", "qualificationsBasic" : "Master’s degree or PhD, 10+ years experience, semiconductor physics fundamentals, digital and mixed-signal circuit design fundamentals, schematic/gate level design, schematic/gate level simulations, scripting languages, automation tools, analytical skills, ability to work independently, ability to work in cross-functional teams, comfortable working in international engineering environment", "qualificationsPreferred" : "Memory design experience", "remoteFriendly" : true, "workSiteFlexibility" : "Remote", "rawDescription" : "**Our vision is to transform how the world uses information to enrich life for** _**all**_**.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Department Overview** In our Munich Development Center for high-speed signaling, we develop, test, and characterize industry-leading DRAM memories for highperformance datacenter, AI, automotive, and gaming applications, within an international, highly innovative, and motivated development team that offers challenging tasks and individual creative freedom. **Role Overview** We are looking for a **Principal DRAM Design Engineer** to design and verify digital and mixed signal blocks for next‑generation memory products. You will work closely with architecture, integration, and verification teams to deliver high‑performance, high‑reliability DRAM solutions. **Responsibilities** * Design digital and mixed signal blocks for GDDR and DDR DRAM at transistor, gate and RTL levels. * Define interface, behavior, and functional requirements for mixed signal blocks. * Collaborate with block owners and integration teams to ensure full‑chip integration. * Develop testbenches. * Perform functional and gate‑level verification. * Support silicon bring‑up and design validation activities. * Use AI‑driven tools to streamline workflows and enhance design efficiency. **Required Qualifications** * Master’s degree or PhD in Electrical Engineering or related field. * 10+ years of experience in mixed signal design for semiconductor products. * Strong fundamentals in semiconductor physics and digital and mixed-signal circuit design. * Knowledge of common digital circuit concepts such as decoders, FIFOs, serial-to-parallel, parallel-to-serial converters, crossdomain synchronization techniques, error detection and correction codes, random data generators is beneficial * Experience with schematic/gate level design and simulations. * Experience with industry‑standard EDA tools (e.g., Spice, Primesim, SystemVerilog, Design Compiler, PrimeTime, Xcelium, Spyglass). * Experience with scripting languages and automation tools such as Python, TCL, Claude Code, Atlassian toolchain. * Strong analytical skills with the ability to work independently and in cross-functional teams. * Comfortable working in an international engineering environment. **Preferred Qualifications** * Memory design experience. The base salary range that Micron estimates it could pay in for this position full-time is: 101.000,00 € - 173.000,00 € per year. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for the position. In addition to base pay, the remuneration package also includes: eligibility for a variable plan subject to the personal achievement of objectives and the company's performance, and benefits, which -at the discretion of the company- currently include meal vouchers, corporate welfare, yearly allowance of remote working days, supplementary health insurance, life coverage, Employee Assistance Program. Please refer to this page to check our current benefit offering: [EMEA Benefits](https://www.micron.com/about/careers/emea-benefits) All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. Remuneration is determined by objective criteria, regardless of gender and of any other factor protected by applicable federal, state, or local laws. To request assistance with the application process and/or for reasonable accommodations, please contact [ _HRsupport_EMEA @micron.com_](mailto:HRsupport_EMEA@micron.com). Before uploading your CV to apply for this position, please review our [ _Applicant Privacy Notice_](https://www.micron.com/Privacy/applicant-Privacy-Notice) and [ _Employment Privacy Notice_](https://www.micron.com/Privacy/Employment-Privacy-Notice). Micron recruiters use review tools to identify your unique skill set based on the information in your CV, to inform the recruiter of skills you may have that are not listed on your CV (based on your career history and work experience), to supplement the information provided in your CV with information obtained from publicly accessible professional-oriented sources (such as your publicly available LinkedIn profile) and to assess how closely your skill set matches the defined skill set for this position. While submitting your CV through this platform is not obligatory, we encourage you to do so. If you do not want to benefit from the skill and qualification matching features, then you should not upload your CV through this platform. Instead, email your CV to [ _TA_EMEA @micron.com_](mailto:ta_emea@micron.com) along with the Req Id number listed in the job description. Your CV will be forwarded to the appropriate recruiter for review. Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc. **About Micron Technology, Inc.** We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life _for all_. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® brand. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit [_micron.com/careers_](http://micron.com/careers)", "summaryDescription" : "Principal Engineer: Mixed Signal Design (m/f/d) at Micron Technology. Skills: Mixed Signal Design, DRAM Design, Semiconductor Physics. Design digital blocks. Design mixed signal blocks", "postedDate" : "2026-06-09T15:42:49.386", "createdAt" : "2026-06-11T15:42:49.294", "lastUpdated" : "2026-06-12T17:32:01.185", "ingestTimestamp" : "2026-06-11T15:42:49.294", "mongoId" : "6a2a688774d8ee00a0634841", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://micron.wd1.myworkdayjobs.com/External/job/Munich-MDC-Germany/Principal-Engineer--Mixed-Signal-Design--m-f-d-_JR91508", "salaryBand" : "100k-150k", "hasSalary" : false, "allSkills" : [ "Transistor level design", "Gate level design", "RTL level design", "Functional verification", "Gate-level verification", "Analytical skills", "Mixed Signal Design", "DRAM Design", "Semiconductor Physics", "Mixed signal design", "High-speed signaling", "DRAM design", "Interface definition", "Behavior definition", "Functional requirements", "Full-chip integration", "Silicon bring-up", "Design validation", "Semiconductor physics", "Digital circuit design", "Mixed-signal circuit design", "High-performance DRAM", "Memory products", "Spice", "Primesim", "SystemVerilog", "Design Compiler", "PrimeTime", "Xcelium", "Spyglass", "Python", "TCL", "Claude Code", "Atlassian toolchain" ], "skillCount" : 34, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 284.6974, "daysOld" : 3, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a0dfc0a58b93c861ebec45a", "title" : "Senior Mixed Signal Design Engineer", "company" : "NVIDIA", "industry" : "Artificial Intelligence", "salary" : { "min" : 168000.0, "max" : 310500.0, "currency" : "USD", "frequency" : "yearly" }, "location" : "US, CA, Santa Clara", "locations" : [ "US, CA, Santa Clara", "United States of America" ], "timestamp" : "2026-05-20T21:49:59.183", "fingerprint" : "e93b1bbf94ebd1ff2ae60b6b5c0e8f58ed01be99fcb5aa0ef3d8b61f36d6d67a", "source" : "workday", "language" : "en", "applyUrl" : "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mixed-Signal-Design-Engineer_JR2000424", "externalId" : "JR2000424", "industryFunction" : { }, "locationPoint" : "45.16105,12.2989", "structuredLocations" : [ { "city" : "Santa Clara", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite" }, { "workMode" : "remote" } ], "locationText" : "Santa Clara, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Master of Science in Electrical Engineering, Computer Engineering or related field with analog design background (or equivalent experience)", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "high speed interfaces, analog circuits, integrated circuit designs, deep-submicron CMOS technologies, CMOS Analog / Mixed Signal Circuit Design, FINFET, analog and digital circuits, noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo", "professionalSkills" : [ "analytical skills" ], "hardSkillsList" : [ "analog design", "mixed-signal design", "schematic design", "layout", "verification", "characterization", "floorplan", "debugging" ], "softSkillsList" : [ "interpersonal skills", "ability & desire to work as a great teammate" ], "hardSkills" : [ { "name" : "analog design", "level" : "intermediate" }, { "name" : "mixed-signal design", "level" : "intermediate" }, { "name" : "schematic design", "level" : "intermediate" }, { "name" : "layout", "level" : "intermediate" }, { "name" : "verification", "level" : "intermediate" }, { "name" : "characterization", "level" : "intermediate" }, { "name" : "floorplan", "level" : "intermediate" }, { "name" : "debugging", "level" : "intermediate" } ], "softSkills" : [ { "name" : "interpersonal skills" }, { "name" : "ability & desire to work as a great teammate" } ], "majorSkills" : "mixed-signal design, analog circuits, high speed interfaces", "majorSkillsList" : [ "mixed-signal design", "analog circuits", "high speed interfaces" ], "coreResponsibilities" : "Develop and implement high speed interfaces and analog circuits, hands on experience taking innovative integrated circuit designs at data rates of 25Gbps and higher from concept through silicon characterization, defining circuit requirements, complete design from schematic, layout, and verification to characterization, Conduct schematic design of deep-submicron CMOS technologies, Take ownership for the architecture, transistor design and verification, Optimize circuit to meet the specifications for system performance, Work closely with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings, Provide support for post-silicon bring-up and debugging", "teamCollaboration" : "Work closely with layout engineers; ability & desire to work as a great teammate", "domainKnowledge" : "mixed-signal design; deep-submicron CMOS technologies; FINFET", "domainList" : [ "mixed-signal-design", "deep-submicron-cmos-technologies", "finfet" ], "domainSpecificKnowledge" : [ "mixed-signal design", "deep-submicron CMOS technologies", "FINFET" ], "toolProficiency" : [ "Spectre", "Hspice", "Cadence virtuoso", "Cadence's IC design environment", "Finesim", "XA" ], "innovationCreativity" : "innovative integrated circuit designs", "problemSolvingSkills" : "analytical skills", "outcomesObjectives" : "Optimize circuit to meet the specifications for system performance", "qualificationsBasic" : "Minimum of 5 years analog design experience in industry, CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET), Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA), Experience in crafting test bench environments for component and top level circuit verification, Behavioral modeling of analog and digital circuits, debugging and analytical skills, Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc.", "qualificationsPreferred" : "interpersonal skills and ability & desire to work as a great teammate are huge plus", "remoteFriendly" : true, "workSiteFlexibility" : "No", "rawDescription" : "NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice and join us today! This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle! We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. **What you 'll be doing:** * Develop and implement high speed interfaces and analog circuits. You will have hands on experience taking innovative integrated circuit designs at data rates of 25Gbps and higher from concept through silicon characterization. * Help by defining circuit requirements and complete design from schematic, layout, and verification to characterization. * Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. * Take ownership for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. * Optimize circuit to meet the specifications for system performance. * Work closely with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. * Provide support for post-silicon bring-up and debugging. **What we need to see:** * Hold a Master of Science in Electrical Engineering, Computer Engineering or related field with strong analog design background (or equivalent experience) * Minimum of 5 years analog design experience in industry * CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) * Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) * Experience in crafting test bench environments for component and top level circuit verification * Behavioral modeling of analog and digital circuits * Strong debugging and analytical skills * Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. * Strong interpersonal skills and ability & desire to work as a great teammate are huge plus. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and [benefits](https://www.nvidia.com/en-us/benefits/). Applications for this job will be accepted at least until May 4, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.", "summaryDescription" : "Senior Mixed Signal Design Engineer at NVIDIA. Skills: mixed-signal design, analog circuits, high speed interfaces. Develop and implement high speed interfaces and analog circuits. hands on experience taking innovative integrated circuit designs at data rates of 25Gbps and higher from concept through silicon characterization", "postedDate" : "2026-04-30T21:44:16.154", "createdAt" : "2026-05-20T21:44:16.141", "lastUpdated" : "2026-05-20T21:49:59.183", "ingestTimestamp" : "2026-05-20T21:44:16.141", "mongoId" : "6a0dfc0a58b93c861ebec45a", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mixed-Signal-Design-Engineer_JR2000424", "salaryAnnualMin" : 168000, "salaryAnnualMax" : 310500, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "analog design", "mixed-signal design", "schematic design", "layout", "verification", "characterization", "floorplan", "debugging", "interpersonal skills", "ability & desire to work as a great teammate", "analog circuits", "high speed interfaces", "analytical skills", "deep-submicron CMOS technologies", "FINFET", "Spectre", "Hspice", "Cadence virtuoso", "Cadence's IC design environment", "Finesim", "XA" ], "skillCount" : 21, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 283.38757, "daysOld" : 20, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Artificial Intelligence" }, { "id" : "6a1a4ed558b93c861e7e1259", "title" : "Principal Mixed-Signal Design Engineer", "company" : "Analog Devices, Inc.", "industry" : "semiconductor", "salary" : { "min" : 9.0, "max" : 9.0, "currency" : "USD", "frequency" : "yearly" }, "location" : "Germany, Munich, Otl-Aicher-Strasse", "locations" : [ "Germany, Munich, Otl-Aicher-Strasse" ], "timestamp" : "2026-05-30T06:24:07.684", "fingerprint" : "807ca2078d71251554abfa7561fcef621b1c2f8cd8aa07c0022062f452d997e3", "source" : "workday", "language" : "en", "applyUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/Germany-Munich-Otl-Aicher-Strasse/Principal-Mixed-Signal-Design-Engineer_R260358", "externalId" : "R260358", "industryFunction" : { }, "locationPoint" : "48.13743,11.57549", "structuredLocations" : [ { "city" : "Munich", "country" : "Germany", "continent" : "eu", "source" : "llm", "workMode" : "onsite" } ], "locationText" : "Munich, Germany", "employmentType" : "FULL_TIME", "minimumEducation" : "MS Electrical Engineering", "experienceMinYears" : 10, "experienceMaxYears" : 15, "experienceLevel" : "Lead", "technicalSkills" : "Mixed-Signal, ADC, DAC, SerDes PHY, SoC, FinFET", "professionalSkills" : [ "technical leadership", "teamwork", "communication skills" ], "hardSkillsList" : [ "mixed-signal integrated circuit development", "data converter architectures", "SerDes PHY architectures", "mixed-signal design fundamentals", "design tools", "methodologies", "integrated circuit product development", "design", "verification", "evaluation", "test", "qualification" ], "hardSkills" : [ { "name" : "mixed-signal integrated circuit development", "level" : "intermediate" }, { "name" : "data converter architectures", "level" : "intermediate" }, { "name" : "SerDes PHY architectures", "level" : "intermediate" }, { "name" : "mixed-signal design fundamentals", "level" : "intermediate" }, { "name" : "design tools", "level" : "intermediate" }, { "name" : "methodologies", "level" : "intermediate" }, { "name" : "integrated circuit product development", "level" : "intermediate" }, { "name" : "design", "level" : "intermediate" }, { "name" : "verification", "level" : "intermediate" }, { "name" : "evaluation", "level" : "intermediate" }, { "name" : "test", "level" : "intermediate" }, { "name" : "qualification", "level" : "intermediate" } ], "majorSkills" : "Mixed-Signal Design, Integrated Circuits, Data Converters, SerDes PHY", "majorSkillsList" : [ "Mixed-Signal Design", "Integrated Circuits", "Data Converters", "SerDes PHY" ], "coreResponsibilities" : "Develop mixed-signal subsystem implementation architectures, Design transistor-level mixed-signal integrated circuits, Prepare design documents, Conduct design reviews, Lead mixed-signal integrated circuit subsystem development, Mentor mixed-signal design engineers, Guide mixed-signal integrated circuit layout, Guide mixed-signal integrated circuit evaluation, Guide mixed-signal integrated circuit test", "teamCollaboration" : "work with product team", "domainKnowledge" : "data converter architectures; SerDes PHY architectures; mixed-signal design fundamentals; integrated circuit product development", "domainList" : [ "data-converter-architectures", "serdes-phy-architectures", "mixed-signal-design-fundamentals", "integrated-circuit-product-development" ], "domainSpecificKnowledge" : [ "data converter architectures", "SerDes PHY architectures", "mixed-signal design fundamentals", "integrated circuit product development" ], "toolProficiency" : [ "design tools" ], "communicationSkills" : "communication skills", "documentationSkills" : "design documents", "innovationCreativity" : "innovative; state of the art; high-performance circuits", "specialRequirements" : "export licensing approval", "qualificationsBasic" : "MS Electrical Engineering, 10+ years of mixed-signal integrated circuit development experience, Deep understanding of data converter architectures and specifications, Deep understanding of SerDes PHY architectures and specifications, Deep understanding of mixed-signal design fundamentals, Deep understanding of design tools, Deep understanding of methodologies, Solid understanding of integrated circuit product development, Solid understanding of design, Solid understanding of verification, Solid understanding of evaluation, Solid understanding of test, Solid understanding of qualification, Successful experience developing challenging mixed-signal integrated circuits for commercial applications", "remoteFriendly" : false, "rawDescription" : "**About Analog Devices** Analog Devices, Inc. (NASDAQ: _[ADI](http://finance.yahoo.com/q?s=ADI)_ ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at _[www.analog.com](https://www.analog.com/)_ and on _[LinkedIn](https://www.linkedin.com/company/analog-devices/posts/?feedView=all)_ and _[Twitter (X)](https://x.com/adi_news)_. **Principal Mixed-Signal Design Engineer** **Job Duties and Responsibilities** As a Principal Mixed-Signal Design Engineer within the Advanced Cores Group (ACG) you will work on the development of ADC, DAC, and/or SerDes PHY subsystems for highly sophisticated mixed-signal system-on-chip (SoC) integrated circuit products using FinFET wafer technologies. The Advanced Cores Group develops innovative, state of the art, high-performance circuits as often shown by presentations at premier conferences and publications in premier journals. Your work will include: * Developing and selecting mixed-signal subsystem implementation architectures. * Designing challenging transistor-level mixed-signal integrated circuits. * Preparing effective design documents and conduct effective design reviews. * Leading mixed-signal integrated circuit subsystem development efforts. * Mentoring mixed-signal design engineers. * Guiding mixed-signal integrated circuit layout. * Guiding mixed-signal integrated circuit evaluation and test. **Qualifications** * MS Electrical Engineering. * 10+ years of mixed-signal integrated circuit development experience. * Deep understanding of data converter architectures and specifications and/or deep understanding of SerDes PHY architectures and specifications * Deep understanding of mixed-signal design fundamentals, design tools, and methodologies. * Solid understanding of integrated circuit product development, including design, verification, evaluation, test, and qualification. * Successful experience developing challenging mixed-signal integrated circuits for commercial applications. * Strong technical leadership, teamwork, and communication skills. _For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process._ _Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group._ Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days", "summaryDescription" : "Principal Mixed-Signal Design Engineer at Analog Devices, Inc.. Skills: Mixed-Signal Design, Integrated Circuits, Data Converters, SerDes PHY. Develop mixed-signal subsystem implementation architectures. Design transistor-level mixed-signal integrated circuits", "postedDate" : "2026-05-15T06:09:53.210", "createdAt" : "2026-05-30T06:09:53.183", "lastUpdated" : "2026-05-30T06:24:07.684", "ingestTimestamp" : "2026-05-30T06:09:53.183", "mongoId" : "6a1a4ed558b93c861e7e1259", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://analogdevices.wd1.myworkdayjobs.com/External/job/Germany-Munich-Otl-Aicher-Strasse/Principal-Mixed-Signal-Design-Engineer_R260358", "salaryAnnualMin" : 18720, "salaryAnnualMax" : 18720, "salaryBand" : "<30k", "hasSalary" : true, "allSkills" : [ "mixed-signal integrated circuit development", "data converter architectures", "SerDes PHY architectures", "mixed-signal design fundamentals", "design tools", "methodologies", "integrated circuit product development", "design", "verification", "evaluation", "test", "qualification", "Mixed-Signal Design", "Integrated Circuits", "Data Converters", "SerDes PHY", "technical leadership", "teamwork", "communication skills" ], "skillCount" : 19, "jobCategory" : "engineering", "seniorityLevel" : "senior", "dataQualityScore" : 1.0, "_score" : 280.3209, "daysOld" : 15, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "semiconductor" } ], "status" : 200, "message" : "OK", "pagination" : { "page" : 0, "limit" : 50, "totalCount" : 39539, "totalPages" : 791, "hasNext" : true, "hasPrevious" : false } }

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