Renesas Electronics

Tech / AI / Software

Sr.StaffLayoutEngineer

toyosu, tokyo, japan FULL TIME
The Brief

“Sr. Staff Layout Engineer at Renesas Electronics. Skills: floor planning, layout of complex mixed signal circuits and systems, Routing and verification (DRC, ERC, Antenna & LVS). take technical lead on floor planning and layout of complex mixed signal circuits and systems. lead layout projects as appropriate”

What You'll Achieve.

yield optimization; ESD robustness; deliver on-time under tight schedule

Industry & Context.

Tech / AI / Software
Problems you'll solve

Ability to make good judgement in selecting method/technique for obtaining solutions

What They're Looking For.

Must Have

Typically 7-10 years experience, Demonstrate expertise in the required CAD tools (Virtuoso XL/Calibre DRC, LVS & PEX/VCAR/VSR/PVS/R3D), Strong competence with various tools and procedures, reaching specialist level, Ability to make good judgement in selecting method/technique for obtaining solutions, Ability to support and mentor less experienced team members

Nice to Have

Results-oriented and able to deliver on-time under tight schedule, Ability to work both independently and part of a team, Ability to make good judgement in selecting method/technique for obtaining solutions, Strong competence with various tools and procedures, reaching specialist level

What You'll Do.

take technical lead on floor planning and layout of complex mixed signal circuits and systems

lead layout projects as appropriate

support layout team members with guidance in layout best practice

drive identification and implementation of improvements

Lead floor planning of all levels of layout work (chip

block and cell) in collaboration with TPL and relevant designers

Work as lead layout engineer on a project

supporting TPL from initial feasibility work through to tape out

Champion state-of-the-art layout techniques for matching accuracy

yield optimization and ESD robustness in any project you are responsible for

Routing and verification (DRC

Antenna & LVS) of chip

block and cell level layout

Responsible for high quality and efficient layout reviews with TPL

Layout Manager and other key stakeholders

report and present recommendations for progress against project plan

key risk and any issues that arise

Working closely in collaboration with colleagues in design and layout to ensure effective communication and alignment on block and cell requirements

Guide a large team of engineers whilst working as lead layout engineer and act as a mentor for less experienced layout engineers

How You'll Work.

Team & Collaboration

lead layout projects; support layout team members with guidance in layout best practice; drive identification and implementation of improvements; lead floor planning of all levels of layout work (chip, block and cell) in collaboration with TPL and relevant designers; support TPL from initial feasibility work through to tape out; Responsible for high quality and efficient layout reviews with TPL, Layout Manager and other key stakeholders; Working closely in collaboration with colleagues in design and layout to ensure effective communication and alignment on block and cell requirements; Guide a large team of engineers whilst working as lead layout engineer and act as a mentor for less experienced layout engineers

Communication Scope

Responsible for high quality and efficient layout reviews with TPL, Layout Manager and other key stakeholders; Monitor, report and present recommendations for progress against project plan, key risk and any issues that arise; ensure effective communication and alignment on block and cell requirements

Process & Methodology

lead layout projects, Monitor, report and present recommendations for progress against project plan, key risk and any issues that arise

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