Weekday AI
CustomLayoutEngineer
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optimal for Senior candidates.
“Custom Layout Engineer at Weekday AI. Skills: Analog layout design, Mixed-signal layout design, Cadence Virtuoso. Develop custom analog layouts. Implement custom analog layouts”
Industry & Context.
Analytical skills; Problem-solving skills
What They're Looking For.
Must Have
4+ years analog layout design, Cadence Virtuoso proficiency, DRC knowledge, LVS knowledge, Physical verification knowledge
Nice to Have
VXL familiarity, Layout verification tools familiarity, Debugging physical design issues familiarity
What You'll Do.
Develop custom analog layouts
Implement custom analog layouts
Develop mixed-signal layouts
Implement mixed-signal layouts
Create transistor-level layouts
Perform floorplanning
Perform device placement
Ensure layout compliance
Resolve physical verification issues
Work with schematic designers
Implement layout solutions
Optimize layouts for area
Optimize layouts for performance
Optimize layouts for yield
Optimize layouts for power
Optimize layouts for manufacturability
Execute parasitic-aware layout techniques
Support extraction activities
Support post-layout verification
Collaborate with design teams
Collaborate with verification teams
Collaborate with technology teams
Maintain design documentation
Maintain layout methodologies
Maintain best practices
Support tape-out activities
Contribute to process improvements
Provide technical feedback
Ensure quality standards adherence
How You'll Work.
Team & Collaboration
Cross-functional teams; Design teams; Verification teams; Technology teams
Full Job Description
**This role is for one of the Weekday's clients** **Salary range: Rs 200000 - Rs 1800000 (ie INR 2-18 LPA)** Experience: 4+ yrs Location: Hyderabad Job Type: full-time We are looking for a highly skilled **Custom Layout Engineer** with strong expertise in **analog and mixed-signal layout design** to contribute to the development of advanced semiconductor products. In this role, you will be responsible for creating high-quality custom layouts for complex analog, mixed-signal, and custom digital circuits while ensuring compliance with design specifications, process requirements, and quality standards. You will work closely with circuit designers, verification engineers, and cross-functional teams to transform schematics into optimized physical layouts that meet performance, area, power, reliability, and manufacturability goals. This position is ideal for professionals who are passionate about physical design, layout optimization, and solving challenging semiconductor design problems in a fast-paced engineering environment. The role offers the opportunity to work on cutting-edge technologies, contribute to full-chip and block-level layout development, and play a critical role in delivering high-performance silicon products. **Requirements** ### Key Responsibilities * Develop and implement custom analog and mixed-signal layouts using **Cadence Virtuoso**. * Create transistor-level layouts for analog, RF, memory, and custom digital circuit blocks. * Perform floorplanning, device placement, routing, matching, shielding, and layout optimization to meet performance targets. * Ensure layouts comply with foundry design rules, process requirements, and reliability guidelines. * Conduct and resolve **DRC (Design Rule Check)** , **LVS (Layout Versus Schematic)** , and physical verification issues. * Work with schematic designers to understand circuit requirements and implement efficient layout solutions. * Optimize layouts for area, performance, yield, power consumption, and man
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