{ "count" : 197850, "data" : [ { "id" : "6a25146374d8ee00a00bb795", "title" : "Manager, ASIC Sustaining Engineering, Silicon Operations", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Project/Program/Product Management--Non-Tech, Technical Program Management, alexa and amazon devices", "salary" : { "min" : 188100.0, "max" : 254500.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Sunnyvale, California, USA", "locations" : [ "Sunnyvale, California, USA" ], "timestamp" : "2026-06-16T02:31:10.897", "fingerprint" : "13c9edad2061c93830d4ae49a9816fa0e007ed778273cc6d155568a5a7b94e9b", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10440379/apply", "externalId" : "d7941625-42d7-4bfb-9d41-b1546071f1aa", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceLevel" : "Manager", "technicalSkills" : "Semiconductor manufacturing, ASIC, Silicon, Process control, Yield enhancement, Failure analysis, Statistical process control, Data analysis, Manufacturing execution systems, Python, SQL", "professionalSkills" : [ "Problem-solving", "Analytical skills", "Project management", "Cross-functional collaboration" ], "hardSkillsList" : [ "Semiconductor fabrication", "Statistical analysis", "Root cause analysis" ], "hardSkills" : [ { "name" : "Semiconductor fabrication", "level" : "intermediate" }, { "name" : "Statistical analysis", "level" : "intermediate" }, { "name" : "Root cause analysis", "level" : "intermediate" } ], "majorSkills" : "ASIC Sustaining Engineering, Silicon Operations, Semiconductor Manufacturing", "majorSkillsList" : [ "ASIC Sustaining Engineering", "Silicon Operations", "Semiconductor Manufacturing" ], "coreResponsibilities" : "Manage ASIC sustaining engineering activities, Drive silicon operations improvements, Analyze manufacturing data, Identify and resolve yield issues, Implement process control strategies, Collaborate with cross-functional teams, Develop and maintain manufacturing documentation, Support new product introductions", "teamCollaboration" : "Cross-functional teams; Engineering teams; Manufacturing teams; Product teams", "projectManagementSkills" : [ "Agile methodologies", "Project planning", "Risk management" ], "domainKnowledge" : "Semiconductor manufacturing; ASIC design; Silicon technology; Process control; Yield management; Failure analysis; Manufacturing execution systems", "domainList" : [ "semiconductor-manufacturing", "asic-design", "silicon-technology", "process-control", "yield-management", "failure-analysis", "manufacturing-execution-systems" ], "domainSpecificKnowledge" : [ "Semiconductor manufacturing", "ASIC design", "Silicon technology", "Process control", "Yield management", "Failure analysis", "Manufacturing execution systems" ], "toolProficiency" : [ "JIRA", "SQL", "Python" ], "communicationSkills" : "Technical presentations; Status reports", "documentationSkills" : "Technical documentation; Process documentation", "problemSolvingSkills" : "Root cause analysis; Troubleshooting; Data analysis", "outcomesObjectives" : "Improve manufacturing yield; Reduce production costs; Enhance product reliability; Ensure timely product delivery", "qualificationsBasic" : "Bachelor's degree or equivalent practical experience, 5+ years of experience in semiconductor manufacturing, Experience with ASIC sustaining engineering, Experience with silicon operations", "qualificationsPreferred" : "Master's degree or PhD, Experience with yield enhancement, Experience with process control, Experience with failure analysis, Experience with manufacturing execution systems (MES)", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Leo is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. The Silicon Operations team is seeking a Manager,ASIC Sustaining Engineer who has the responsibility for Yield improvement to meet or beat target and Root Cause Analysis for Yield excursions across Wafer, Assembly and Test. Use statistical tools and data analysis to identify yield limiters and trends in electrical test and in-line inspection data. Conduct failure analysis (FA) on defective wafers and devices to identify the source of, or prevent, yield excursions. Design and execute experiments (DOE) to optimize manufacturing processes and reduce particle contamination. Partner with process, equipment, and design engineers to implement solutions to improve, maintain, or troubleshoot production lines. Install, qualify, and maintain in-line defect inspection and review equipment. Create and maintain specifications, process documentation, and best-known methods Key job responsibilities Lead team to identify root cause for chip performance / yield / quality issues. Analyze CP test bin / data log to identify failure mode. Electrical failure analysis and physical failure analysis to locate suspect process stage Work with appropriate supplier to define corrective actions / solutions. Trace action implementation to verify effectiveness. Product early-stage design support to help product tape-out smoothly and Si success: Design rule review & assessment for robust product design Layout review or DFM to enlarge manufacturing window Yield window characterization and device sweet spot identification for the best yield / performance process condition. Basic Qualifications: - 5+ years of people management experience - 5+ years of technical program management experience - Bachelor's degree in Engineering, Computer Science, or a related technical field - Experience managing efforts in Unix/Linux environments, distributed systems or developing large-scale web applications Preferred Qualifications: - Knowledge of the AWS product suite - Knowledge of data center infrastructure design, operations, or delivery - Experience communicating across technical and non-technical audiences, including executive level stakeholders or clients - Experience managing projects across cross functional teams, building sustainable processes and coordinating release schedules - Experience with Agile or other program management methodologies Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Sunnyvale - 188,100.00 - 254,500.00 USD annually USA, WA, Bellevue - 163,600.00 - 221,300.00 USD annually", "summaryDescription" : "Manager, ASIC Sustaining Engineering, Silicon Operations at Amazon Kuiper Manufacturing Enterprises LLC. Skills: ASIC Sustaining Engineering, Silicon Operations, Semiconductor Manufacturing. Manage ASIC sustaining engineering activities. Drive silicon operations improvements", "postedDate" : "2026-06-14T20:21:31.739", "createdAt" : "2026-06-14T20:21:31.739", "lastUpdated" : "2026-06-16T02:31:10.897", "ingestTimestamp" : "2026-06-14T20:21:31.739", "mongoId" : "6a25146374d8ee00a00bb795", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10440379/apply", "salaryAnnualMin" : 188100, "salaryAnnualMax" : 254500, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Semiconductor fabrication", "Statistical analysis", "Root cause analysis", "ASIC Sustaining Engineering", "Silicon Operations", "Semiconductor Manufacturing", "Problem-solving", "Analytical skills", "Project management", "Cross-functional collaboration", "Agile methodologies", "Project planning", "Risk management", "Semiconductor manufacturing", "ASIC design", "Silicon technology", "Process control", "Yield management", "Failure analysis", "Manufacturing execution systems", "JIRA", "SQL", "Python" ], "skillCount" : 23, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Manager", "dataQualityScore" : 1.0, "_score" : 2207.6472, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "69fda4e54c40e2acd1b99a29", "title" : "ASIC Sustaining Engineering Manager", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Project/Program/Product Management--Non-Tech, ASIC, alexa and amazon devices", "salary" : { "min" : 183000.0, "max" : 247600.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Sunnyvale, California, USA", "locations" : [ "Sunnyvale, California, USA" ], "timestamp" : "2026-06-15T05:02:55.478", "fingerprint" : "5f2038f1344f247178469cff2c20f373ce729cec3ec3d46b7ef9c42c82bdb298", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10412733/apply", "externalId" : "d5cba53a-1ed7-4876-afa4-d0caedefcd43", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "employmentType" : "FULL_TIME", "experienceLevel" : "Manager", "technicalSkills" : "ASIC, FPGA, RTL, AI tools", "professionalSkills" : [ "Supply Chain Management", "Cross-Functional Collaboration", "Relationship Management", "Production Operations", "Issue Management", "Quality Optimization", "Yield Optimization", "Cost Reduction", "Supplier Management", "Capacity Scaling", "Data Analytics" ], "hardSkillsList" : [ "Synthesis", "STA", "Physical design", "RTL coding", "RTL debug", "Performance analysis", "Power analysis", "Area analysis", "SOC bring-up", "Post-silicon validation" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Synthesis", "level" : "intermediate" }, { "name" : "STA", "level" : "intermediate" }, { "name" : "Physical design", "level" : "intermediate" }, { "name" : "RTL coding", "level" : "intermediate" }, { "name" : "RTL debug", "level" : "intermediate" }, { "name" : "Performance analysis", "level" : "intermediate" }, { "name" : "Power analysis", "level" : "intermediate" }, { "name" : "Area analysis", "level" : "intermediate" }, { "name" : "SOC bring-up", "level" : "intermediate" }, { "name" : "Post-silicon validation", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "ASIC Sustaining Engineering, Supply Chain, Operations Management", "majorSkillsList" : [ "ASIC Sustaining Engineering", "Supply Chain", "Operations Management" ], "coreResponsibilities" : "Lead offshore sustain engineers, Provide KPI, Provide technical training, Provide motivation, Build trust-based relationships, Maintain urgency, Maintain accountability, Solve complex problems, Partner with NPI teams, Partner with OSAT teams, Establish work models, Establish ownership, Establish expectations, Collaborate with NPI engineers, Debug test issues, Prioritize production needs, Manage SW/HW consignment, Respond to daily production issues, Determine local resolution needs, Determine NPI escalation needs, Establish JIRA workflows, Enable priority-setting, Identify quality concerns, Highlight yield improvement opportunities, Drive continuous improvement initiatives, Monitor production metrics, Alert stakeholders to deviations, Support cost reduction campaigns, Reduce test time, Implement multi-site testing, Simplify hardware, Eliminate cost adders, Eliminate redundant work, Eliminate material waste, Improve throughput, Improve resource utilization, Define capacity scaling criteria, Evaluate OSAT partners, Qualify new OSAT sources, Leverage internal systems, Query yield data, Query consignment status, Implement automated alerts", "teamCollaboration" : "Cross-functional stakeholders; NPI teams; OSAT teams; Cross-functional teams", "projectManagementSkills" : [ "Agile" ], "domainKnowledge" : "Deep sub-micron nodes; ASIC/FPGA design; SOC architecture; LEO satellites; Broadband access", "domainList" : [ "deep-sub-micron-nodes", "asic-fpga-design", "soc-architecture", "leo-satellites", "broadband-access" ], "domainSpecificKnowledge" : [ "Deep sub-micron nodes", "ASIC/FPGA design", "SOC architecture", "LEO satellites", "Broadband access" ], "toolProficiency" : [ "JIRA" ], "communicationSkills" : "Communicate effectively; Communicate respectfully", "problemSolvingSkills" : "Solve complex problems", "specialRequirements" : "U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S. as refugee, Lawfully admitted into the U. S. as granted asylum", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, 7+ years ASIC implementation experience, 7+ years synthesis experience, 7+ years STA experience, 7+ years physical design experience, Deep sub-micron nodes experience, U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S. as refugee, Lawfully admitted into the U. S. as granted asylum", "qualificationsPreferred" : "Master's degree or Ph. D. degree, Experience in RTL coding, Experience in RTL debug, Experience with performance analysis, Experience with power analysis, Experience with area analysis, Experience with modern ASIC design tools, Experience with modern FPGA design tools, Experience with SOC bring-up, Experience with post-silicon validation", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon Leo is an initiative to increase global broadband access through a constellation of 3,236 satellites in low Earth orbit (LEO). Its mission is to bring fast, affordable broadband to unserved and underserved communities around the world. Amazon Leo will help close the digital divide by delivering fast, affordable broadband to a wide range of customers, including consumers, businesses, government agencies, and other organizations operating in places without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. The Amazon Leo Supply Chain team is looking for a ASIC Sustaining Engineering Manager Lead offshore sustain engineers by providing KPI, technical training and motivation. The ideal candidate will have a successful track record building trust-based relationships while maintaining urgency and accountability. Experience working in new and ambiguous environments while solving complex problems with a broad range of cross functional stakeholders will also be an advantage. Key job responsibilities Cross-Functional Collaboration & Relationship Management • Partner with NPI and OSAT teams to establish clear work models, ownership, and expectations • Build trust-based relationships with OSAT while maintaining urgency and accountability • Collaborate with NPI engineers on test issue debugging while prioritizing production needs Production Operations & Issue Management • Manage SW/HW consignment to OSAT and respond to daily production issues (yield, QA failures, line downtime, data issues, logistics) • Determine whether issues require local resolution or NPI escalation • Establish and maintain JIRA workflows that enable priority-setting in dynamic situations Quality & Yield Optimization • Proactively identify quality concerns from OSAT reports and site visits (repetitive failures, abnormal behavior changes) • Highlight yield improvement opportunities and drive continuous improvement initiatives • Monitor production metrics and alert stakeholders to deviations from targets Cost Reduction & Efficiency • Support NPI cost reduction campaigns (test time reduction, multi-site testing, hardware simplification) • Identify and eliminate cost adders, redundant work, and material waste • Improve throughput and resource utilization Supplier Management & Scaling • Define capacity scaling criteria for OSAT partners • Evaluate and qualify new OSAT sources using defined metrics, execution plans, and correlation reports Data & Analytics • Leverage internal production monitoring systems to query real-time yield data and consignment status across multiple OSAT sites • Implement automated alerts using AI tools to notify stakeholders of missed targets Basic Qualifications: - Bachelor's degree in Electrical Engineering or a related field - 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience Preferred Qualifications: - Master's degree or Ph.D. degree in Electrical Engineering or related field - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs - Experience with modern ASIC/FPGA design and verification tools - Experience with SOC bring-up and post-silicon validation Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Sunnyvale - 183,000.00 - 247,600.00 USD annually", "summaryDescription" : "ASIC Sustaining Engineering Manager at Amazon Kuiper Manufacturing Enterprises LLC. Skills: ASIC Sustaining Engineering, Supply Chain, Operations Management. Lead offshore sustain engineers. Provide KPI", "postedDate" : "2026-06-13T17:19:52.447", "createdAt" : "2026-06-13T17:19:52.447", "lastUpdated" : "2026-06-15T05:02:55.478", "ingestTimestamp" : "2026-06-13T17:19:52.447", "mongoId" : "69fda4e54c40e2acd1b99a29", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10412733/apply", "salaryAnnualMin" : 183000, "salaryAnnualMax" : 247600, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Synthesis", "STA", "Physical design", "RTL coding", "RTL debug", "Performance analysis", "Power analysis", "Area analysis", "SOC bring-up", "Post-silicon validation", "Leadership", "ASIC Sustaining Engineering", "Supply Chain", "Operations Management", "Supply Chain Management", "Cross-Functional Collaboration", "Relationship Management", "Production Operations", "Issue Management", "Quality Optimization", "Yield Optimization", "Cost Reduction", "Supplier Management", "Capacity Scaling", "Data Analytics", "Agile", "Deep sub-micron nodes", "ASIC/FPGA design", "SOC architecture", "LEO satellites", "Broadband access", "JIRA" ], "skillCount" : 32, "jobCategory" : "project-management", "dataQualityScore" : 1.0, "_score" : 1235.1849, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a210e2a74d8ee00a0af6036", "title" : "ASIC RTL Engineer III, Silicon", "industry" : "Technology", "salary" : { "min" : 2200000.0, "max" : 3500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for an ASIC RTL Engineer III in Bengaluru, India, adjusted for senior experience level and the technology industry." }, "location" : "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]", "locations" : [ "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]" ], "timestamp" : "2026-06-16T12:38:57.194", "fingerprint" : "b1c262870b66bac5501f455e543653ca477782b2a2ac7bc4e11cfd5092ae36a3", "source" : "google", "language" : "en", "externalId" : "131996864789521094", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "summaryDescription" : "ASIC RTL Engineer III, Silicon", "postedDate" : "2026-06-16T01:48:27.632", "createdAt" : "2026-06-16T01:48:27.632", "lastUpdated" : "2026-06-16T12:38:57.194", "ingestTimestamp" : "2026-06-16T01:48:27.632", "mongoId" : "6a210e2a74d8ee00a0af6036", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.5555556, "_score" : 1097.752, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a307f0ff292fd229c054d87", "title" : "ASIC Digital Design Engineer II, Silicon Engineering", "salary" : { "min" : 1500000.0, "max" : 2500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level ASIC Digital Design Engineer II in Bengaluru, India, adjusted for junior seniority and the technology industry." }, "location" : "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]", "locations" : [ "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]" ], "timestamp" : "2026-06-16T13:54:47.479", "fingerprint" : "2ecc3608c118362ad239e3b34577ec9617c62ae40d66399eb245225548e9594c", "source" : "google", "language" : "en", "externalId" : "140959387895112390", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "experienceMinYears" : 2, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "remoteFriendly" : false, "summaryDescription" : "ASIC Digital Design Engineer II, Silicon Engineering", "postedDate" : "2026-06-16T01:49:51.836", "createdAt" : "2026-06-16T01:49:51.836", "lastUpdated" : "2026-06-16T13:54:47.479", "ingestTimestamp" : "2026-06-16T01:49:51.836", "mongoId" : "6a307f0ff292fd229c054d87", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Junior", "dataQualityScore" : 0.5555556, "_score" : 1083.7173, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a210e3e74d8ee00a0af66ea", "title" : "Silicon Validation Engineering Manager, Cloud", "industry" : "Technology", "salary" : { "min" : 220000.0, "max" : 320000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Manager in Technology in Sunnyvale, United States, adjusted for seniority and industry." }, "location" : "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]", "locations" : [ "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]" ], "timestamp" : "2026-06-16T11:13:04.901", "fingerprint" : "aebb91bc8b45750f04a5ba665ad9de0edb995ea50b203dab28a2276e746eb345", "source" : "google", "language" : "en", "externalId" : "133161664315826886", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "experienceLevel" : "Manager", "remoteFriendly" : false, "summaryDescription" : "Silicon Validation Engineering Manager, Cloud", "postedDate" : "2026-06-16T01:48:28.318", "createdAt" : "2026-06-16T01:48:28.318", "lastUpdated" : "2026-06-16T11:13:04.901", "ingestTimestamp" : "2026-06-16T01:48:28.318", "mongoId" : "6a210e3e74d8ee00a0af66ea", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 220000, "salaryAnnualMax" : 320000, "salaryBand" : "200k+", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Manager", "dataQualityScore" : 0.5555556, "_score" : 847.49854, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a3092acf292fd229c0c3aef", "title" : "Senior Engineer, ASIC development Engineering (ASIC, SOC Validation)", "company" : "Sandisk", "industry" : "Computer Hardware", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior ASIC Development Engineers in Bengaluru, India, adjusted for industry and seniority." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-16T13:08:28.814", "fingerprint" : "c147f099a5887f0664c1e1fc1db50da2c6f2d8e0facd8e79e15ce4813efedf3d", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000132211732-senior-engineer-asic-development-engineering-asic-soc-validation-with-3-to-5-years-of-experience", "externalId" : "744000132211732", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "C, SystemVerilog, UVM, Python, Perl, DDR, PCIe, LPDDR, USB, Ethernet, I2C, I3C, SPI, AXI, AHB, APB, UPF, CPF", "professionalSkills" : [ "Root cause analysis", "System design" ], "hardSkillsList" : [ "Embedded programming", "Hardware/software co-validation", "SoC verification", "SoC validation", "ASIC bring-up", "Post-silicon validation", "Datapath validation", "Firmware development", "HAL development", "Validation infrastructure", "Gate-level simulations", "Power-aware validation", "ATE functional patterns", "Performance testing", "Stress testing", "Constrained-random verification", "Coverage-driven verification", "Assertion-based verification" ], "hardSkills" : [ { "name" : "Embedded programming", "level" : "intermediate" }, { "name" : "Hardware/software co-validation", "level" : "intermediate" }, { "name" : "SoC verification", "level" : "intermediate" }, { "name" : "SoC validation", "level" : "intermediate" }, { "name" : "ASIC bring-up", "level" : "intermediate" }, { "name" : "Post-silicon validation", "level" : "intermediate" }, { "name" : "Datapath validation", "level" : "intermediate" }, { "name" : "Firmware development", "level" : "intermediate" }, { "name" : "HAL development", "level" : "intermediate" }, { "name" : "Validation infrastructure", "level" : "intermediate" }, { "name" : "Gate-level simulations", "level" : "intermediate" }, { "name" : "Power-aware validation", "level" : "intermediate" }, { "name" : "ATE functional patterns", "level" : "intermediate" }, { "name" : "Performance testing", "level" : "intermediate" }, { "name" : "Stress testing", "level" : "intermediate" }, { "name" : "Constrained-random verification", "level" : "intermediate" }, { "name" : "Coverage-driven verification", "level" : "intermediate" }, { "name" : "Assertion-based verification", "level" : "intermediate" } ], "majorSkills" : "SoC Validation, ASIC Development, Verification Planning, Test Environment Development", "majorSkillsList" : [ "SoC Validation", "ASIC Development", "Verification Planning", "Test Environment Development" ], "coreResponsibilities" : "Understand complex ASIC specifications, Create comprehensive Verification/Validation plans, Independently develop and execute tests, Collaborate with cross-functional teams, Drive closure of verification and validation activities, Sign off on verification and validation deliverables, Debug and root cause analysis of issues, Develop and maintain automated test environments, Develop and maintain regression suites, Contribute to continuous improvement of verification methodologies, Contribute to best practices, Enable industry-leading data storage control SoCs, Plan verification and validation flows, Execute verification and validation flows, Close verification and validation flows, Verify industry-standard protocols, Accelerate debug on Palladiumulation platforms, Improve pre-silicon coverage, Contribute to SoC-level testbenches, Perform initial debug, Perform root cause analysis, Enable datapath, integration, and SoC-level validation, Enable datapath, integration, and SoC-level verification, Build validation infrastructure, Maintain validation infrastructure, Integrate lab equipment, Debug SoC issues across multiple domains, Use JTAG for debugging, Use trace for debugging, Use waveform capture for debugging, Use performance counters for debugging, Run gate-level simulations, Debug gate-level simulations, Run power-aware validation, Debug power-aware validation, Validate ATE functional patterns, Validate performance bottlenecks, Validate traffic generation, Validate corner-case stress scenarios, Apply constrained-random verification, Apply coverage-driven verification, Apply assertion-based verification", "teamCollaboration" : "Cross-functional teams", "domainKnowledge" : "SoC designs; Data storage control SoCs; Digital world; Flash memory; Advanced memory technologies; 4IR innovations; Digital world; Data storage solutions; Next-generation data solutions; Storage solutions; Industry-standard protocols; SoC verification environments; SoC-level testbenches; Pre-/post-silicon phases; Datapath flows; Post-silicon ASIC; Hardware Abstraction Layer; SoC-level validation; SoC-level verification; Multiple domains; Low-power; DFT; Power-aware validation; ATE functional patterns; Performance bottlenecks; Traffic generation; Corner-case stress scenarios; Verification methodologies", "domainList" : [ "soc-designs", "data-storage-control-socs", "digital-world", "flash-memory", "advanced-memory-technologies", "4ir-innovations", "data-storage-solutions", "next-generation-data-solutions", "storage-solutions", "industry-standard-protocols", "soc-verification-environments", "soc-level-testbenches", "pre-post-silicon-phases", "datapath-flows", "post-silicon-asic", "hardware-abstraction-layer", "soc-level-validation", "soc-level-verification", "multiple-domains", "low-power", "dft", "power-aware-validation", "ate-functional-patterns", "performance-bottlenecks", "traffic-generation", "corner-case-stress-scenarios", "verification-methodologies" ], "domainSpecificKnowledge" : [ "SoC designs", "Data storage control SoCs", "Digital world", "Flash memory", "Advanced memory technologies", "4IR innovations", "Digital world", "Data storage solutions", "Next-generation data solutions", "Storage solutions", "Industry-standard protocols", "SoC verification environments", "SoC-level testbenches", "Pre-/post-silicon phases", "Datapath flows", "Post-silicon ASIC", "Hardware Abstraction Layer", "SoC-level validation", "SoC-level verification", "Multiple domains", "Low-power", "DFT", "Power-aware validation", "ATE functional patterns", "Performance bottlenecks", "Traffic generation", "Corner-case stress scenarios", "Verification methodologies" ], "toolProficiency" : [ "Palladiumulation" ], "innovationCreativity" : "Relentlessly innovate; Groundbreaking innovations; Pushing possibility forward; Driving innovation", "problemSolvingSkills" : "Debugging; Root cause analysis", "qualificationsBasic" : "BE or MS degree in Electrical Engineering or Computer Engineering, 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up, Deep understanding of C, embedded programming, and hardware/software co-validation methodologies, Knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts, Proven history of developing and executing verification and validation strategies for complex SoCs, End-to-end ownership of one or more subsystems or SoC verification and validation flows, Experience in verification and validation of industry-standard protocols, Run complex SoC verification and validation scenarios on Palladiumulation platforms, Understand and contribute to complex SoC-level testbenches, Execute verification and validation cases in simulation environments, Experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug, Ability to understand and validate complex datapath flows, Hands-on experience in post-silicon ASIC bring-up, validation, and debug, Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code, Build and maintain validation infrastructure, Proficiency in debugging SoC issues across multiple domains, Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns, Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios, Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification", "qualificationsPreferred" : "Experience with Python or Perl scripting languages", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. As a SoC Validation/Verification Engineer, you will play a key role in ensuring the quality and reliability of our SoC designs. You will be responsible for: * Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation. * Independently developing and executing tests for verification and validation. * Collaborating with cross-functional teams to drive closure of verification and validation activities. * Signing off on verification and validation deliverables. * Debugging and root cause analysis of issues found during validation. * Developing and maintaining automated test environments and regression suites. * Contributing to the continuous improvement of verification methodologies and best practices. Your work will enable industry-leading data storage control SoCs that are deployed in high-volume consumer and enterprise products. Why Join Us? At SanDisk, you’ll be part of a team of highly skilled engineers solving complex verification challenges and driving innovation in data storage solutions. Your work will directly impact the performance and reliability of next-generation data solutions for both consumer and enterprise markets. Together, we’ll push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions. ## Qualifications Qualifications: Required: * BE or MS degree in Electrical Engineering or Computer Engineering, with 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up. * Deep understanding of C, embedded programming, and hardware/software co-validation methodologies. * Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts. * Proven history of developing and executing verification and validation strategies for complex SoCs. Essential Duties and Responsibilities * Ownership: End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure. * Protocol Expertise: Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB. * Emulation Experience: Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage. * Testbench Proficiency: Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components. * Simulation & Debug: Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis. * Pre-/Post-Silicon Validation: Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases. * Datapath Validation: Ability to understand and validate complex datapath flows of the controller, create datapath scenarios in SoC verification environments, and port them across pre-silicon and post-silicon environments. * Post-Silicon Experience: Hands-on experience in post-silicon ASIC bring-up, validation, and debug. * Firmware & HAL Development: Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code to enable datapath, integration, and SoC-level validation and verification. * Language Proficiency: Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development * Validation Infrastructure: Build and maintain validation infrastructure, including test content, regression automation, and lab equipment integration (oscilloscopes, analyzers, logic probes). * Debug Expertise: Proficiency in debugging SoC issues across multiple domains (digital logic, firmware, timing, low-power, DFT) using JTAG, trace, waveform capture, and performance counters. * Power & GLS Validation: Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns. * Performance & Stress Testing: Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios at the SoC level. * Verification Methodology: Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification to ensure design quality and completeness. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Senior Engineer, ASIC development Engineering (ASIC, SOC Validation) at Sandisk. Skills: SoC Validation, ASIC Development, Verification Planning, Test Environment Development. Understand complex ASIC specifications. Create comprehensive Verification/Validation plans", "postedDate" : "2026-06-15T14:07:05.000", "createdAt" : "2026-06-16T03:37:09.926", "lastUpdated" : "2026-06-16T13:08:28.814", "ingestTimestamp" : "2026-06-16T03:37:09.926", "mongoId" : "6a3092acf292fd229c0c3aef", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Embedded programming", "Hardware/software co-validation", "SoC verification", "SoC validation", "ASIC bring-up", "Post-silicon validation", "Datapath validation", "Firmware development", "HAL development", "Validation infrastructure", "Gate-level simulations", "Power-aware validation", "ATE functional patterns", "Performance testing", "Stress testing", "Constrained-random verification", "Coverage-driven verification", "Assertion-based verification", "SoC Validation", "ASIC Development", "Verification Planning", "Test Environment Development", "Root cause analysis", "System design", "SoC designs", "Data storage control SoCs", "Digital world", "Flash memory", "Advanced memory technologies", "4IR innovations", "Data storage solutions", "Next-generation data solutions", "Storage solutions", "Industry-standard protocols", "SoC verification environments", "SoC-level testbenches", "Pre-/post-silicon phases", "Datapath flows", "Post-silicon ASIC", "Hardware Abstraction Layer", "SoC-level validation", "SoC-level verification", "Multiple domains", "Low-power", "DFT", "Performance bottlenecks", "Traffic generation", "Corner-case stress scenarios", "Verification methodologies", "Palladiumulation" ], "skillCount" : 50, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 789.1647, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a3080e2f292fd229c068079", "title" : "Senior Engineer, ASIC development Engineering (ASIC, SOC Validation)", "company" : "Sandisk", "industry" : "Computer Hardware", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior ASIC Development Engineers in Bengaluru, India, adjusted for industry and seniority." }, "location" : "Bengaluru, KA, IN", "locations" : [ "Bengaluru", "KA", "IN" ], "timestamp" : "2026-06-16T11:51:51.039", "fingerprint" : "1c70e5a556fb053442b350f3c7129e251e686aafac4f20b2bb76601699e1a598", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Sandisk/744000132211732-senior-engineer-asic-development-engineering-asic-soc-validation-with-3-to-5-years-of-experience", "externalId" : "744000132211732", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "technicalSkills" : "C, SystemVerilog, UVM, Python, Perl, AXI, AHB, APB, UPF, CPF", "professionalSkills" : [ "Root cause analysis", "System design" ], "hardSkillsList" : [ "Embedded programming", "Hardware/software co-validation", "SoC verification", "SoC validation", "ASIC bring-up", "Post-silicon validation", "Firmware development", "HAL development", "Validation infrastructure", "Gate-level simulations", "Power-aware validation", "ATE functional patterns", "Performance testing", "Stress testing", "Constrained-random verification", "Coverage-driven verification", "Assertion-based verification" ], "hardSkills" : [ { "name" : "Embedded programming", "level" : "intermediate" }, { "name" : "Hardware/software co-validation", "level" : "intermediate" }, { "name" : "SoC verification", "level" : "intermediate" }, { "name" : "SoC validation", "level" : "intermediate" }, { "name" : "ASIC bring-up", "level" : "intermediate" }, { "name" : "Post-silicon validation", "level" : "intermediate" }, { "name" : "Firmware development", "level" : "intermediate" }, { "name" : "HAL development", "level" : "intermediate" }, { "name" : "Validation infrastructure", "level" : "intermediate" }, { "name" : "Gate-level simulations", "level" : "intermediate" }, { "name" : "Power-aware validation", "level" : "intermediate" }, { "name" : "ATE functional patterns", "level" : "intermediate" }, { "name" : "Performance testing", "level" : "intermediate" }, { "name" : "Stress testing", "level" : "intermediate" }, { "name" : "Constrained-random verification", "level" : "intermediate" }, { "name" : "Coverage-driven verification", "level" : "intermediate" }, { "name" : "Assertion-based verification", "level" : "intermediate" } ], "majorSkills" : "SoC Validation, ASIC Development, Verification Planning, Test Environment Development", "majorSkillsList" : [ "SoC Validation", "ASIC Development", "Verification Planning", "Test Environment Development" ], "coreResponsibilities" : "Understand complex ASIC specifications, Create comprehensive Verification/Validation plans, Independently develop and execute tests, Collaborate with cross-functional teams, Drive closure of verification and validation activities, Sign off on verification and validation deliverables, Debug and root cause analysis of issues, Develop and maintain automated test environments, Develop and maintain regression suites, Contribute to continuous improvement of verification methodologies, Contribute to best practices, Enable industry-leading data storage control SoCs, Plan verification and validation flows, Execute verification and validation flows, Close verification and validation flows, Verify industry-standard protocols, Validate industry-standard protocols, Run verification scenarios on Palladiumulation platforms, Accelerate debug on Palladiumulation platforms, Improve pre-silicon coverage on Palladiumulation platforms, Contribute to SoC-level testbenches, Perform initial debug, Perform root cause analysis, Validate complex datapath flows, Create datapath scenarios, Port datapath scenarios, Enable datapath validation, Enable integration validation, Enable SoC-level validation, Develop firmware, Develop bare-metal tests, Develop Hardware Abstraction Layer (HAL) code, Build validation infrastructure, Maintain validation infrastructure, Integrate lab equipment, Debug SoC issues, Debug digital logic issues, Debug firmware issues, Debug timing issues, Debug low-power issues, Debug DFT issues, Use JTAG for debugging, Use trace for debugging, Use waveform capture for debugging, Use performance counters for debugging, Run gate-level simulations, Debug gate-level simulations, Run power-aware validation, Debug power-aware validation, Validate ATE functional patterns, Validate performance bottlenecks, Validate traffic generation, Validate corner-case stress scenarios, Apply constrained-random verification, Apply coverage-driven verification, Apply assertion-based verification", "teamCollaboration" : "Cross-functional teams", "domainKnowledge" : "SoC designs; Data storage; Flash memory; Advanced memory technologies; Industry-standard protocols; DDR; PCIe; LPDDR; USB; Ethernet; I²C; I3C; SPI; Datapath flows; Low-power design; DFT; Power-aware design", "domainList" : [ "soc-designs", "data-storage", "flash-memory", "advanced-memory-technologies", "industry-standard-protocols", "ddr", "pcie", "lpddr", "usb", "ethernet", "i-c", "i3c", "spi", "datapath-flows", "low-power-design", "dft", "power-aware-design" ], "domainSpecificKnowledge" : [ "SoC designs", "Data storage", "Flash memory", "Advanced memory technologies", "Industry-standard protocols", "DDR", "PCIe", "LPDDR", "USB", "Ethernet", "I²C", "I3C", "SPI", "Datapath flows", "Low-power design", "DFT", "Power-aware design" ], "toolProficiency" : [ "Palladiumulation" ], "problemSolvingSkills" : "Debugging; Root cause analysis", "qualificationsBasic" : "BE or MS degree in Electrical Engineering or Computer Engineering, 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up, Deep understanding of C, embedded programming, and hardware/software co-validation methodologies, Knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts, Proven history of developing and executing verification and validation strategies for complex SoCs, End-to-end ownership of one or more subsystems or SoC verification and validation flows, Experience in verification and validation of industry-standard protocols, Run complex SoC verification and validation scenarios on Palladiumulation platforms, Understand and contribute to complex SoC-level testbenches, Execute verification and validation cases in simulation environments, Experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug, Ability to understand and validate complex datapath flows, Hands-on experience in post-silicon ASIC bring-up, validation, and debug, Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code, Build and maintain validation infrastructure, Proficiency in debugging SoC issues across multiple domains, Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns, Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios, Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification", "qualificationsPreferred" : "Experience with Python or Perl scripting languages", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. As a SoC Validation/Verification Engineer, you will play a key role in ensuring the quality and reliability of our SoC designs. You will be responsible for: * Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation. * Independently developing and executing tests for verification and validation. * Collaborating with cross-functional teams to drive closure of verification and validation activities. * Signing off on verification and validation deliverables. * Debugging and root cause analysis of issues found during validation. * Developing and maintaining automated test environments and regression suites. * Contributing to the continuous improvement of verification methodologies and best practices. Your work will enable industry-leading data storage control SoCs that are deployed in high-volume consumer and enterprise products. Why Join Us? At SanDisk, you’ll be part of a team of highly skilled engineers solving complex verification challenges and driving innovation in data storage solutions. Your work will directly impact the performance and reliability of next-generation data solutions for both consumer and enterprise markets. Together, we’ll push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions. ## Qualifications Qualifications: Required: * BE or MS degree in Electrical Engineering or Computer Engineering, with 4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up. * Deep understanding of C, embedded programming, and hardware/software co-validation methodologies. * Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts. * Proven history of developing and executing verification and validation strategies for complex SoCs. Essential Duties and Responsibilities * Ownership: End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure. * Protocol Expertise: Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB. * Emulation Experience: Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage. * Testbench Proficiency: Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components. * Simulation & Debug: Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis. * Pre-/Post-Silicon Validation: Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases. * Datapath Validation: Ability to understand and validate complex datapath flows of the controller, create datapath scenarios in SoC verification environments, and port them across pre-silicon and post-silicon environments. * Post-Silicon Experience: Hands-on experience in post-silicon ASIC bring-up, validation, and debug. * Firmware & HAL Development: Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code to enable datapath, integration, and SoC-level validation and verification. * Language Proficiency: Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development * Validation Infrastructure: Build and maintain validation infrastructure, including test content, regression automation, and lab equipment integration (oscilloscopes, analyzers, logic probes). * Debug Expertise: Proficiency in debugging SoC issues across multiple domains (digital logic, firmware, timing, low-power, DFT) using JTAG, trace, waveform capture, and performance counters. * Power & GLS Validation: Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns. * Performance & Stress Testing: Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios at the SoC level. * Verification Methodology: Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification to ensure design quality and completeness. ## Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [jobs.accommodations@sandisk.com](mailto:jobs.accommodations@sandisk.com) to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.", "summaryDescription" : "Senior Engineer, ASIC development Engineering (ASIC, SOC Validation) at Sandisk. Skills: SoC Validation, ASIC Development, Verification Planning, Test Environment Development. Understand complex ASIC specifications. Create comprehensive Verification/Validation plans", "postedDate" : "2026-06-15T14:07:05.000", "createdAt" : "2026-06-16T01:41:33.626", "lastUpdated" : "2026-06-16T11:51:51.039", "ingestTimestamp" : "2026-06-16T01:41:33.626", "mongoId" : "6a3080e2f292fd229c068079", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Embedded programming", "Hardware/software co-validation", "SoC verification", "SoC validation", "ASIC bring-up", "Post-silicon validation", "Firmware development", "HAL development", "Validation infrastructure", "Gate-level simulations", "Power-aware validation", "ATE functional patterns", "Performance testing", "Stress testing", "Constrained-random verification", "Coverage-driven verification", "Assertion-based verification", "SoC Validation", "ASIC Development", "Verification Planning", "Test Environment Development", "Root cause analysis", "System design", "SoC designs", "Data storage", "Flash memory", "Advanced memory technologies", "Industry-standard protocols", "DDR", "PCIe", "LPDDR", "USB", "Ethernet", "I²C", "I3C", "SPI", "Datapath flows", "Low-power design", "DFT", "Power-aware design", "Palladiumulation" ], "skillCount" : 41, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 789.1647, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a305b03f292fd229cf584e9", "title" : "Silicon Emulation Engineer", "company" : "Waymo", "industry" : "Technology", "salary" : { "min" : 175000.0, "max" : 215000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Mountain View, California, United States", "locations" : [ "Mountain View", "California", "United States" ], "timestamp" : "2026-06-16T07:21:35.569", "fingerprint" : "fd32fcc0842fd919e0180c0a7dbd6d78223e89d6761cd34e3cf329cc6e514780", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://careers.withwaymo.com/jobs?gh_jid=8004234", "externalId" : "8004234", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Mountain View", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "hybrid", "geo" : "37.3893889,-122.0832101" } ], "locationText" : "Mountain View, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "technicalSkills" : "SystemVerilog, C++, Python, TCL, QEMU, VirtualBox", "professionalSkills" : [ "System design", "Performance analysis", "Power analysis" ], "hardSkillsList" : [ "Hardware emulation", "Software development", "Testbench development", "Root cause analysis", "Infrastructure building", "Automation", "Regression testing", "Continuous integration", "Data analysis", "Bare metal programming", "Embedded systems", "Linux internals", "Operating systems", "Boot loaders", "Drivers", "Firmware" ], "hardSkills" : [ { "name" : "Hardware emulation", "level" : "intermediate" }, { "name" : "Software development", "level" : "intermediate" }, { "name" : "Testbench development", "level" : "intermediate" }, { "name" : "Root cause analysis", "level" : "intermediate" }, { "name" : "Infrastructure building", "level" : "intermediate" }, { "name" : "Automation", "level" : "intermediate" }, { "name" : "Regression testing", "level" : "intermediate" }, { "name" : "Continuous integration", "level" : "intermediate" }, { "name" : "Data analysis", "level" : "intermediate" }, { "name" : "Bare metal programming", "level" : "intermediate" }, { "name" : "Embedded systems", "level" : "intermediate" }, { "name" : "Linux internals", "level" : "intermediate" }, { "name" : "Operating systems", "level" : "intermediate" }, { "name" : "Boot loaders", "level" : "intermediate" }, { "name" : "Drivers", "level" : "intermediate" }, { "name" : "Firmware", "level" : "intermediate" } ], "majorSkills" : "Silicon emulation, Hardware/software debug, Testbench optimization", "majorSkillsList" : [ "Silicon emulation", "Hardware/software debug", "Testbench optimization" ], "coreResponsibilities" : "Collaborate with Design, Verification, Software teams, Simulate future silicon designs, Simulate software on emulation platform, Target functional validation, Target performance validation, Left-shift software development, Design emulation testbenches, Implement emulation testbenches, Optimize emulation testbenches, Write synthesizable transactors, Interact with emulated designs, Triage failures, Root-cause failures, Assist with post-silicon bring-up, Assist with debug, Assist with characterization, Build infrastructure for emulation users, Develop tools for model build, Develop tools for regression, Develop tools for automation, Develop tools for continuous integration, Develop tools for data analysis, Develop tools for training", "teamCollaboration" : "Design teams; Verification teams; Software teams; Silicon Engineering Lead", "domainKnowledge" : "Autonomous driving; Compute platforms; Automotive compute; Hardware/software co-design; Embedded systems; Linux internals; Operating systems; Bare metal programming", "domainList" : [ "autonomous-driving", "compute-platforms", "automotive-compute", "hardware-software-co-design", "embedded-systems", "linux-internals", "operating-systems", "bare-metal-programming" ], "domainSpecificKnowledge" : [ "Autonomous driving", "Compute platforms", "Automotive compute", "Hardware/software co-design", "Embedded systems", "Linux internals", "Operating systems", "Bare metal programming" ], "toolProficiency" : [ "Palladium", "Zebu", "Veloce", "Protium", "HAPS", "Trace32", "OpenOCD", "TARMAC" ], "problemSolvingSkills" : "Root-cause analysis; Debug; Problem-solving", "qualificationsBasic" : "BS degree in Computer Science / Electrical Engineering, 5 years of silicon development experience, Experience with major hardware emulation platform, High proficiency with emulation approaches, Experience with SystemVerilog, Experience with design verification methodologies, Programming and scripting for automation, Debug and problem-solving ability", "qualificationsPreferred" : "Experience with AXI/AMBA, Experience with PCIe, Experience with DRAM, Experience with Ethernet interfaces, Performance and power analysis techniques, Experience with JTAG, Experience with DFT, Experience with UART, Experience with SPI, Experience with GPIO, Experience with test/low-speed interfaces, Knowledge of advanced design verification methods, Post-silicon debug software experience, Lab bench tools experience, Understanding of bare metal programming, Understanding of embedded systems, Understanding of Linux internals, Understanding of operating systems, Understanding of boot loaders, Understanding of drivers, Understanding of firmware", "remoteFriendly" : true, "workSiteFlexibility" : "Hybrid", "rawDescription" : "Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U. S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle’s software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world’s highest performance automotive compute platforms. This role follows a hybrid work schedule and you will report to a Silicon Engineering Lead. You will: Collaborate with the Design, Verification, and Software teams to simulate future silicon designs and software on an emulation platform, targeting functional and performance validation and left-shift of software development Design, implement, and optimize emulation testbenches, balancing performance and debug capabilities based on user needs and hardware constraints Write end-to-end synthesizable transactors to interact with emulated designs through software APIs and C-DPI Triage and root-cause failures alongside emulation users, leveraging waveforms, software logging, and custom-built emulation monitors Assist with post-silicon bring-up, debug, and characterization Build infrastructure to support the emulation user base, including tools for model build, regression, automation, continuous integration, data analysis, and training You have: BS degree in Computer Science / Electrical Engineering or related field and 5 years of silicon development experience. Experience with at least one major hardware emulation platform (Palladium, Zebu, Veloce, Protium, HAPS). High level of proficiency with one or more of the following emulation approaches: virtual prototyping, testbench acceleration, hybrid emulation, in-circuit emulation (speed bridge), QEMU, or VirtualBox Experience with SystemVerilog and design verification methodologies Programming and scripting (C++, Python, or TCL) for automation, test development, debug flows, and release process. Strong debug and problem-solving ability across hardware and software We prefer: Experience with AXI/AMBA, PCIe, DRAM, and Ethernet interfaces Performance and power analysis techniques Experience with JTAG, DFT, UART, SPI, GPIO and other test/low-speed interfaces Knowledge of advanced design verification methods (coverage, gate-level simulation, assertions, and UVM). Post-silicon debug software (e. g. Trace32, OpenOCD, TARMAC) and lab bench tools (analyzers, scopes, meters) Understanding of bare metal programming, embedded systems, Linux internals, operating systems, boot loaders, drivers, and firmware The expected base salary range for this full-time position across US locations is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Your recruiter can share more about the specific salary range for the role location or, if the role can be performed remote, the specific salary range for your preferred location, during the hiring process. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range $175,000—$215,000 USD", "summaryDescription" : "Silicon Emulation Engineer at Waymo. Skills: Silicon emulation, Hardware/software debug, Testbench optimization. Collaborate with Design, Verification, Software teams. Simulate future silicon designs", "postedDate" : "2026-06-15T23:20:52.716", "createdAt" : "2026-06-15T23:20:52.716", "lastUpdated" : "2026-06-16T07:21:35.569", "ingestTimestamp" : "2026-06-15T23:20:52.716", "mongoId" : "6a305b03f292fd229cf584e9", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 175000, "salaryAnnualMax" : 215000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Hardware emulation", "Software development", "Testbench development", "Root cause analysis", "Infrastructure building", "Automation", "Regression testing", "Continuous integration", "Data analysis", "Bare metal programming", "Embedded systems", "Linux internals", "Operating systems", "Boot loaders", "Drivers", "Firmware", "Silicon emulation", "Hardware/software debug", "Testbench optimization", "System design", "Performance analysis", "Power analysis", "Autonomous driving", "Compute platforms", "Automotive compute", "Hardware/software co-design", "Palladium", "Zebu", "Veloce", "Protium", "HAPS", "Trace32", "OpenOCD", "TARMAC" ], "skillCount" : 34, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 760.95685, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "68c2e436f8b1b0376634c803", "title" : "ASIC SoC Manager", "company" : "Amazon Development Center Taiwan Limited", "industry" : "Software Development, ASIC, alexa and amazon devices", "salary" : { "min" : 2600000.0, "max" : 4000000.0, "currency" : "TWD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Manager in the Technology industry in Hsinchu City, Taiwan, adjusted for company size and seniority." }, "location" : "Hsinchu City, TWN", "locations" : [ "Hsinchu City, TWN" ], "timestamp" : "2026-06-15T03:11:28.891", "fingerprint" : "2a016df674346a520aed3d01719b6a75d5e59d7e8a0c6346fdf99aa65d42b1c7", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3073148/apply", "externalId" : "d29b760a-1b4a-4a93-a4e6-b75d56a339d8", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Hsinchu City", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "24.8078135,121.0336572" } ], "locationText" : "Hsinchu City, Taiwan", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceLevel" : "Manager", "technicalSkills" : "RTL, UPF", "professionalSkills" : [ "Silicon development", "Microarchitecture", "SoC integration", "Digital design", "Low-power design" ], "hardSkillsList" : [ "RTL simulation", "Synthesis", "Timing constraints", "STA", "LEC", "Low-power design", "Floor planning" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "RTL simulation", "level" : "intermediate" }, { "name" : "Synthesis", "level" : "intermediate" }, { "name" : "Timing constraints", "level" : "intermediate" }, { "name" : "STA", "level" : "intermediate" }, { "name" : "LEC", "level" : "intermediate" }, { "name" : "Low-power design", "level" : "intermediate" }, { "name" : "Floor planning", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "ASIC SoC, Silicon development, Team leadership", "majorSkillsList" : [ "ASIC SoC", "Silicon development", "Team leadership" ], "coreResponsibilities" : "Lead engineering team for silicon development, Hire engineering team for silicon development, Develop engineering team for silicon development, Deliver world-class silicon, Solve fundamental challenges in battery powered camera devices, Work with IP suppliers, Ensure best-in-class IP availability, Take ownership of crucial design issues, Lead design reviews, Build design processes, Improve performance, Improve quality, Deliver year-on-year performance, Deliver year-on-year power, Deliver year-on-year features, Drive analysis to determine performance targets, Validate hardware/software, Debug issues", "teamCollaboration" : "Cross-functional teams; Product management; Firmware teams; Validation teams; IP integration teams", "domainKnowledge" : "Video processing; Low power SoC; Battery powered devices; High volume ASICs", "domainList" : [ "video-processing", "low-power-soc", "battery-powered-devices", "high-volume-asics" ], "domainSpecificKnowledge" : [ "Video processing", "Low power SoC", "Battery powered devices", "High volume ASICs" ], "problemSolvingSkills" : "Design issues", "outcomesObjectives" : "Deliver silicon that reaches end customers; Deliver year-on-year performance; Deliver year-on-year power; Deliver year-on-year features", "qualificationsBasic" : "Bachelor’s degree in Electronic Engineering, Computer Engineering or related field, 5+ years of management / lead experience of engineering teams, Experience with all aspects of digital silicon development, RTL simulation, Synthesis, Front-end timing constraints, STA, LEC, UPF, Low-power design flows, Floor planning, Delivered and shipped silicon for high-volume consumer devices", "qualificationsPreferred" : "Master’s degree in Electronic Engineering, Computer Engineering or related field, Experience designing and delivering SoCs for consumer devices, 10+ years of management experience of engineering teams, IP or SoC integration efforts", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "As an SoC Manager, you will lead a team responsible for executing and delivering complex IPs and silicon that ship in the Blink and Ring camera products. Your team will be responsible for front-end digital design and verification of complex IP and SoC integration. This role provides you a rare opportunity to build high volume ASICs and deliver silicon that reaches end customers in the shortest possible time. This role is inherently cross-functional; you will work closely with product management, firmware, validation and other IP/integration teams. A successful candidate must have a track record of designing or verifying complex SoCs and leading teams. Experience in video processing and low power SoC flows would be beneficial. #ASICTW Key job responsibilities - Lead, hire and develop a world-class engineering team for silicon development, including expertise in front-end microarchitecture, RTL and verification through netlist hand-off - Deliver world-class silicon that solves fundamental challenges in battery powered camera devices - Work with internal and external IP suppliers to ensure best-in-class IP availability for integration - Dive into and take ownership of crucial design issues - Lead design reviews - Build design processes to continuously improve performance and quality - Deliver year-on-year performance, power and features - Drive analysis to determine performance targets - Validate hardware/software and debug issues Basic Qualifications: - Bachelor’s degree in Electronic Engineering, Computer Engineering or related field - 5+ years of management / lead experience of engineering teams - Experience with all aspects of digital silicon development including RTL simulation, synthesis, front-end timing constraints, STA, LEC, UPF, low-power design flows, floor planning, etc. - Has lead, delivered and shipped silicon for high-volume consumer devices Preferred Qualifications: - Master’s degree in Electronic Engineering, Computer Engineering or related field - Experience designing and delivering SoCs for consumer devices - 10+ years of management experience of engineering teams – either IP or SoC integration efforts Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "ASIC SoC Manager at Amazon Development Center Taiwan Limited. Skills: ASIC SoC, Silicon development, Team leadership. Lead engineering team for silicon development. Hire engineering team for silicon development", "postedDate" : "2026-06-13T07:15:32.083", "createdAt" : "2026-06-13T07:15:32.083", "lastUpdated" : "2026-06-15T03:11:28.891", "ingestTimestamp" : "2026-06-13T07:15:32.083", "mongoId" : "68c2e436f8b1b0376634c803", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3073148/apply", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "RTL simulation", "Synthesis", "Timing constraints", "STA", "LEC", "Low-power design", "Floor planning", "Leadership", "ASIC SoC", "Silicon development", "Team leadership", "Microarchitecture", "SoC integration", "Digital design", "Video processing", "Low power SoC", "Battery powered devices", "High volume ASICs" ], "skillCount" : 18, "jobCategory" : "engineering", "dataQualityScore" : 1.0, "_score" : 754.19836, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2a660174d8ee00a062b706", "title" : "Sr Manager ASIC NPI", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Project/Program/Product Management--Non-Tech, ASIC, alexa and amazon devices", "salary" : { "min" : 239000.0, "max" : 324000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Sunnyvale, California, USA", "locations" : [ "Sunnyvale, California, USA" ], "timestamp" : "2026-06-15T03:46:58.875", "fingerprint" : "879d9b0aa8d603cc3cce8e06c14e64adf1730b04efd037d8451a10a40868c932", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10444191/apply", "externalId" : "bb5b68da-bf8c-4565-a1a0-120f88ee3d4a", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 15, "experienceLevel" : "Manager", "technicalSkills" : "ASIC development", "professionalSkills" : [ "Silicon NPI strategy", "Manufacturing yield optimization", "Supply chain readiness", "Cost optimization", "Vendor management", "Contract manufacturing strategy", "Material procurement", "Program execution", "Quality assurance", "Reliability specifications" ], "hardSkillsList" : [ "Design for Manufacturing", "Design for Test" ], "softSkillsList" : [ "Strategic Leadership" ], "hardSkills" : [ { "name" : "Design for Manufacturing", "level" : "intermediate" }, { "name" : "Design for Test", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Strategic Leadership" } ], "majorSkills" : "Silicon NPI, High-volume manufacturing, Cross-functional leadership", "majorSkillsList" : [ "Silicon NPI", "High-volume manufacturing", "Cross-functional leadership" ], "coreResponsibilities" : "Develop end-to-end silicon NPI strategy, Align with Product Management, Engineering, Operations, Meet product lifecycle milestones, Drive DFM and DFT requirements, Optimize wafer fabrication processes, Optimize assembly processes, Optimize test processes, Maximize yield, Reduce costs, Oversee vendor management, Oversee CM strategy, Oversee material procurement, Ensure capacity, Ensure timely engineering build schedules, Lead cross-functional teams, Resolve technical constraints, Resolve supply constraints, Ensure seamless transfer to mass production, Guarantee products meet quality standards, Guarantee products meet reliability specifications", "teamCollaboration" : "Cross-functional teams; Product Management; Engineering; Operations teams; Quality team", "projectManagementSkills" : [ "Program Execution" ], "domainKnowledge" : "Semiconductor products; High-volume manufacturing; Silicon wafer fab; 3D packaging; ASIC development; Advanced packaging", "domainList" : [ "semiconductor-products", "high-volume-manufacturing", "silicon-wafer-fab", "3d-packaging", "asic-development", "advanced-packaging" ], "domainSpecificKnowledge" : [ "Semiconductor products", "High-volume manufacturing", "Silicon wafer fab", "3D packaging", "ASIC development", "Advanced packaging" ], "specialRequirements" : "U. S. citizen or national, U. S. permanent resident, Lawfully admitted into U. S. as refugee, Granted asylum in U. S.", "outcomesObjectives" : "On-time delivery of samples; On-time delivery of production ramps", "qualificationsBasic" : "10+ years management experience, Bachelor's degree in EE, ME, or related, 15+ years semiconductor operations/NPI/product engineering, Proven track record in high-volume silicon manufacturing, Deep understanding of silicon wafer fab, 3D packaging, or ASIC development, Experience leading large, diverse, cross-functional teams", "qualificationsPreferred" : "Master or PhD in EE, CS, Math, or related, Experience in advanced packaging", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon Leo is an initiative to increase global broadband access through a constellation of 3,236 satellites in low Earth orbit (LEO). Its mission is to bring fast, affordable broadband to unserved and underserved communities around the world. Amazon Leo will help close the digital divide by delivering fast, affordable broadband to a wide range of customers, including consumers, businesses, government agencies, and other organizations operating in places without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Silicon NPI (New Product Introduction) leads the transition of complex semiconductor products from design to high-volume manufacturing (HVM). Responsibilities include driving cross-functional strategies for engineering validation, manufacturing yield, supply chain readiness, and cost optimization, ensuring on-time delivery of samples and production ramps. Key job responsibilities Strategic Leadership: Develop and own the end-to-end silicon NPI strategy, aligning with Product Management, Engineering, and Operations teams to meet product lifecycle milestones (EVT, DVT, PVT) Manufacturing & Yield: Drive Design for Manufacturing (DFM) and Design for Test (DFT) requirements. Optimize wafer fabrication, assembly, and test processes to maximize yield and reduce costs, including in advanced packaging. Supply Chain & Ops Readiness: Oversee vendor management, contract manufacturer (CM) strategy, and material procurement to ensure capacity and timely engineering build schedules. Program Execution: Lead cross-functional teams to resolve technical and supply constraints during the NPI phase, ensuring a seamless transfer to mass production Quality & Reliability: Guarantee that products meet quality standards and reliability specifications before product release in conjunction with the Quality team. Basic Qualifications: - 10+ years of management experience - Bachelor's degree in electrical engineering, material engineering, mechanical engineering or related fields - 15+ years in semiconductor operations, NPI, or product engineering, with a proven track record in high-volume silicon manufacturing - Deep understanding of silicon wafer fab, 3D packaging, or complex ASIC development - Experience leading large, diverse, cross-functional teams in a fast-paced environment Preferred Qualifications: - Master or PhD in Electrical Engineering, Computer Science, Mathematics, or a related technical field Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Sunnyvale - 239,600.00 - 324,100.00 USD annually", "summaryDescription" : "Sr Manager ASIC NPI at Amazon Kuiper Manufacturing Enterprises LLC. Skills: Silicon NPI, High-volume manufacturing, Cross-functional leadership. Develop end-to-end silicon NPI strategy. Align with Product Management, Engineering, Operations", "postedDate" : "2026-06-13T15:57:59.545", "createdAt" : "2026-06-13T15:57:59.545", "lastUpdated" : "2026-06-15T03:46:58.875", "ingestTimestamp" : "2026-06-13T15:57:59.545", "mongoId" : "6a2a660174d8ee00a062b706", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10444191/apply", "salaryAnnualMin" : 239000, "salaryAnnualMax" : 324000, "salaryBand" : "200k+", "hasSalary" : true, "allSkills" : [ "Design for Manufacturing", "Design for Test", "Strategic Leadership", "Silicon NPI", "High-volume manufacturing", "Cross-functional leadership", "Silicon NPI strategy", "Manufacturing yield optimization", "Supply chain readiness", "Cost optimization", "Vendor management", "Contract manufacturing strategy", "Material procurement", "Program execution", "Quality assurance", "Reliability specifications", "Program Execution", "Semiconductor products", "Silicon wafer fab", "3D packaging", "ASIC development", "Advanced packaging" ], "skillCount" : 22, "jobCategory" : "project-management", "dataQualityScore" : 1.0, "_score" : 717.8419, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Semiconductor Manufacturing" }, { "id" : "6a307f59f292fd229c05838b", "title" : "Senior Silicon DFT Engineer", "company" : "Google", "industry" : "Technology", "salary" : { "min" : 450000.0, "max" : 750000.0, "currency" : "ILS", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior Silicon DFT Engineer in Tel Aviv, Israel, adjusted for Google's industry and size, and senior experience level." }, "location" : "[Tel Aviv, Israel, [Yigal Alon St 98, Tel Aviv-Yafo, Israel], Tel Aviv-Yafo, null, Tel Aviv District, IL]", "locations" : [ "[Tel Aviv, Israel, [Yigal Alon St 98, Tel Aviv-Yafo, Israel], Tel Aviv-Yafo, null, Tel Aviv District, IL]", "[Haifa, Israel, [Haifa, Israel], Haifa, null, Haifa District, IL]" ], "timestamp" : "2026-06-16T13:56:53.371", "fingerprint" : "693e959583b6dd3068e693d783a49b672f81582ea304c2fbe95612d29bc416aa", "source" : "google", "language" : "en", "externalId" : "113854278786785990", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Tel Aviv", "country" : "Israel", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "32.0852997,34.7818064" } ], "locationText" : "Tel Aviv, Israel", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "DFT, Scan chains, Boundary scan, Test patterns, ATPG, Memory BIST, Logic BIST, Scan compression, SoC, ASIC, Verilog, VHDL, SystemVerilog, Python, Shell scripting, Perl, Tcl", "professionalSkills" : [ "Silicon validation", "Chip design", "Test development" ], "hardSkillsList" : [ "DFT methodologies", "Test pattern generation", "Scan insertion", "BIST implementation", "Compression techniques" ], "hardSkills" : [ { "name" : "DFT methodologies", "level" : "intermediate" }, { "name" : "Test pattern generation", "level" : "intermediate" }, { "name" : "Scan insertion", "level" : "intermediate" }, { "name" : "BIST implementation", "level" : "intermediate" }, { "name" : "Compression techniques", "level" : "intermediate" } ], "majorSkills" : "DFT, Silicon validation, SoC design", "majorSkillsList" : [ "DFT", "Silicon validation", "SoC design" ], "coreResponsibilities" : "Design and implement DFT structures, Develop scan chains, Implement boundary scan, Generate test patterns, Perform ATPG, Implement memory BIST, Implement logic BIST, Develop scan compression, Support SoC and ASIC design, Collaborate with design teams, Debug DFT issues, Validate DFT implementation, Work with cloud technologies, Work with AI/ML", "teamCollaboration" : "Design teams; Cross-functional teams", "domainKnowledge" : "DFT; SoC; ASIC; Semiconductor industry", "domainList" : [ "dft", "soc", "asic", "semiconductor-industry" ], "domainSpecificKnowledge" : [ "DFT", "SoC", "ASIC", "Semiconductor industry" ], "toolProficiency" : [ "Cadence", "Synopsys", "Mentor Graphics" ], "documentationSkills" : "Technical documentation", "problemSolvingSkills" : "Debug DFT issues; Root cause analysis", "qualificationsBasic" : "5+ years DFT experience, BS/MS degree", "qualificationsPreferred" : "Experience with cloud technologies, Experience with AI/ML", "workSiteFlexibility" : "Onsite", "summaryDescription" : "Senior Silicon DFT Engineer at Google. Skills: DFT, Silicon validation, SoC design. Design and implement DFT structures. Develop scan chains", "postedDate" : "2026-06-16T01:51:54.593", "createdAt" : "2026-06-16T01:51:54.593", "lastUpdated" : "2026-06-16T13:56:53.371", "ingestTimestamp" : "2026-06-16T01:51:54.593", "mongoId" : "6a307f59f292fd229c05838b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "DFT methodologies", "Test pattern generation", "Scan insertion", "BIST implementation", "Compression techniques", "DFT", "Silicon validation", "SoC design", "Chip design", "Test development", "SoC", "ASIC", "Semiconductor industry", "Cadence", "Synopsys", "Mentor Graphics" ], "skillCount" : 16, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.7777778, "_score" : 685.04803, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "69fda4e54c40e2acd1b99a28", "title" : "Sr Manager ASIC NPI", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Project/Program/Product Management--Non-Tech, Aerospace MFG Engineer, alexa and amazon devices", "salary" : { "min" : 206700.0, "max" : 279600.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Sunnyvale, California, USA", "locations" : [ "Sunnyvale, California, USA" ], "timestamp" : "2026-06-15T04:32:58.572", "fingerprint" : "e41dee671e0910ae014d7317ebfe2c793b48f8cb8e3c581d271fa1ab3714d10a", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10412734/apply", "externalId" : "be89db50-64fd-4748-99d2-8d33fb02f984", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 12, "experienceMaxYears" : 15, "experienceLevel" : "Manager", "technicalSkills" : "ASIC development", "professionalSkills" : [ "Silicon NPI", "Manufacturing yield", "Supply chain readiness", "Cost optimization", "Design for Manufacturing", "Design for Test", "Wafer fabrication", "Assembly", "Test processes", "Advanced packaging", "Vendor management", "Contract manufacturer strategy", "Material procurement", "Program execution", "Quality standards", "Reliability specifications" ], "hardSkillsList" : [ "Semiconductor operations", "Product engineering", "Silicon wafer fab", "3D packaging", "ASIC development" ], "softSkillsList" : [ "Strategic Leadership" ], "hardSkills" : [ { "name" : "Semiconductor operations", "level" : "intermediate" }, { "name" : "Product engineering", "level" : "intermediate" }, { "name" : "Silicon wafer fab", "level" : "intermediate" }, { "name" : "3D packaging", "level" : "intermediate" }, { "name" : "ASIC development", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Strategic Leadership" } ], "majorSkills" : "Silicon NPI, Manufacturing, Supply chain", "majorSkillsList" : [ "Silicon NPI", "Manufacturing", "Supply chain" ], "coreResponsibilities" : "Develop end-to-end silicon NPI strategy, Drive Design for Manufacturing (DFM) requirements, Drive Design for Test (DFT) requirements, Optimize wafer fabrication processes, Optimize assembly processes, Optimize test processes, Oversee vendor management, Oversee contract manufacturer strategy, Oversee material procurement, Lead cross-functional teams, Resolve technical constraints, Resolve supply constraints, Ensure seamless transfer to mass production, Guarantee products meet quality standards, Guarantee products meet reliability specifications", "teamCollaboration" : "Cross-functional teams; Product Management; Engineering; Operations teams; Quality team", "projectManagementSkills" : [ "Program execution" ], "domainKnowledge" : "Semiconductor manufacturing; Silicon wafer fab; 3D packaging; ASIC development; New Product Introduction (NPI)", "domainList" : [ "semiconductor-manufacturing", "silicon-wafer-fab", "3d-packaging", "asic-development", "new-product-introduction-npi" ], "domainSpecificKnowledge" : [ "Semiconductor manufacturing", "Silicon wafer fab", "3D packaging", "ASIC development", "New Product Introduction (NPI)" ], "problemSolvingSkills" : "Root cause analysis", "specialRequirements" : "U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S. as a refugee or granted asylum", "outcomesObjectives" : "Meet product lifecycle milestones; Maximize yield; Reduce costs; Ensure capacity; Ensure timely engineering build schedules; Ensure on-time delivery of samples; Ensure on-time production ramps; Meet quality standards; Meet reliability specifications", "qualificationsBasic" : "10+ years management experience, Bachelor's degree in electrical engineering, material engineering, mechanical engineering or related fields, 12–15+ years semiconductor operations, NPI, or product engineering, Proven track record in high-volume silicon manufacturing, Deep understanding of silicon wafer fab, 3D packaging, or complex ASIC development, Experience leading large, diverse, cross-functional teams", "qualificationsPreferred" : "PhD in Electrical Engineering, Computer Science, Mathematics, or a related technical field, Master or PhD in Electrical Engineering, Computer Science, Mathematics, or a related technical field", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon Leo is an initiative to increase global broadband access through a constellation of 3,236 satellites in low Earth orbit (LEO). Its mission is to bring fast, affordable broadband to unserved and underserved communities around the world. Amazon Leo will help close the digital divide by delivering fast, affordable broadband to a wide range of customers, including consumers, businesses, government agencies, and other organizations operating in places without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Silicon NPI (New Product Introduction) leads the transition of complex semiconductor products from design to high-volume manufacturing (HVM). Responsibilities include driving cross-functional strategies for engineering validation, manufacturing yield, supply chain readiness, and cost optimization, ensuring on-time delivery of samples and production ramps. Key job responsibilities Strategic Leadership: Develop and own the end-to-end silicon NPI strategy, aligning with Product Management, Engineering, and Operations teams to meet product lifecycle milestones (EVT, DVT, PVT) Manufacturing & Yield: Drive Design for Manufacturing (DFM) and Design for Test (DFT) requirements. Optimize wafer fabrication, assembly, and test processes to maximize yield and reduce costs, including in advanced packaging. Supply Chain & Ops Readiness: Oversee vendor management, contract manufacturer (CM) strategy, and material procurement to ensure capacity and timely engineering build schedules. Program Execution: Lead cross-functional teams to resolve technical and supply constraints during the NPI phase, ensuring a seamless transfer to mass production Quality & Reliability: Guarantee that products meet quality standards and reliability specifications before product release in conjunction with the Quality team. Basic Qualifications: - 10+ years of management experience - Bachelor's degree in electrical engineering, material engineering, mechanical engineering or related fields - 12–15+ years in semiconductor operations, NPI, or product engineering, with a proven track record in high-volume silicon manufacturing - Deep understanding of silicon wafer fab, 3D packaging, or complex ASIC development - Experience leading large, diverse, cross-functional teams in a fast-paced environment Preferred Qualifications: - PhD in Electrical Engineering, Computer Science, Mathematics, or a related technical field - Master or PhD in Electrical Engineering, Computer Science, Mathematics, or a related technical field Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Sunnyvale - 206,700.00 - 279,600.00 USD annually", "summaryDescription" : "Sr Manager ASIC NPI at Amazon Kuiper Manufacturing Enterprises LLC. Skills: Silicon NPI, Manufacturing, Supply chain. Develop end-to-end silicon NPI strategy. Drive Design for Manufacturing (DFM) requirements", "postedDate" : "2026-06-13T13:25:26.963", "createdAt" : "2026-06-13T13:25:26.963", "lastUpdated" : "2026-06-15T04:32:58.572", "ingestTimestamp" : "2026-06-13T13:25:26.963", "mongoId" : "69fda4e54c40e2acd1b99a28", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10412734/apply", "salaryAnnualMin" : 206700, "salaryAnnualMax" : 279600, "salaryBand" : "200k+", "hasSalary" : true, "allSkills" : [ "Semiconductor operations", "Product engineering", "Silicon wafer fab", "3D packaging", "ASIC development", "Strategic Leadership", "Silicon NPI", "Manufacturing", "Supply chain", "Manufacturing yield", "Supply chain readiness", "Cost optimization", "Design for Manufacturing", "Design for Test", "Wafer fabrication", "Assembly", "Test processes", "Advanced packaging", "Vendor management", "Contract manufacturer strategy", "Material procurement", "Program execution", "Quality standards", "Reliability specifications", "Semiconductor manufacturing", "New Product Introduction (NPI)" ], "skillCount" : 26, "jobCategory" : "project-management", "dataQualityScore" : 1.0, "_score" : 671.12427, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a2a65f774d8ee00a062b387", "title" : "Strategic Sourcing Manager, Silicon Operations", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Project/Program/Product Management--Technical, Technical Program Management, alexa and amazon devices", "salary" : { "min" : 171000.0, "max" : 231400.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Sunnyvale, California, USA", "locations" : [ "Sunnyvale, California, USA" ], "timestamp" : "2026-06-15T00:57:24.262", "fingerprint" : "88dd0de0c55b3318e364e3fdd9825a72e0e53b9bd320fd9d427d679691eab86e", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10441773/apply", "externalId" : "91f84f84-1c27-49a4-ae9a-b4a47b717ef7", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 5, "experienceLevel" : "Manager", "technicalSkills" : "Cloud computing services, Deployment architecture", "professionalSkills" : [ "Business operations", "Supply chain management", "Sales order management", "Inventory management", "Supply planning", "Demand planning", "Material allocations", "Fulfillment", "Process improvement", "Supplier performance management", "Cross-functional initiatives", "Business relationships" ], "hardSkillsList" : [ "Operations models" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Operations models", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "Strategic sourcing, Business operations, Supply chain management", "majorSkillsList" : [ "Strategic sourcing", "Business operations", "Supply chain management" ], "coreResponsibilities" : "Support business stakeholders, Support engineering stakeholders, Select technology suppliers, Develop technology suppliers, Manage technology suppliers, Select service suppliers, Develop service suppliers, Manage service suppliers, Execute Amazon Leo objectives, Develop operations models, Oversee supply chain, Oversee sales orders, Oversee inventory management, Plan supply, Plan demand, Manage inventory, Allocate materials, Manage sales orders, Manage fulfillment, Establish wafer supply chain process, Establish ASIC supply chain process, Establish business structure, Manage inventory, Set goals, Set strategic directions, Drive automation, Drive process improvements, Lead operational collaboration suppliers, Lead operational collaboration internal customers, Provide leadership project selection, Provide leadership project scope, Provide leadership project definition, Provide leadership project performance, Align with business strategy, Train team members new processes, Ensure effective communication change", "teamCollaboration" : "Cross-functional teams; Internal customers; Executive level stakeholders", "projectManagementSkills" : [ "Program management", "Agile", "Release schedules" ], "domainKnowledge" : "Silicon operations; ASIC supply chain; Wafer supply chain", "domainList" : [ "silicon-operations", "asic-supply-chain", "wafer-supply-chain" ], "domainSpecificKnowledge" : [ "Silicon operations", "ASIC supply chain", "Wafer supply chain" ], "communicationSkills" : "Executive presentations; Technical writing", "problemSolvingSkills" : "Complex problems", "specialRequirements" : "Export control requirement", "qualificationsBasic" : "5+ years technical product management, 5+ years program management, Manage programs across cross functional teams, Build processes, Coordinate release schedules, Bachelor's degree engineering, Bachelor's degree computer science, U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S. as refugee, Granted asylum", "qualificationsPreferred" : "Define KPI's/SLA's, Report to senior leadership, Knowledge of cloud computing services, Knowledge of deployment architecture, Experience internet-related program, Experience technical product management software applications, Master's degree, 7+ years work internet-related program, 7+ years work technical product management software applications, Communicate across technical audiences, Communicate across non-technical audiences, Communicate with executive level stakeholders, Communicate with clients, Experience agile program management, Experience other program management methodologies", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Leo is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Amazon Leo team is looking for a Business Operations Manager to support business and engineering stakeholders in selecting, developing and managing business relationships with critical technology and service suppliers, and others as needed to execute on Amazon Leo objectives. The ideal candidate will have a successful track record developing and executing strategy, and managing supplier performance. Experience working in new and ambiguous environments while solving complex problems with a broad range of cross functional stakeholders will be an advantage. Key job responsibilities Be the Leader for ASIC Global Business Operations. Develops operations models and oversees supply chain, sales orders and inventory management. Responsible for supply and demand planning, inventory management, material allocations, sales orders, and fulfillment. Lead cross-functional Initiatives to establish wafer and ASIC supply chain process and overall structure of the business. Leading supply chain and inventory management, setting goals, and strategic directions, and driving automation and process improvements. Lead and drive operational collaboration with suppliers and internal customers. Provide leadership on project selection, scope, definition and performance to ensure alignment with business strategy. Train team members on new processes and ensure effective communication of change. Basic Qualifications: - 5+ years of technical product or program management experience - Experience managing programs across cross functional teams, building processes and coordinating release schedules - Bachelor's degree in engineering, computer science or equivalent Preferred Qualifications: - Experience defining KPI's/SLA's used to drive multi-million dollar businesses and reporting to senior leadership - Knowledge of cloud computing services or deployment architecture - Experience working in an internet-related program or technical product management in a software applications environment - Master's degree or equivalent - 7+ years of work in internet-related program or technical product management in a software applications environment experience - Experience communicating across technical and non-technical audiences, including executive level stakeholders or clients - Experience with agile or other program management methodologies Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Sunnyvale - 171,000.00 - 231,400.00 USD annually", "summaryDescription" : "Strategic Sourcing Manager, Silicon Operations at Amazon Kuiper Manufacturing Enterprises LLC. Skills: Strategic sourcing, Business operations, Supply chain management. Support business stakeholders. Support engineering stakeholders", "postedDate" : "2026-06-13T11:45:07.040", "createdAt" : "2026-06-13T11:45:07.040", "lastUpdated" : "2026-06-15T00:57:24.262", "ingestTimestamp" : "2026-06-13T11:45:07.040", "mongoId" : "6a2a65f774d8ee00a062b387", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10441773/apply", "salaryAnnualMin" : 171000, "salaryAnnualMax" : 231400, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Operations models", "Leadership", "Strategic sourcing", "Business operations", "Supply chain management", "Sales order management", "Inventory management", "Supply planning", "Demand planning", "Material allocations", "Fulfillment", "Process improvement", "Supplier performance management", "Cross-functional initiatives", "Business relationships", "Program management", "Agile", "Release schedules", "Silicon operations", "ASIC supply chain", "Wafer supply chain" ], "skillCount" : 21, "jobCategory" : "project-management", "dataQualityScore" : 1.0, "_score" : 665.77997, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a210e3374d8ee00a0af6359", "title" : "Software Engineer Manager II, Silicon Tools", "industry" : "Technology", "salary" : { "min" : 2200000.0, "max" : 3500000.0, "currency" : "TWD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Software Engineer Manager II in New Taipei City, Taiwan, adjusted for the technology industry and manager seniority." }, "location" : "[New Taipei, Banqiao District, New Taipei City, Taiwan, [Banqiao District, New Taipei City, Taiwan 220], null, 220, New Taipei City, TW]", "locations" : [ "[New Taipei, Banqiao District, New Taipei City, Taiwan, [Banqiao District, New Taipei City, Taiwan 220], null, 220, New Taipei City, TW]" ], "timestamp" : "2026-06-16T12:32:28.016", "fingerprint" : "9ed965af5439fb3a9c208ca2106054772e62b9ff57269f27dac612103bc55245", "source" : "google", "language" : "en", "externalId" : "137160042544538310", "industryFunction" : { }, "structuredLocations" : [ { "city" : "New Taipei City", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "25.0834547,121.4755340" } ], "locationText" : "New Taipei City, Taiwan", "experienceLevel" : "Manager", "summaryDescription" : "Software Engineer Manager II, Silicon Tools", "postedDate" : "2026-06-16T01:48:09.802", "createdAt" : "2026-06-16T01:48:09.802", "lastUpdated" : "2026-06-16T12:32:28.016", "ingestTimestamp" : "2026-06-16T01:48:09.802", "mongoId" : "6a210e3374d8ee00a0af6359", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Manager", "dataQualityScore" : 0.5555556, "_score" : 663.9054, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a30609ff292fd229cf9201b", "title" : "Junior ASIC Design Engineer", "company" : "Astera Labs", "industry" : "Technology", "salary" : { "min" : 180000.0, "max" : 270000.0, "currency" : "ILS", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Junior ASIC Design Engineer in Haifa, Israel, adjusted for entry-level seniority and the technology industry." }, "location" : "Haifa, Israel", "locations" : [ "Haifa", "Israel", "Tel Aviv", "Israel" ], "timestamp" : "2026-06-16T07:41:49.897", "fingerprint" : "38417ee06cf83642406e081430d6ac882d5a333bf1af74f1b1773c38cd45f3e3", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/asteralabs/jobs/4704182005", "externalId" : "4704182005", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Haifa", "country" : "Israel", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "32.8191218,34.9983856" } ], "locationText" : "Haifa, Israel", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 0, "experienceMaxYears" : 2, "experienceLevel" : "Entry", "technicalSkills" : "Verilog, SystemVerilog, RTL", "professionalSkills" : [ "Logic design", "Micro-architecture", "Implementation support" ], "hardSkillsList" : [ "Digital design principles", "RTL coding concepts" ], "softSkillsList" : [ "Adapt", "Collaborate" ], "hardSkills" : [ { "name" : "Digital design principles", "level" : "intermediate" }, { "name" : "RTL coding concepts", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Adapt" }, { "name" : "Collaborate" } ], "majorSkills" : "ASIC Design, Digital blocks, Connectivity projects", "majorSkillsList" : [ "ASIC Design", "Digital blocks", "Connectivity projects" ], "coreResponsibilities" : "Own the journey from high-level definition, Tackle complex logic challenges, Transform logic into hardware solutions, Serve as point of contact for logic blocks, Interact with Architecture teams, Interact with Verification teams, Interact with Backend teams, Utilize EDA tools, Utilize quality assurance tools, Ensure designs are robust, Ensure designs are scalable, Ensure designs are power-efficient, Apply design techniques, Meet PPA targets, Contribute to design quality, Participate in design methodology improvements, Participate in tool automation initiatives, Leverage AI assistance tools, Contribute to in-house automation development, Make engineering workflows faster, Make engineering workflows smarter, Collaborate effectively across teams, Ensure seamless integration", "teamCollaboration" : "Interacting with Architecture; Interacting with Verification; Interacting with Backend teams; Collaborate across teams", "domainKnowledge" : "AI infrastructure; Connectivity solutions; Deep-submicron processes", "domainList" : [ "ai-infrastructure", "connectivity-solutions", "deep-submicron-processes" ], "domainSpecificKnowledge" : [ "AI infrastructure", "Connectivity solutions", "Deep-submicron processes" ], "toolProficiency" : [ "Lint", "CDC", "Synthesis", "Timing", "Power" ], "communicationSkills" : "Communication skills", "innovationCreativity" : "Innovation", "problemSolvingSkills" : "Tackle complex logic challenges", "qualificationsBasic" : "Bachelor’s degree in Electrical Engineering, Bachelor’s degree in Computer Engineering, 0–2 years of experience in logic design, Foundational knowledge of Verilog, Foundational knowledge of SystemVerilog, Understanding of digital design principles, Understanding of fundamental RTL coding concepts", "qualificationsPreferred" : "Master's degree in Electrical Engineering, Master's degree in related field, Relevant internships valued, University labs valued, Hands-on academic projects valued", "workSiteFlexibility" : "Onsite", "rawDescription" : "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Junior ASIC Design Engineer, you won't just build chips - you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Responsibilities Design Ownership & Implementation Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams Quality Assurance & Design Optimization Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient Apply design techniques to meet PPA (Power, Performance, Area) targets Contribute to design quality through verification and validation activities Methodology Innovation & Collaboration Participate in design methodology improvements and tool automation initiatives Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter Collaborate effectively across teams to ensure seamless integration Basic Qualifications Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field. Experience: 0–2 years of experience in logic design (relevant internships, university labs, or hands-on academic projects are highly valued). Technical Skills: Foundational knowledge of Verilog and/or SystemVerilog. Strong understanding of digital design principles and fundamental RTL coding concepts. Soft Skills: Excellent communication skills with a strong motivation to learn, adapt, and collaborate effectively within cross-functional teams. Preferred Qualifications Master's degree in Electrical Engineering or related field We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "summaryDescription" : "Junior ASIC Design Engineer at Astera Labs. Skills: ASIC Design, Digital blocks, Connectivity projects. Own the journey from high-level definition. Tackle complex logic challenges", "postedDate" : "2026-06-15T23:26:39.928", "createdAt" : "2026-06-15T23:26:39.928", "lastUpdated" : "2026-06-16T07:41:49.897", "ingestTimestamp" : "2026-06-15T23:26:39.928", "mongoId" : "6a30609ff292fd229cf9201b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "150k-200k", "hasSalary" : false, "allSkills" : [ "Digital design principles", "RTL coding concepts", "Adapt", "Collaborate", "ASIC Design", "Digital blocks", "Connectivity projects", "Logic design", "Micro-architecture", "Implementation support", "AI infrastructure", "Connectivity solutions", "Deep-submicron processes", "Lint", "CDC", "Synthesis", "Timing", "Power" ], "skillCount" : 18, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Junior", "dataQualityScore" : 1.0, "_score" : 661.2696, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a210e4674d8ee00a0af6a81", "title" : "GPU Commodity Manager, Global Strategic Sourcing and Silicon Operations", "industry" : "Technology", "salary" : { "min" : 175000.0, "max" : 250000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level GPU Commodity Manager in Kirkland, United States, adjusted for the technology industry and manager experience." }, "location" : "[Kirkland, WA, USA, [Kirkland, WA, USA], Kirkland, null, WA, US]", "locations" : [ "[Kirkland, WA, USA, [Kirkland, WA, USA], Kirkland, null, WA, US]" ], "timestamp" : "2026-06-16T14:56:48.931", "fingerprint" : "1491c86ab9d31d7a8d11d504a9e8fb30e4a56e641597e89d25e88bb575da1cbd", "source" : "google", "language" : "en", "externalId" : "111590929806041798", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Kirkland", "state" : "Washington", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "47.6765382,-122.2070775" } ], "locationText" : "Kirkland, Washington, United States", "experienceLevel" : "Manager", "workSiteFlexibility" : "Onsite", "summaryDescription" : "GPU Commodity Manager, Global Strategic Sourcing and Silicon Operations", "postedDate" : "2026-06-16T01:48:31.130", "createdAt" : "2026-06-16T01:48:31.130", "lastUpdated" : "2026-06-16T14:56:48.931", "ingestTimestamp" : "2026-06-16T01:48:31.130", "mongoId" : "6a210e4674d8ee00a0af6a81", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 175000, "salaryAnnualMax" : 250000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Mid", "dataQualityScore" : 0.5555556, "_score" : 658.4223, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a307f51f292fd229c057e7e", "title" : "Silicon DFT Engineer III", "company" : "Google", "industry" : "Technology", "salary" : { "min" : 3500000.0, "max" : 5500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for a Silicon DFT Engineer III at Google in Bengaluru, India, adjusted for mid-seniority and full-time employment." }, "location" : "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]", "locations" : [ "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]" ], "timestamp" : "2026-06-16T11:04:16.332", "fingerprint" : "9709c73a0820af4ca985d5d9b63659a07e0eaa48704412a4f22544cb9afd06f6", "source" : "google", "language" : "en", "externalId" : "123648462079042246", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "summaryDescription" : "Silicon DFT Engineer III at Google", "postedDate" : "2026-06-16T01:49:31.035", "createdAt" : "2026-06-16T01:49:31.035", "lastUpdated" : "2026-06-16T11:04:16.332", "ingestTimestamp" : "2026-06-16T01:49:31.035", "mongoId" : "6a307f51f292fd229c057e7e", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.6666667, "_score" : 658.3419, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a307f5cf292fd229c058628", "title" : "Global Supply Chain Manager, Silicon", "industry" : "Manufacturing", "salary" : { "min" : 1750000.0, "max" : 2750000.0, "currency" : "TWD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Manager in the Technology industry in Taipei, Taiwan, adjusted for seniority and full-time employment." }, "location" : "[Taipei, Taiwan, [110, Taiwan, Taipei City, Xinyi District, Ankang Village, Section 5, Xinyi Rd, 109號2樓], Ankang Village, 110, Taipei City, TW]", "locations" : [ "[Taipei, Taiwan, [110, Taiwan, Taipei City, Xinyi District, Ankang Village, Section 5, Xinyi Rd, 109號2樓], Ankang Village, 110, Taipei City, TW]" ], "timestamp" : "2026-06-16T11:26:42.192", "fingerprint" : "15bd91a5dc362d9b8cbbc1a8d33b863075fee7514fa80a8ac37891d8817a12eb", "source" : "google", "language" : "en", "externalId" : "107450229145379526", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Taipei", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "25.0375198,121.5636796" } ], "locationText" : "Taipei, Taiwan", "experienceLevel" : "Manager", "summaryDescription" : "Global Supply Chain Manager, Silicon", "postedDate" : "2026-06-16T01:51:23.542", "createdAt" : "2026-06-16T01:51:23.542", "lastUpdated" : "2026-06-16T11:26:42.192", "ingestTimestamp" : "2026-06-16T01:51:23.542", "mongoId" : "6a307f5cf292fd229c058628", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Manager", "dataQualityScore" : 0.5555556, "_score" : 650.25385, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a305191f292fd229cf02480", "title" : "Engineering Manager, Waste and Sustainability (NEA)", "company" : "GovTech", "industry" : "Government", "salary" : { "min" : 140000.0, "max" : 210000.0, "currency" : "SGD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Manager in Government in Singapore, adjusted for industry and company size." }, "location" : "NEA National Environment Agency", "locations" : [ "NEA National Environment Agency" ], "timestamp" : "2026-06-16T10:37:56.268", "fingerprint" : "e411126b37c9540d1960f7f954c81a6c275999168e85317a9fbc3a84af5185af", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://jobs.careers.gov.sg/jobs/greenhouse/4004084201?gh_jid=4004084201", "externalId" : "4004084201", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Singapore", "country" : "Singapore", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "1.2899175,103.8519072" } ], "locationText" : "Singapore, Singapore", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceLevel" : "Manager", "remoteFriendly" : true, "workSiteFlexibility" : "Flexible", "rawDescription" : "GovTech is the lead agency driving Singapore’s Smart Nation initiatives and public sector digital transformation. As the Centre of Excellence for Infocomm Technology and Smart Systems (ICT experience in modern front-end engineering like Next.Js/React.js and Java/TypeScript on the backend is preferred. Knowledge of cloud technology such as Azure, AWS and Docker or Kubernetes is preferred. Have a strong sense of what it means to be a technical leader, particularly as it relates to the suite of soft skills beyond just your technical chops.  Passion towards engineering excellence; you deeply understand that software engineering is a team sport, and you take pride in the craftsmanship aspect of software engineering.  Passion towards working for public good with interest.  The ability to guide a team to achieve important goals together.  Minimally 5+ year of development experience and 2+ years of experience coaching developers; helping them enhance their performance and grow their careers What we offer you: GovTech is an equal opportunity employer committed to fostering an inclusive workplace that values diverse voices and perspectives, as we believe that diversity is the foundation to innovation.    Our employee benefits are based on a total rewards approach, offering a holistic and market-competitive suite of perks. These include leave benefits to meet your work-life needs and employee wellness programs.  We champion flexible work arrangements (subject to your job role) and trust that you will manage your own time to deliver your best, wherever you are, and whatever works best for you.  Learn more about life inside GovTech at go.gov.sg/GovTechCareers. Stay connected with us on social media at go.gov.sg/ConnectWithGovTech", "summaryDescription" : "Engineering Manager, Waste and Sustainability (NEA) at GovTech", "postedDate" : "2026-06-15T23:21:54.492", "createdAt" : "2026-06-15T23:21:54.492", "lastUpdated" : "2026-06-16T10:37:56.268", "ingestTimestamp" : "2026-06-15T23:21:54.492", "mongoId" : "6a305191f292fd229cf02480", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "100k-150k", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Manager", "dataQualityScore" : 0.8888889, "_score" : 627.9791, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Government", "llmIndustryConfidence" : 0.95 }, { "id" : "6a210e4874d8ee00a0af6b63", "title" : "Silicon Design Verification Engineer", "industry" : "Technology", "location" : "[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US]", "locations" : [ "[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US]" ], "timestamp" : "2026-06-16T11:50:16.251", "fingerprint" : "33e14147a8aae8bf3d51e339e83ba763da13b226092318c482a6f7a091b2dd0e", "source" : "google", "language" : "en", "externalId" : "86602986070909638", "industryFunction" : { }, "technicalSkills" : "Verilog, SystemVerilog, UVM", "hardSkillsList" : [ "Design verification", "RTL design" ], "hardSkills" : [ { "name" : "Design verification", "level" : "intermediate" }, { "name" : "RTL design", "level" : "intermediate" } ], "majorSkills" : "Design verification, RTL design, SystemVerilog, UVM", "majorSkillsList" : [ "Design verification", "RTL design", "SystemVerilog", "UVM" ], "coreResponsibilities" : "Develop verification plans, Write verification environments, Execute verification tests, Debug failures, Document results, Collaborate with design teams, Improve verification methodologies", "teamCollaboration" : "Design teams; Cross-functional teams", "domainKnowledge" : "ASIC design; SoC architecture", "domainList" : [ "asic-design", "soc-architecture" ], "domainSpecificKnowledge" : [ "ASIC design", "SoC architecture" ], "toolProficiency" : [ "EDA tools" ], "communicationSkills" : "Technical documentation", "documentationSkills" : "Verification plans; Test results", "problemSolvingSkills" : "Root cause analysis", "outcomesObjectives" : "Achieve high verification coverage; Ensure silicon quality", "qualificationsBasic" : "5+ years experience, Bachelor's degree", "qualificationsPreferred" : "Master's degree preferred, PhD preferred", "workSiteFlexibility" : "Onsite", "summaryDescription" : "Silicon Design Verification Engineer. Skills: Design verification, RTL design, SystemVerilog, UVM. Develop verification plans. Write verification environments", "postedDate" : "2026-06-16T01:48:39.427", "createdAt" : "2026-06-16T01:48:39.427", "lastUpdated" : "2026-06-16T11:50:16.251", "ingestTimestamp" : "2026-06-16T01:48:39.427", "mongoId" : "6a210e4874d8ee00a0af6b63", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "hasSalary" : false, "allSkills" : [ "Design verification", "RTL design", "SystemVerilog", "UVM", "ASIC design", "SoC architecture", "EDA tools" ], "skillCount" : 7, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Mid", "dataQualityScore" : 0.44444445, "_score" : 618.97943, "daysOld" : 0, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.0 }, { "id" : "69d5e4952beec4dd3d931859", "title" : "Senior ASIC Design Engineer", "company" : "Amazon Technologies, Inc.", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 159000.0, "max" : 215300.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "San Diego, California, USA", "locations" : [ "San Diego, California, USA" ], "timestamp" : "2026-06-15T09:52:56.853", "fingerprint" : "4c4d7def052b1c1d6077329abbf6c24dab1c3adcdef406755c918bc043caf7a3", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10385600/apply", "externalId" : "164d406e-fb4b-4b88-862f-5c6a44d52db8", "industryFunction" : { }, "structuredLocations" : [ { "city" : "San Diego", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "32.7174202,-117.1627720" } ], "locationText" : "San Diego, California, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 7, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "CMOS, DSP, UVM, System C, DPI-C, Matlab", "professionalSkills" : [ "Wireless system architecture", "Chip specification", "Timing optimization", "Power optimization", "Chip level validation", "Trade-off analysis" ], "hardSkillsList" : [ "Digital design", "Low power design", "Wireless system design", "RTL design", "Timing closure", "Power analysis", "Verification test bench" ], "hardSkills" : [ { "name" : "Digital design", "level" : "intermediate" }, { "name" : "Low power design", "level" : "intermediate" }, { "name" : "Wireless system design", "level" : "intermediate" }, { "name" : "RTL design", "level" : "intermediate" }, { "name" : "Timing closure", "level" : "intermediate" }, { "name" : "Power analysis", "level" : "intermediate" }, { "name" : "Verification test bench", "level" : "intermediate" } ], "majorSkills" : "ASIC design, SOC design, Wireless communication", "majorSkillsList" : [ "ASIC design", "SOC design", "Wireless communication" ], "coreResponsibilities" : "Implement wireless system architecture in silicon, Develop solutions optimizing customer experience, Meet power and cost constraints, Drive high quality designs, Create standalone verification test bench, Verify correctness of your block, Participate in System level verification, Ensure block meets DFT targets, Ensure block meets timing targets, Ensure block meets power targets, Learn about systems operating in space, Drive trade-off analysis", "teamCollaboration" : "Customer requirements teams; Wireless system teams; Verification team; Implementation team", "domainKnowledge" : "Low Earth Orbit satellites; Broadband connectivity; Wireless communication systems; Space systems", "domainList" : [ "low-earth-orbit-satellites", "broadband-connectivity", "wireless-communication-systems", "space-systems" ], "domainSpecificKnowledge" : [ "Low Earth Orbit satellites", "Broadband connectivity", "Wireless communication systems", "Space systems" ], "toolProficiency" : [ "UVM", "System C", "DPI-C" ], "continuousLearning" : "Learn about systems operating in space", "innovationCreativity" : "Define a groundbreaking wireless solution", "problemSolvingSkills" : "Trade-off analysis", "specialRequirements" : "U. S. citizen or national, U. S. permanent resident, Lawfully admitted into the U. S.", "outcomesObjectives" : "Optimize customer experience; Meet power and cost constraints; Drive high quality designs; Meet power objectives", "qualificationsBasic" : "Bachelor's degree in Electrical Engineering, 7+ years of experience in digital design, Experience with products that have gone to volume production, Experience in low power design techniques", "qualificationsPreferred" : "10+ years of experience in digital design, Familiarity with UVM, Familiarity with Matlab, Ability to write assertions, Exposure to Formal verification", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Role: Be part of Amazon Leo’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation · Develop solutions optimizing customer experience (throughput, latency, and availability) while meeting power and cost constraints · Drive high quality designs for first-time right silicon solutions, and meeting the power objectives · Create standalone verification test bench to verify the correctness of your block · Work with the verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C · Ensure that the block meets DFT, timing and power targets by working closely with the implementation team · Learn about requirements and solutions for systems operating in space · Drive trade-off analysis to benefit customer experience and optimization of resources (costs, power, spectrum) Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Basic Qualifications: - Bachelor's degree in Electrical Engineering or a related field - 7+ years of experience in digital design, preferably in communication systems - Experience with products that have gone to volume production - Experience in low power design techniques Preferred Qualifications: - 10+ years of experience in digital design, preferably in communication systems - Familiarity with UVM and Matlab - Ability to write assertions and exposure to Formal verification - Strong written and verbal skills Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, San Diego - 159,200.00 - 215,300.00 USD annually", "summaryDescription" : "Senior ASIC Design Engineer at Amazon Technologies, Inc.. Skills: ASIC design, SOC design, Wireless communication. Implement wireless system architecture in silicon. Develop solutions optimizing customer experience", "postedDate" : "2026-06-13T17:15:55.737", "createdAt" : "2026-06-13T17:15:55.737", "lastUpdated" : "2026-06-15T09:52:56.853", "ingestTimestamp" : "2026-06-13T17:15:55.737", "mongoId" : "69d5e4952beec4dd3d931859", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10385600/apply", "salaryAnnualMin" : 159000, "salaryAnnualMax" : 215300, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Digital design", "Low power design", "Wireless system design", "RTL design", "Timing closure", "Power analysis", "Verification test bench", "ASIC design", "SOC design", "Wireless communication", "Wireless system architecture", "Chip specification", "Timing optimization", "Power optimization", "Chip level validation", "Trade-off analysis", "Low Earth Orbit satellites", "Broadband connectivity", "Wireless communication systems", "Space systems", "UVM", "System C", "DPI-C" ], "skillCount" : 23, "jobCategory" : "other", "dataQualityScore" : 1.0, "_score" : 607.1572, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" }, { "id" : "6a30577ff292fd229cf3a6ce", "title" : "Senior Sustainability Manager", "company" : "Monzo", "industry" : "FinTech", "salary" : { "min" : 90000.0, "currency" : "GBP", "frequency" : "yearly", "is_estimated" : false }, "location" : "London", "locations" : [ "London" ], "timestamp" : "2026-06-16T07:18:57.030", "fingerprint" : "f6cef0adcae579d40082be2fb2879b500f347a72f9842c6ec905e661a5a2c5ae", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/monzo/jobs/8007672", "externalId" : "8007672", "industryFunction" : { }, "structuredLocations" : [ { "city" : "London", "country" : "United Kingdom", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "51.5074456,-0.1277653" } ], "locationText" : "London, United Kingdom", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "professionalSkills" : [ "Regulatory analysis", "Risk management", "Legal research", "Compliance oversight" ], "hardSkillsList" : [ "Regulatory reporting", "Compliance monitoring", "Legal drafting", "Policy development" ], "hardSkills" : [ { "name" : "Regulatory reporting", "level" : "intermediate" }, { "name" : "Compliance monitoring", "level" : "intermediate" }, { "name" : "Legal drafting", "level" : "intermediate" }, { "name" : "Policy development", "level" : "intermediate" } ], "majorSkills" : "Legal compliance, Risk management, Regulatory analysis", "majorSkillsList" : [ "Legal compliance", "Risk management", "Regulatory analysis" ], "coreResponsibilities" : "Develop and implement compliance policies, Conduct regulatory risk assessments, Monitor adherence to regulations, Prepare regulatory reports, Advise on legal and compliance matters, Stay updated on regulatory changes, Manage compliance training programs, Investigate compliance breaches", "teamCollaboration" : "Cross-functional teams; Legal and compliance departments", "projectManagementSkills" : [ "Policy implementation" ], "domainKnowledge" : "Financial regulations; Risk management frameworks; Data privacy regulations", "domainList" : [ "financial-regulations", "risk-management-frameworks", "data-privacy-regulations" ], "domainSpecificKnowledge" : [ "Financial regulations", "Risk management frameworks", "Data privacy regulations" ], "toolProficiency" : [ "Compliance software" ], "communicationSkills" : "Regulatory reporting; Policy communication", "documentationSkills" : "Policy documentation; Compliance documentation", "continuousLearning" : "Regulatory updates", "problemSolvingSkills" : "Regulatory interpretation; Risk mitigation", "outcomesObjectives" : "Ensure regulatory compliance; Mitigate legal risks; Maintain strong compliance culture", "qualificationsBasic" : "5+ years experience in legal or compliance, Experience with financial regulations, Experience with risk management frameworks, Experience with regulatory reporting", "qualificationsPreferred" : "Experience in a fast-paced startup environment, Experience with data privacy regulations", "remoteFriendly" : true, "workSiteFlexibility" : "Remote", "rawDescription" : "\uD83D\uDE80 We’re on a mission to make money work for everyone. We’re waving goodbye to the complicated and confusing ways of traditional banking. After starting as a prepaid card, our product offering has grown a lot in the last 10 years in the UK. As well as personal and business bank accounts, we offer joint accounts, accounts for 16-17 year olds, a free kids account and credit cards in the UK, with more exciting things to come beyond. Our UK customers can also save, invest and combine their pensions with us. With our hot coral cards and get-paid-early feature, combined with financial education on social media and our award winning customer service, we have a long history of creating magical moments for our customers! We’re not about selling products - we want to solve problems and change lives through Monzo ❤️ \uD83D\uDCCD London | \uD83D\uDCB0circa £90k + Incentive Awards tied to your performance + Benefits | Hear from the team ✨ ⭐Our Sustainability team We’re looking for a Senior Sustainability Manager to help deliver and scale Monzo’s climate and sustainability work. This role sits in our Legal all employees are given Macbooks and for fully remote workers we will provide extra support for your work-from-home setup. ➕ Plus lots more! Read our full list of benefits. \uD83C\uDF08 The application journey has 3 key steps Call with Recruiter Initial Call with Hiring Manager Loop interviews Behavioural interview Role Specific interview This process should take around 2-3 weeks - your schedule is really important to us, so we promise to be as flexible as possible! We have some guidelines on using Artificial Intelligence (AI) to ace an application and interview at Monzo. You can read them here. You’ll hear from us throughout the application process, but if you’ve got any questions, please reach out to hiring@monzo.com. You can also use this email address to let us know if there’s anything we can do to make the process easier for you because of disability, neurodiversity or anything else. #LI-DH1 Equal opportunities for everyone Diversity and inclusion are a priority for us and we’re making sure we have lots of support for all of our people to grow at Monzo. At Monzo, we’re embracing diversity by fostering an inclusive environment for all people to do the best work of their lives with us. This is integral to our mission of making money work for everyone. You can read more in our blog, 2026 Diversity and Inclusion Report and 2025 Gender Pay Gap Report. We’re an equal opportunity employer. All applicants will be considered for employment without attention to age, ethnicity, religion, sex, sexual orientation, gender identity, family or parental status, national origin, or veteran, neurodiversity or disability status. If you have a preferred name, please use it to apply. We don't need full or birth names at application stage \uD83D\uDE0A", "summaryDescription" : "Senior Sustainability Manager at Monzo. Skills: Legal compliance, Risk management, Regulatory analysis. Develop and implement compliance policies. Conduct regulatory risk assessments", "postedDate" : "2026-06-15T23:22:13.146", "createdAt" : "2026-06-15T23:22:13.146", "lastUpdated" : "2026-06-16T07:18:57.030", "ingestTimestamp" : "2026-06-15T23:22:13.146", "mongoId" : "6a30577ff292fd229cf3a6ce", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "75k-100k", "hasSalary" : false, "allSkills" : [ "Regulatory reporting", "Compliance monitoring", "Legal drafting", "Policy development", "Legal compliance", "Risk management", "Regulatory analysis", "Legal research", "Compliance oversight", "Policy implementation", "Financial regulations", "Risk management frameworks", "Data privacy regulations", "Compliance software" ], "skillCount" : 14, "jobCategory" : "operations", "jobSubcategory" : "legal", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 603.9447, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "FinTech", "llmIndustryConfidence" : 0.95 }, { "id" : "6a307f2df292fd229c055ead", "title" : "Silicon Design Verification Engineer ll", "company" : "Google", "industry" : "Technology", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for a Mid-level Silicon Design Verification Engineer II at a large technology company in Bengaluru, India, adjusted for seniority and industry." }, "location" : "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]", "locations" : [ "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]" ], "timestamp" : "2026-06-16T10:47:21.154", "fingerprint" : "ea073ae23cdbd296211fcc41b91345e5b1b1fa35fc0204f4f69f91d1a08fe5d4", "source" : "google", "language" : "en", "externalId" : "86238684898042566", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "experienceMinYears" : 2, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "remoteFriendly" : false, "summaryDescription" : "Silicon Design Verification Engineer ll at Google", "postedDate" : "2026-06-16T01:48:28.545", "createdAt" : "2026-06-16T01:48:28.545", "lastUpdated" : "2026-06-16T10:47:21.154", "ingestTimestamp" : "2026-06-16T01:48:28.545", "mongoId" : "6a307f2df292fd229c055ead", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.6666667, "_score" : 603.54504, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a307f39f292fd229c0565f2", "title" : "Senior Silicon Product Manager, TPU Hardware", "industry" : "Technology", "salary" : { "min" : 195000.0, "max" : 285000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior Silicon Product Manager, TPU Hardware in Mountain View, United States, adjusted for seniority and industry." }, "location" : "[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US]", "locations" : [ "[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US]" ], "timestamp" : "2026-06-16T12:56:01.313", "fingerprint" : "591af8efa36110e555c65dd5ad9ced15951c723390e0322cc50b5350798a1b0a", "source" : "google", "language" : "en", "externalId" : "75231995830903494", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Mountain View", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3893889,-122.0832101" } ], "locationText" : "Mountain View, California, United States", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "coreResponsibilities" : "Focus on product strategy, Develop product roadmap, Write user stories, Collaborate cross-functionally", "summaryDescription" : "Senior Silicon Product Manager, TPU Hardware. Focus on product strategy. Develop product roadmap", "postedDate" : "2026-06-16T01:51:51.310", "createdAt" : "2026-06-16T01:51:51.310", "lastUpdated" : "2026-06-16T12:56:01.313", "ingestTimestamp" : "2026-06-16T01:51:51.310", "mongoId" : "6a307f39f292fd229c0565f2", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 195000, "salaryAnnualMax" : 285000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "product", "jobSubcategory" : "product_management", "seniorityLevel" : "Senior", "dataQualityScore" : 0.5555556, "_score" : 592.5239, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a307f01f292fd229c054602", "title" : "Silicon Validation Engineer, Google Cloud", "company" : "Google", "industry" : "Technology", "salary" : { "min" : 175000.0, "max" : 250000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level Silicon Validation Engineer in Sunnyvale, CA, adjusted for Google's size and industry." }, "location" : "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]", "locations" : [ "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]" ], "timestamp" : "2026-06-16T11:26:23.664", "fingerprint" : "e0ea0ff7a4fe6c42b991f95f62a6c0a35f2a8b8473fee3f5bb29650c9cd6d570", "source" : "google", "language" : "en", "externalId" : "87066834049606342", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "summaryDescription" : "Silicon Validation Engineer, Google Cloud at Google", "postedDate" : "2026-06-16T01:49:09.635", "createdAt" : "2026-06-16T01:49:09.635", "lastUpdated" : "2026-06-16T11:26:23.664", "ingestTimestamp" : "2026-06-16T01:49:09.635", "mongoId" : "6a307f01f292fd229c054602", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 175000, "salaryAnnualMax" : 250000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.5555556, "_score" : 590.7552, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "68c2e436f8b1b0376634c802", "title" : "ASIC Verification Engineer, Blink/Ring ASIC Team", "company" : "Amazon Development Center Taiwan Limited", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 2200000.0, "max" : 3500000.0, "currency" : "TWD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Senior ASIC Verification Engineers in Hsinchu City, Taiwan, adjusted for the technology industry and large company size." }, "location" : "Hsinchu City, TWN", "locations" : [ "Hsinchu City, TWN" ], "timestamp" : "2026-06-15T05:25:49.242", "fingerprint" : "56494f2ae4c94c53089192f4e749cc52bdc44cf951d85593b7648c0f51835d2d", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3073145/apply", "externalId" : "03e1c617-eccb-4c4d-8430-1293fe7d6030", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Hsinchu City", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "24.8402128,121.0177998" } ], "locationText" : "Hsinchu City, Taiwan", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 6, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "technicalSkills" : "C, C++, Python, TCL, System Verilog, UVM", "professionalSkills" : [ "Architectural modeling", "Micro-architectural trade-offs", "Silicon validation", "Post-silicon validation" ], "hardSkillsList" : [ "Block level testplans", "System level testplans", "Traffic generators", "Scoreboards" ], "hardSkills" : [ { "name" : "Block level testplans", "level" : "intermediate" }, { "name" : "System level testplans", "level" : "intermediate" }, { "name" : "Traffic generators", "level" : "intermediate" }, { "name" : "Scoreboards", "level" : "intermediate" } ], "majorSkills" : "ASIC Verification, SoC Verification, System Verilog, UVM", "majorSkillsList" : [ "ASIC Verification", "SoC Verification", "System Verilog", "UVM" ], "coreResponsibilities" : "Build bit accurate C models, Evaluate block testability, Evaluate sub-systems testability, Write block level testplans, Write system level testplans, Build assertions, Build traffic generators, Build scoreboards, Execute testplans, Perform debug", "teamCollaboration" : "Vertically integrated team", "domainKnowledge" : "Image processing; AI; Video processing; Low power communications; CMOS fabrication", "domainList" : [ "image-processing", "ai", "video-processing", "low-power-communications", "cmos-fabrication" ], "domainSpecificKnowledge" : [ "Image processing", "AI", "Video processing", "Low power communications", "CMOS fabrication" ], "communicationSkills" : "Written skills; Verbal skills", "problemSolvingSkills" : "Rigorous debug", "qualificationsBasic" : "Bachelor's degree, 6+ years experience digital verification, 3+ years C/C++, 3+ years scripting, 6+ years System Verilog, 6+ years UVM", "qualificationsPreferred" : "Master's or PH. D, 8+ years experience digital verification, Familiarity with formal verification, Lab debug experience, FPGA debug experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Our verification team is involved in early architectural and micro-architectural trade-offs to reduce time-to-revenue by shortening the DV cycle. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Use and/or build bit accurate C models - Evaluate block and sub-systems for testability/verifiability - Write comprehensive block and system level testplans - Build assertions, traffic generators and scoreboards - Execute testplans and perform rigorous debug Basic Qualifications: - Bachelor's degree in Electrical / Computer Engineering or related field - 6+ years experience in digital verification, preferably in image processor, SoC/Interfaces - 3+ years of experience in C/C++ and scripting (Python or TCL) - 6+ years experience in System Verilog or UVM Preferred Qualifications: - Master's or PH.D in Computer Engineering - 8+ years of experience in digital verification, preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - Strong written and verbal skills Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "ASIC Verification Engineer, Blink/Ring ASIC Team at Amazon Development Center Taiwan Limited. Skills: ASIC Verification, SoC Verification, System Verilog, UVM. Build bit accurate C models. Evaluate block testability", "postedDate" : "2026-06-14T06:37:47.347", "createdAt" : "2026-06-14T06:37:47.347", "lastUpdated" : "2026-06-15T05:25:49.242", "ingestTimestamp" : "2026-06-14T06:37:47.347", "mongoId" : "68c2e436f8b1b0376634c802", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3073145/apply", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Block level testplans", "System level testplans", "Traffic generators", "Scoreboards", "ASIC Verification", "SoC Verification", "System Verilog", "UVM", "Architectural modeling", "Micro-architectural trade-offs", "Silicon validation", "Post-silicon validation", "Image processing", "AI", "Video processing", "Low power communications", "CMOS fabrication" ], "skillCount" : 17, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 1.0, "_score" : 586.7799, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a210e4d74d8ee00a0af6c66", "title" : "Engineering Manager, Operations Intelligence, gUP Engineering", "salary" : { "min" : 175000.0, "max" : 250000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for an Engineering Manager in Pittsburgh, USA, adjusted for seniority, industry, and company size." }, "location" : "[Pittsburgh, PA, USA, [Pittsburgh, PA, USA], Pittsburgh, null, PA, US]", "locations" : [ "[Pittsburgh, PA, USA, [Pittsburgh, PA, USA], Pittsburgh, null, PA, US]", "[Boulder, CO, USA, [Boulder, CO, USA], Boulder, null, CO, US]", "[Irvine, CA, USA, [Irvine, CA, USA], Irvine, null, CA, US]", "[Sunnyvale, CA, USA, [Sunnyvale, CA, USA], Sunnyvale, null, CA, US]" ], "timestamp" : "2026-06-16T11:27:21.990", "fingerprint" : "2c40decc35bcb79f1de61dd857932a7aaabe93b5b026a0f1927e553b86947123", "source" : "google", "language" : "en", "externalId" : "81538390800900806", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Pittsburgh", "state" : "Pennsylvania", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "40.4406968,-80.0025666" } ], "locationText" : "Pittsburgh, Pennsylvania, United States", "experienceLevel" : "Manager", "remoteFriendly" : false, "summaryDescription" : "Engineering Manager, Operations Intelligence, gUP Engineering", "postedDate" : "2026-06-16T01:48:31.944", "createdAt" : "2026-06-16T01:48:31.944", "lastUpdated" : "2026-06-16T11:27:21.990", "ingestTimestamp" : "2026-06-16T01:48:31.944", "mongoId" : "6a210e4d74d8ee00a0af6c66", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 175000, "salaryAnnualMax" : 250000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Manager", "dataQualityScore" : 0.5555556, "_score" : 550.90546, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a307f98f292fd229c05b1ef", "title" : "Senior Physical Design Engineer, Cloud Silicon", "industry" : "Technology", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for Senior Physical Design Engineer, Cloud Silicon in Bengaluru, India, adjusted for seniority and industry." }, "location" : "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]", "locations" : [ "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]" ], "timestamp" : "2026-06-16T12:05:10.670", "fingerprint" : "d100aa281c0e739cc3acb367760fe65865c2a4474e29dfd17e25974275ca7539", "source" : "google", "language" : "en", "externalId" : "91250802210808518", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "summaryDescription" : "Senior Physical Design Engineer, Cloud Silicon", "postedDate" : "2026-06-16T01:52:10.957", "createdAt" : "2026-06-16T01:52:10.957", "lastUpdated" : "2026-06-16T12:05:10.670", "ingestTimestamp" : "2026-06-16T01:52:10.957", "mongoId" : "6a307f98f292fd229c05b1ef", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.5555556, "_score" : 548.11273, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a307f55f292fd229c0580b8", "title" : "Senior Software Engineer, System Acceleration, Silicon", "industry" : "Technology", "salary" : { "min" : 1750000.0, "max" : 2500000.0, "currency" : "TWD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Senior Software Engineer in New Taipei City, Taiwan, adjusted for the technology industry and senior experience level." }, "location" : "[New Taipei, Banqiao District, New Taipei City, Taiwan, [Banqiao District, New Taipei City, Taiwan 220], null, 220, New Taipei City, TW]", "locations" : [ "[New Taipei, Banqiao District, New Taipei City, Taiwan, [Banqiao District, New Taipei City, Taiwan 220], null, 220, New Taipei City, TW]" ], "timestamp" : "2026-06-16T11:48:01.613", "fingerprint" : "526dbdc103c383edb21e878c979fea585a1c4ae0676bfbd801fdddf98613a4c4", "source" : "google", "language" : "en", "externalId" : "95806293633049286", "industryFunction" : { }, "structuredLocations" : [ { "city" : "New Taipei City", "country" : "Taiwan", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "25.0834547,121.4755340" } ], "locationText" : "New Taipei City, Taiwan", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "summaryDescription" : "Senior Software Engineer, System Acceleration, Silicon", "postedDate" : "2026-06-16T01:49:47.552", "createdAt" : "2026-06-16T01:49:47.552", "lastUpdated" : "2026-06-16T11:48:01.613", "ingestTimestamp" : "2026-06-16T01:49:47.552", "mongoId" : "6a307f55f292fd229c0580b8", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.5555556, "_score" : 548.0118, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a307f5ff292fd229c05887c", "title" : "Senior Silicon Physical Design STA Engineer", "industry" : "Technology", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior Silicon Physical Design STA Engineer in Bengaluru, India, adjusted for seniority and industry." }, "location" : "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]", "locations" : [ "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]" ], "timestamp" : "2026-06-16T08:51:42.265", "fingerprint" : "baef068bb83f0d3f7a6eea7cb0cda8534e0dadb33c13784b235b4b1cb42d04de", "source" : "google", "language" : "en", "externalId" : "95720866733531846", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "remoteFriendly" : false, "summaryDescription" : "Senior Silicon Physical Design STA Engineer", "postedDate" : "2026-06-16T01:49:06.361", "createdAt" : "2026-06-16T01:49:06.361", "lastUpdated" : "2026-06-16T08:51:42.265", "ingestTimestamp" : "2026-06-16T01:49:06.361", "mongoId" : "6a307f5ff292fd229c05887c", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.5555556, "_score" : 547.9827, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a210e3e74d8ee00a0af66e4", "title" : "Staff Front-End CAD Engineer, Silicon", "industry" : "Technology", "salary" : { "min" : 220000.0, "max" : 300000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Staff Front-End CAD Engineer in San Diego, adjusted for lead seniority and the technology industry." }, "location" : "[San Diego, CA, USA, [San Diego, CA, USA], San Diego, null, CA, US]", "locations" : [ "[San Diego, CA, USA, [San Diego, CA, USA], San Diego, null, CA, US]", "[Mountain View, CA, USA, [Mountain View, CA, USA], Mountain View, null, CA, US]" ], "timestamp" : "2026-06-16T10:56:38.835", "fingerprint" : "ecde316ad23018d5234d395dfb6af2a9a1c58367534204ac19c0dacb9025c0cb", "source" : "google", "language" : "en", "externalId" : "83747129272476358", "industryFunction" : { }, "structuredLocations" : [ { "city" : "San Diego", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "32.7174202,-117.1627720" } ], "locationText" : "San Diego, California, United States", "experienceMinYears" : 8, "experienceMaxYears" : 15, "experienceLevel" : "Staff", "summaryDescription" : "Staff Front-End CAD Engineer, Silicon", "postedDate" : "2026-06-16T01:48:21.025", "createdAt" : "2026-06-16T01:48:21.025", "lastUpdated" : "2026-06-16T10:56:38.835", "ingestTimestamp" : "2026-06-16T01:48:21.025", "mongoId" : "6a210e3e74d8ee00a0af66e4", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 220000, "salaryAnnualMax" : 300000, "salaryBand" : "200k+", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 0.5555556, "_score" : 547.9508, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a307f9df292fd229c05b53f", "title" : "Silicon Design Verification Engineer, Google Cloud", "company" : "Google", "industry" : "Technology", "salary" : { "min" : 2500000.0, "max" : 4500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for a Mid-level Silicon Design Verification Engineer in Bengaluru, India, adjusted for Google's size and industry." }, "location" : "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]", "locations" : [ "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]" ], "timestamp" : "2026-06-16T12:15:40.968", "fingerprint" : "17d4b07e04d687ec9dfc4c8e00b5c12ee16eaa1e389e55bddac1e04f9d1e8f9c", "source" : "google", "language" : "en", "externalId" : "89680811275494086", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "remoteFriendly" : false, "summaryDescription" : "Silicon Design Verification Engineer, Google Cloud at Google", "postedDate" : "2026-06-16T01:50:47.892", "createdAt" : "2026-06-16T01:50:47.892", "lastUpdated" : "2026-06-16T12:15:40.968", "ingestTimestamp" : "2026-06-16T01:50:47.892", "mongoId" : "6a307f9df292fd229c05b53f", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.5555556, "_score" : 545.8405, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a308bc0f292fd229c09a266", "title" : "Manager II, IT Engineering, Operations", "company" : "Flywire", "industry" : "Financial Services", "salary" : { "min" : 65000.0, "max" : 95000.0, "currency" : "EUR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for IT Engineering Managers in València, Spain, adjusted for manager seniority and FinTech industry." }, "location" : "València, VC, Spain", "locations" : [ "València", "VC", "Spain" ], "timestamp" : "2026-06-16T11:30:35.811", "fingerprint" : "451c09a4f7576500810097f5b77321a4fdf1b1d86d93d9648fb747293cae6530", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Flywire1/744000132249911-manager-ii-it-engineering-operations", "externalId" : "744000132249911", "industryFunction" : { }, "structuredLocations" : [ { "city" : "València", "state" : "Valencian Community", "country" : "Spain", "continent" : "eu", "source" : "llm", "workMode" : "hybrid", "geo" : "39.4697065,-0.3763353" } ], "locationText" : "València, Valencian Community, Spain", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "remoteFriendly" : false, "rawDescription" : "Are you ready to trade your job for a journey? Become a FlyMate! Passion, excitement & global collaboration are all core to what it means to be a FlyMate. At Flywire, we’re on a mission to deliver the world’s most important and complex payments. We use our Flywire Advantage - the combination of our next-gen payments platform, proprietary payment network and vertical specific software, to help our clients get paid, and help their customers pay with ease - no matter where they are in the world. What more do we need to truly be unstoppable? Perhaps, that is you! Who we are: Flywire is a global payments enablement and software company, founded a decade ago to solve high-stakes, high-value payments in education, using modern technology. Today, we’ve digitized payments for more than 3,300+ global clients across education, healthcare, travel & B2B, covering more than 240 countries and territories and supporting over 140 currencies. And, we’re just getting started! With over 1000+ global FlyMates, representing more than 40 nationalities, and in 14 offices world-wide, we’re looking for FlyMates to join the next stage of our journey as we continue to grow. Flywire is looking for a strategic and technically grounded Manager II, IT Engineering, Operations to lead our global IT Operations team and help shift it from reactive support to a proactive, engineering-led function. We are predominantly focused on hiring into our Valencia HQ, with office attendance a few times per week. You will bridge business needs and technical execution, manage team capacity and maintain excellence across our core SaaS stack while identifying opportunities to automate and apply AI-driven solutions. You will also own operational compliance and act as the primary liaison between IT Support and our specialised IT Cloud / CPE teams. Key Responsibilities Operational Excellence and Continuous Improvement Analyse workflows and system behaviours to identify inefficiencies. Apply Lean principles to streamline and document scalable processes before introducing automation. Strategy and AI Innovation Shift the team’s focus from ticket resolution to system evolution. Lead research and implementation of AI / AIOps to automate recurring issues and improve internal self-service. Operational Ownership of SaaS-as-Code Partner with CPE to transition our core stack into a Terraform-managed environment. Lead IT Ops in operating these systems through code, moving away from manual console configuration. Capacity and Project Management Manage team bandwidth across Tier 3 operations and strategic projects, including M&A and tool consolidation, ensuring daily noise does not stall innovation. Access Governance and Compliance Own Access Recertification, User Access Reviews and IT audit requirements, including SOC2. Make compliance more streamlined and automated, rather than manually intensive. Cross-Functional Leadership Partner with IT Support to build useful automations and collaborate with IT Cloud / CPE on operational support for high-level infrastructure changes. What We Are Looking For Product Mindset You analyse root causes, not just symptoms, and build scalable internal solutions. You understand how AI can improve modern IT operations. Execution Focus Strong Agile / Kanban skills to visualise capacity and prioritise high-impact work over busy work. Collaborative Leader Able to influence and collaborate with technical leads across CPE / Cloud, as well as non-technical stakeholders across HR, Finance and other functions. Change Agent Comfortable leading teams through technical transitions, including moving from manual console administration to SaaS-as-Code environments. ## Qualifications Basic Qualifications * Bachelor’s degree in Information Technology, Computer Science or equivalent professional experience * 10+ years in IT, including 4+ years managing international, remote-first technical teams * Experience managing global SaaS ecosystems such as Okta, Google Workspace, Slack and Atlassian * Strong understanding of IAM / RBAC logic * Experience with distributed teams and multi-regional IT infrastructure * Strong background managing technical controls and User Access Reviews Preferred Qualifications * Experience in FinTech, global payments or publicly traded technology companies * Familiarity with Terraform or other IaC tools applied to SaaS management * Deep expertise in AI / ML-powered IT operations and transformational technology roadmaps * Lean IT, Six Sigma or ITIL certification or experience focused on continuous improvement ## Additional Information We Offer: * Employee Stock Purchase Plan (ESPP) * Work with brilliant people that will keep you on your toes, learn more about their journeys by checking out #InsideFlywire on social media * Dynamic & Global Team (we have been collaborating virtually for years!) * Wellbeing Programs (Mental Health, Wellness, Yoga/Pilates/HIIT Classes) with Global FlyMates * Be a meaningful part in our success - every FlyMate makes an impact * Competitive time off including FlyBetter Days to volunteer in a cause you believe in and Digital Disconnect Days! * Work From Home Stipend * Great Talent & Development Programs (Managers Taking Flight – for new or aspiring managers!) Submit today and get started! We are excited to get to know you! Throughout our process you can expect to meet with different FlyMates including the Hiring Manager, Peers on the team, the VP of the department, and a skills assessment. Your Talent Acquisition Partner will walk you through the steps and be your “go-to” person for any questions. Flywire is an equal opportunity employer. With over 30 nationalities across 12 different offices, and diversity and inclusion at the core of our people agenda, we believe our FlyMates are our greatest asset, and we’re excited to watch our unique culture evolve with each new hire. Flywire is an equal opportunity employer. #LI-Hybrid", "summaryDescription" : "Manager II, IT Engineering, Operations at Flywire", "postedDate" : "2026-06-15T17:16:40.000", "createdAt" : "2026-06-16T03:37:58.022", "lastUpdated" : "2026-06-16T11:30:35.811", "ingestTimestamp" : "2026-06-16T03:37:58.022", "mongoId" : "6a308bc0f292fd229c09a266", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "50k-75k", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Manager", "dataQualityScore" : 0.8888889, "_score" : 544.43787, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "FinTech", "llmIndustryConfidence" : 0.95 }, { "id" : "6a306dccf292fd229cfda724", "title" : "Manager II, IT Engineering, Operations", "company" : "Flywire", "industry" : "Financial Services", "salary" : { "min" : 65000.0, "max" : 95000.0, "currency" : "EUR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for IT Engineering Managers in València, Spain, adjusted for manager seniority and FinTech industry." }, "location" : "València, VC, Spain", "locations" : [ "València", "VC", "Spain" ], "timestamp" : "2026-06-16T10:50:29.940", "fingerprint" : "527e7b16ee850b5eba323903eee43a669856fd5d3ef58de9fce79a40ee7516c9", "source" : "smartrecruiters", "language" : "en", "applyUrl" : "https://jobs.smartrecruiters.com/Flywire1/744000132249911-manager-ii-it-engineering-operations", "externalId" : "744000132249911", "industryFunction" : { }, "structuredLocations" : [ { "city" : "València", "state" : "Valencian Community", "country" : "Spain", "continent" : "eu", "source" : "llm", "workMode" : "hybrid", "geo" : "39.4697065,-0.3763353" } ], "locationText" : "València, Valencian Community, Spain", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "mid", "remoteFriendly" : false, "rawDescription" : "Are you ready to trade your job for a journey? Become a FlyMate! Passion, excitement & global collaboration are all core to what it means to be a FlyMate. At Flywire, we’re on a mission to deliver the world’s most important and complex payments. We use our Flywire Advantage - the combination of our next-gen payments platform, proprietary payment network and vertical specific software, to help our clients get paid, and help their customers pay with ease - no matter where they are in the world. What more do we need to truly be unstoppable? Perhaps, that is you! Who we are: Flywire is a global payments enablement and software company, founded a decade ago to solve high-stakes, high-value payments in education, using modern technology. Today, we’ve digitized payments for more than 3,300+ global clients across education, healthcare, travel & B2B, covering more than 240 countries and territories and supporting over 140 currencies. And, we’re just getting started! With over 1000+ global FlyMates, representing more than 40 nationalities, and in 14 offices world-wide, we’re looking for FlyMates to join the next stage of our journey as we continue to grow. Flywire is looking for a strategic and technically grounded Manager II, IT Engineering, Operations to lead our global IT Operations team and help shift it from reactive support to a proactive, engineering-led function. We are predominantly focused on hiring into our Valencia HQ, with office attendance a few times per week. You will bridge business needs and technical execution, manage team capacity and maintain excellence across our core SaaS stack while identifying opportunities to automate and apply AI-driven solutions. You will also own operational compliance and act as the primary liaison between IT Support and our specialised IT Cloud / CPE teams. Key Responsibilities Operational Excellence and Continuous Improvement Analyse workflows and system behaviours to identify inefficiencies. Apply Lean principles to streamline and document scalable processes before introducing automation. Strategy and AI Innovation Shift the team’s focus from ticket resolution to system evolution. Lead research and implementation of AI / AIOps to automate recurring issues and improve internal self-service. Operational Ownership of SaaS-as-Code Partner with CPE to transition our core stack into a Terraform-managed environment. Lead IT Ops in operating these systems through code, moving away from manual console configuration. Capacity and Project Management Manage team bandwidth across Tier 3 operations and strategic projects, including M&A and tool consolidation, ensuring daily noise does not stall innovation. Access Governance and Compliance Own Access Recertification, User Access Reviews and IT audit requirements, including SOC2. Make compliance more streamlined and automated, rather than manually intensive. Cross-Functional Leadership Partner with IT Support to build useful automations and collaborate with IT Cloud / CPE on operational support for high-level infrastructure changes. What We Are Looking For Product Mindset You analyse root causes, not just symptoms, and build scalable internal solutions. You understand how AI can improve modern IT operations. Execution Focus Strong Agile / Kanban skills to visualise capacity and prioritise high-impact work over busy work. Collaborative Leader Able to influence and collaborate with technical leads across CPE / Cloud, as well as non-technical stakeholders across HR, Finance and other functions. Change Agent Comfortable leading teams through technical transitions, including moving from manual console administration to SaaS-as-Code environments. ## Qualifications Basic Qualifications * Bachelor’s degree in Information Technology, Computer Science or equivalent professional experience * 10+ years in IT, including 4+ years managing international, remote-first technical teams * Experience managing global SaaS ecosystems such as Okta, Google Workspace, Slack and Atlassian * Strong understanding of IAM / RBAC logic * Experience with distributed teams and multi-regional IT infrastructure * Strong background managing technical controls and User Access Reviews Preferred Qualifications * Experience in FinTech, global payments or publicly traded technology companies * Familiarity with Terraform or other IaC tools applied to SaaS management * Deep expertise in AI / ML-powered IT operations and transformational technology roadmaps * Lean IT, Six Sigma or ITIL certification or experience focused on continuous improvement ## Additional Information We Offer: * Employee Stock Purchase Plan (ESPP) * Work with brilliant people that will keep you on your toes, learn more about their journeys by checking out #InsideFlywire on social media * Dynamic & Global Team (we have been collaborating virtually for years!) * Wellbeing Programs (Mental Health, Wellness, Yoga/Pilates/HIIT Classes) with Global FlyMates * Be a meaningful part in our success - every FlyMate makes an impact * Competitive time off including FlyBetter Days to volunteer in a cause you believe in and Digital Disconnect Days! * Work From Home Stipend * Great Talent & Development Programs (Managers Taking Flight – for new or aspiring managers!) Submit today and get started! We are excited to get to know you! Throughout our process you can expect to meet with different FlyMates including the Hiring Manager, Peers on the team, the VP of the department, and a skills assessment. Your Talent Acquisition Partner will walk you through the steps and be your “go-to” person for any questions. Flywire is an equal opportunity employer. With over 30 nationalities across 12 different offices, and diversity and inclusion at the core of our people agenda, we believe our FlyMates are our greatest asset, and we’re excited to watch our unique culture evolve with each new hire. Flywire is an equal opportunity employer. #LI-Hybrid", "summaryDescription" : "Manager II, IT Engineering, Operations at Flywire", "postedDate" : "2026-06-15T17:16:40.000", "createdAt" : "2026-06-16T00:29:56.004", "lastUpdated" : "2026-06-16T10:50:29.940", "ingestTimestamp" : "2026-06-16T00:29:56.004", "mongoId" : "6a306dccf292fd229cfda724", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "50k-75k", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Manager", "dataQualityScore" : 0.8888889, "_score" : 544.43787, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "FinTech", "llmIndustryConfidence" : 0.95 }, { "id" : "69c94a889bc74574cbbb51d8", "title" : "Sr. NPI & Sustaining Ops Manager, Operation Program Management", "company" : "Amazon Innovation Center (Shenzhen) Company Limited", "industry" : "Project/Program/Product Management--Non-Tech, Program Management, alexa and amazon devices", "salary" : { "min" : 550000.0, "max" : 950000.0, "currency" : "CNY", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Senior NPI & Sustaining Ops Manager in Shenzhen, China, adjusted for seniority, company size, and the technology industry." }, "location" : "Shenzhen, CHN", "locations" : [ "Shenzhen, CHN" ], "timestamp" : "2026-06-15T01:03:57.281", "fingerprint" : "1db41ee3e4fd7634c77c6bd5975bb1592822e65803a03c53ccbae9eb743c9070", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3199565/apply", "externalId" : "628cd3f1-f48f-435e-9a0d-517fd99b4c82", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Shenzhen", "country" : "China", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "22.5445741,114.0545429" } ], "locationText" : "Shenzhen, China", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 7, "experienceLevel" : "Manager", "professionalSkills" : [ "Program management", "Project management", "Supply chain management", "Operations management" ], "hardSkillsList" : [ "Data analysis", "Metrics analysis", "Liability analysis", "Disposal planning" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Data analysis", "level" : "intermediate" }, { "name" : "Metrics analysis", "level" : "intermediate" }, { "name" : "Liability analysis", "level" : "intermediate" }, { "name" : "Disposal planning", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "NPI, Sustaining operations, Program management, Factory operations", "majorSkillsList" : [ "NPI", "Sustaining operations", "Program management", "Factory operations" ], "coreResponsibilities" : "Lead end-to-end programs from NPI development through program, Lead NPI program development to meet the launch, Attend NPI core team meetings, Attend on-site factory builds, Monitor program schedule and milestones, Manage CMs to ensure material and production line, Track material clear-to-build status, Drive resolution of material shortage escalations, Optimize supply chain flexibility, Ensure on-time customer shipments, Drive initiatives to mitigate material shortages, Mitigate excess inventory, Conduct liability analysis, Plan disposal at End of Manufacturing, Develop and qualify new supply base capabilities, Lead Post Ramp Qualification for sustaining programs, Ensure stable operations, Collaborate cross-functionally with global teams, Build partnerships, Drive execution within Amazon, Partner with functional teams, Deliver continuous manufacturing improvements, Deliver operational improvements", "teamCollaboration" : "Cross-functional teams; Global teams", "projectManagementSkills" : [ "Program management", "Project management" ], "domainKnowledge" : "New Product Introduction (NPI); Consumer electronics manufacturing; Supply chain flexibility; End of Manufacturing (EOM); Post Ramp Qualification (PRQ)", "domainList" : [ "new-product-introduction-npi", "consumer-electronics-manufacturing", "supply-chain-flexibility", "end-of-manufacturing-eom", "post-ramp-qualification-prq" ], "domainSpecificKnowledge" : [ "New Product Introduction (NPI)", "Consumer electronics manufacturing", "Supply chain flexibility", "End of Manufacturing (EOM)", "Post Ramp Qualification (PRQ)" ], "communicationSkills" : "Communicating results to senior leadership", "innovationCreativity" : "Inventive research and development", "problemSolvingSkills" : "Drive resolution of material shortage escalations; Drive initiatives to mitigate material shortages; Mitigate excess inventory", "specialRequirements" : "Travel up to 30%", "outcomesObjectives" : "Meet the launch schedule; Ensure material and production line readiness; Ensure on-time customer shipments; Ensure stable operations; Cost savings; Efficiency gains", "qualificationsBasic" : "Bachelor's degree, 7+ years of program or project management experience, Experience using data and metrics to determine and drive improvements, Experience owning program strategy, end to end delivery, and communicating results to senior leadership", "qualificationsPreferred" : "7+ years of driving process improvements experience, Engineering background with FATP development experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Amazon Devices is an inventive research and development company that designs and engineers high-profile consumer electronics. We began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Fire tablets, Fire TV, Amazon Echo. What will you help us to create? This position (NPI and Sustaining Ops Mgr) is responsible for delivering all products from development to launch and manage them through sustaining period to end of life. The scope of responsibility for this position covers various aspects of operation functions including operation program manager, materials program manager and factory operations in both NPI and sustaining stage. Roles and Responsibilities: Lead end-to-end programs from NPI development through program EOM, with full cross-functional ownership and accountability. • Lead NPI program development to meet the launch schedule • Attend NPI core team meetings and on-site factory builds to closely monitor program schedule and milestones. • Manage CMs to ensure material and production line readiness for new product introduction. • Track material clear-to-build status and drive resolution of material shortage escalations from CMs. • Optimize supply chain flexibility to respond to demand fluctuations and ensure on-time customer shipments during mass production. • Drive initiatives to mitigate material shortages and excess inventory across the product lifecycle; conduct liability analysis and disposal planning at End of Manufacturing (EOM). • Develop and qualify new supply base capabilities to support cost and sourcing strategies. • Lead Post Ramp Qualification (PRQ) for sustaining programs to ensure stable operations. • Collaborate cross-functionally with global teams to build strong partnerships and drive execution within Amazon. • Partner with functional teams to deliver continuous manufacturing and operational improvements for cost savings and efficiency gains. • Able to travel up to 30%, primarily domestic/local travel. Basic Qualifications: - Bachelor's degree - 7+ years of program or project management experience - Experience using data and metrics to determine and drive improvements - Experience owning program strategy, end to end delivery, and communicating results to senior leadership Preferred Qualifications: - 7+ years of driving process improvements experience - Engineering background with FATP development experience. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "Sr. NPI & Sustaining Ops Manager, Operation Program Management at Amazon Innovation Center (Shenzhen) Company Limited. Skills: NPI, Sustaining operations, Program management, Factory operations. Lead end-to-end programs from NPI development through program. Lead NPI program development to meet the launch", "postedDate" : "2026-06-13T08:06:48.794", "createdAt" : "2026-06-13T08:06:48.794", "lastUpdated" : "2026-06-15T01:03:57.281", "ingestTimestamp" : "2026-06-13T08:06:48.794", "mongoId" : "69c94a889bc74574cbbb51d8", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3199565/apply", "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ "Data analysis", "Metrics analysis", "Liability analysis", "Disposal planning", "Leadership", "NPI", "Sustaining operations", "Program management", "Factory operations", "Project management", "Supply chain management", "Operations management", "New Product Introduction (NPI)", "Consumer electronics manufacturing", "Supply chain flexibility", "End of Manufacturing (EOM)", "Post Ramp Qualification (PRQ)" ], "skillCount" : 17, "jobCategory" : "project-management", "dataQualityScore" : 1.0, "_score" : 541.18463, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Consumer Electronics" }, { "id" : "68c2e42af8b1b0376634c688", "title" : "ASIC Engineering Internship (Summer 2026)", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Hardware Development, ASIC, studentprograms", "salary" : { "min" : 104000.0, "max" : 212200.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Redmond, Washington, USA", "locations" : [ "Redmond, Washington, USA" ], "timestamp" : "2026-06-15T07:09:39.803", "fingerprint" : "da736d023ba4b09cfcb0b1771eac4624cf77a2f74789cd5ae71f2ab81d4bde99", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/3076360/apply", "externalId" : "db722074-e1c3-4242-95de-880e5ff7d011", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Redmond", "state" : "Washington", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "47.6694141,-122.1238767" } ], "locationText" : "Redmond, Washington, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "technicalSkills" : "Python, C/C++, Verilog, VHDL, RFIC design, Digital design, Communication systems", "professionalSkills" : [ "Technical reviews", "Test procedures" ], "hardSkillsList" : [ "RF fundamentals", "Digital communication systems", "Circuit simulation" ], "hardSkills" : [ { "name" : "RF fundamentals", "level" : "intermediate" }, { "name" : "Digital communication systems", "level" : "intermediate" }, { "name" : "Circuit simulation", "level" : "intermediate" } ], "majorSkills" : "Satellite communication systems, Integrated circuits, RF components", "majorSkillsList" : [ "Satellite communication systems", "Integrated circuits", "RF components" ], "coreResponsibilities" : "Support development of satellite communication systems, Support testing of satellite communication systems, Support development of integrated circuits, Support testing of integrated circuits, Create test procedures for RF components, Execute test procedures for RF components, Create test procedures for RF systems, Execute test procedures for RF systems, Maintain test data, Analyze test data, Contribute to verification of RF circuits, Contribute to verification of mixed-signal circuits, Contribute to validation of RF circuits, Contribute to validation of mixed-signal circuits, Participate in cross-functional team meetings, Participate in technical reviews, Document processes, Document results, Support automation for testing, Support automation for verification", "teamCollaboration" : "Cross-functional team meetings; Technical reviews", "domainKnowledge" : "Satellite communication technology; RFIC design; Digital design; Communication systems", "domainList" : [ "satellite-communication-technology", "rfic-design", "digital-design", "communication-systems" ], "domainSpecificKnowledge" : [ "Satellite communication technology", "RFIC design", "Digital design", "Communication systems" ], "toolProficiency" : [ "Circuit simulation tools" ], "documentationSkills" : "Document processes; Document results", "problemSolvingSkills" : "Root cause analysis", "specialRequirements" : "U. S. citizen or national, U. S. permanent resident, Lawfully admitted refugee, Granted asylum", "qualificationsBasic" : "Relocate to internship location, Work 40 hours/week, Commit to 12 week internship, Pursuing Bachelor's or Master's, Graduation date Dec 2026 - May 2028, Understanding of RF fundamentals, Understanding of digital communication systems, Programming skills in Python, Programming skills in C/C++, Familiarity with Verilog, Familiarity with VHDL, Familiarity with circuit simulation concepts", "qualificationsPreferred" : "Coursework in RFIC design, Coursework in digital design, Coursework in communication systems, Experience with Verilog, Experience with VHDL, Experience with circuit simulation tools, Familiarity with verification methodologies", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a Project Kuiper intern, you will work alongside experienced engineers in our RFIC, RF/Communications Systems, or Digital Design Verification teams. This internship offers hands-on experience in cutting-edge satellite communications technology development, from integrated circuit design to system-level implementation and verification. Export Control Requirement Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities - Support engineering teams in development and testing of satellite communication systems and integrated circuits - Assist in creating and executing test procedures for RF components and systems - Help maintain and analyze test data from IC-level to system-level testing - Contribute to verification and validation of RF/mixed-signal circuits and systems - Participate in cross-functional team meetings and technical reviews - Document processes and results - Support automation efforts for testing and verification workflows Basic Qualifications: - Can relocate to where the internship is based - Work 40 hours/week minimum and commit to 12 week internship maximum - Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical field with a graduation date between December 2026 - May 2028. - Understanding of RF fundamentals or digital communication systems - Programming skills in at least one language (e.g., Python, C/C++) - Familiarity with hardware description languages (e.g., Verilog, VHDL) or circuit simulation concepts Preferred Qualifications: - Coursework in RFIC design, digital design, or communication systems - Experience with hardware description languages (e.g., Verilog, VHDL) or circuit simulation tools - Familiarity with verification methodologies (e.g., UVM) or RF test equipment - Knowledge of Linux operating systems and scripting languages - Understanding of satellite communications systems or digital signal processing - Prior project experience in telecommunications, aerospace, or semiconductor industry Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $104,000/year in our lowest geographic market up to $212,200/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits . This position will remain posted until filled. Applicants should apply via our internal or external career site.", "summaryDescription" : "ASIC Engineering Internship (Summer 2026) at Amazon Kuiper Manufacturing Enterprises LLC. Skills: Satellite communication systems, Integrated circuits, RF components. Support development of satellite communication systems. Support testing of satellite communication systems", "postedDate" : "2026-06-13T19:56:56.785", "createdAt" : "2026-06-13T19:56:56.785", "lastUpdated" : "2026-06-15T07:09:39.803", "ingestTimestamp" : "2026-06-13T19:56:56.785", "mongoId" : "68c2e42af8b1b0376634c688", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/3076360/apply", "salaryAnnualMin" : 104000, "salaryAnnualMax" : 212200, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "RF fundamentals", "Digital communication systems", "Circuit simulation", "Satellite communication systems", "Integrated circuits", "RF components", "Technical reviews", "Test procedures", "Satellite communication technology", "RFIC design", "Digital design", "Communication systems", "Circuit simulation tools" ], "skillCount" : 13, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Entry", "dataQualityScore" : 0.8888889, "_score" : 539.48346, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a305128f292fd229cefb509", "title" : "Manager, Operations Engineering (Physical Infrastructure)", "company" : "xAI", "salary" : { "min" : 175500.0, "max" : 258500.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Operations Engineering Manager in Memphis, TN, adjusted for manager seniority and technology industry." }, "location" : "Memphis, Tennessee, United States", "locations" : [ "Memphis", "Tennessee", "United States" ], "timestamp" : "2026-06-16T08:46:31.678", "fingerprint" : "255660a85fc22ed34f3fa3cef69e631fdf3ff3c063b245e21bc6c673fa1339d1", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/xai/jobs/5164998007", "externalId" : "5164998007", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Memphis", "state" : "Tennessee", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "35.1460260,-90.0517786" } ], "locationText" : "Memphis, Tennessee, United States", "employmentType" : "FULL_TIME", "experienceLevel" : "Manager", "rawDescription" : "ABOUT xAI xAI’s mission is to create AI systems that can accurately understand the universe and aid humanity in its pursuit of knowledge. Our team is small, highly motivated, and focused on engineering excellence. This organization is for individuals who appreciate challenging themselves and thrive on curiosity. We operate with a flat organizational structure. All employees are expected to be hands-on and to contribute directly to the company’s mission. Leadership is given to those who show initiative and consistently deliver excellence. Work ethic and strong prioritization skills are important. All employees are expected to have strong communication skills. They should be able to concisely and accurately share knowledge with their teammates. ABOUT THE ROLE: As a Manager, Operations Engineering (Physical Infrastructure) on the xAI infrastructure team, you will lead the design, build, activation, and continuous optimization of the world’s most technically advanced data centers and AI compute facilities. You will own end-to-end operational excellence for physical infrastructure, driving process improvements, metrics-driven decision making, and cross-functional alignment to ensure maximum uptime, efficiency, and scalability. This role will report directly to the department head (or equivalent senior leader) and serve as a key leader org-wide, managing a team of operations engineers and analysts while acting as a strategic partner to site directors, construction, maintenance, and facilities teams. If you thrive on strategic planning, leading continuous improvement initiatives, building high-performing teams, and operating in a dynamic, fast-paced environment, this role is for you! RESPONSIBILITIES: Lead and develop a team of Operations Engineers and analysts focused on physical infrastructure optimization for xAI’s hyperscale data centers Define and own department-level visual standards, JIRA workflows, PowerBI dashboards, and operational processes; drive adoption and continuous refinement across the organization Champion department-wide continuous improvement projects, including new process rollouts, standardization, and lean/six sigma initiatives Partner with all levels of the business to map current workflows, identify systemic gaps, and implement scalable solutions Establish and evolve department-level metrics & dashboards that quantify operational health, drive data-informed decisions, and demonstrate impact to leadership Conduct in-depth analyses using SQL, Python, Excel, and other tools to uncover trends, mitigate risks, and recommend optimizations Develop and implement automation, tools, and reports that reduce business risk, improve efficiencies, and enhance communication with facility and site directors Lead department-wide operations audits to streamline repair, maintenance, and construction engineering workflows Own maintenance program enhancements, focusing resources on critical hardware health while descoping low-value work Evaluate, select, and implement construction management, maintenance, and facilities tools (software/hardware) to minimize waste and maximize technician/engineer productivity Perform site services analysis for contracts (custodial, utilities, waste, power, cooling, fiber, etc.), negotiate improvements, and build roadmaps for cost optimization and reliability Standardize material libraries and procurement processes to reduce lead times and support rapid scaling across sites Drive alignment and best-practice sharing with maintenance and construction teams at other xAI sites nationwide to eliminate duplication and accelerate execution Build and mentor high-performing cross-functional teams while fostering a culture of operational excellence and accountability BASIC QUALIFICATIONS: Bachelor’s degree in an engineering discipline, operations research, industrial engineering, management science, or related field 5+ years of experience in operations, process improvement, or facilities management (with progressive leadership experience managing teams or projects) Demonstrated experience with Excel, SQL, Python, Power BI, JIRA, or similar tools for data analysis, visualization, and workflow management Proven track record leading cross-functional initiatives in fast-paced environments PREFERRED SKILLS AND EXPERIENCE: Previous experience in data centers, hyperscale infrastructure, manufacturing, supply chain, or production environments Strong proficiency in statistics, data analysis, data visualization, cost-benefit analysis, and operational excellence frameworks (Lean, Six Sigma, etc.) Hands-on experience with CAD, ArcGIS, Archibus, BMS/SCADA, ERP systems, inventory/capacity planning, or critical infrastructure (MEP systems) Experience contributing to or leading multi-disciplinary teams in construction, commissioning, or facilities operations Excellent written and verbal communication skills with the ability to influence stakeholders at all levels Ability to thrive in a dynamic environment with extended hours/weekends as needed and occasional short-notice travel ADDITIONAL REQUIREMENTS: Must be able to work extended hours and/or weekends as needed, including occasional short-notice domestic travel xAI is an equal opportunity employer. For details on data processing, view our Recruitment Privacy Notice.", "summaryDescription" : "Manager, Operations Engineering (Physical Infrastructure) at xAI", "postedDate" : "2026-06-15T23:15:42.658", "createdAt" : "2026-06-15T23:15:42.658", "lastUpdated" : "2026-06-16T08:46:31.678", "ingestTimestamp" : "2026-06-15T23:15:42.658", "mongoId" : "6a305128f292fd229cefb509", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 175500, "salaryAnnualMax" : 258500, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Manager", "dataQualityScore" : 0.8888889, "_score" : 537.70654, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a210e2a74d8ee00a0af602e", "title" : "ASIC Design Verification Engineer, TPU Cloud", "industry" : "Technology", "salary" : { "min" : 155000.0, "max" : 215000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level ASIC Design Verification Engineer in Sunnyvale, United States, adjusted for the technology industry." }, "location" : "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]", "locations" : [ "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]" ], "timestamp" : "2026-06-16T11:47:07.727", "fingerprint" : "336bcb5badbe0c287d1b9a57c2abca42641a678d0ee033dd6cc67ad9ba4a78c5", "source" : "google", "language" : "en", "externalId" : "95737844638589638", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "technicalSkills" : "ASIC, TPU", "majorSkills" : "ASIC Design, Verification", "majorSkillsList" : [ "ASIC Design", "Verification" ], "domainKnowledge" : "TPU Cloud", "domainList" : [ "tpu-cloud" ], "domainSpecificKnowledge" : [ "TPU Cloud" ], "qualificationsBasic" : "ASIC design verification experience", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "summaryDescription" : "ASIC Design Verification Engineer, TPU Cloud. Skills: ASIC Design, Verification", "postedDate" : "2026-06-16T01:48:01.337", "createdAt" : "2026-06-16T01:48:01.337", "lastUpdated" : "2026-06-16T11:47:07.727", "ingestTimestamp" : "2026-06-16T01:48:01.337", "mongoId" : "6a210e2a74d8ee00a0af602e", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 155000, "salaryAnnualMax" : 215000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "ASIC Design", "Verification", "TPU Cloud" ], "skillCount" : 3, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.5555556, "_score" : 537.012, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a2d85f174d8ee00a0c221be", "title" : "Senior Software Engineer (Sustaining Automation)", "company" : "Chainguard", "industry" : "Cybersecurity", "salary" : { "min" : 145000.0, "max" : 200000.0, "currency" : "CAD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market data for a Senior Software Engineer in Canada, adjusted for seniority and remote work in the technology industry." }, "location" : "Remote - Canada", "locations" : [ "Remote - Canada", "Remote - US" ], "timestamp" : "2026-06-15T23:08:47.510", "fingerprint" : "efd268bf23ed20d85851bcb320ca776e4ca8ee745c22d988f2ed87003ba37e06", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/chainguard/jobs/4688557006", "externalId" : "4688557006", "industryFunction" : { }, "structuredLocations" : [ { "country" : "Canada", "continent" : "na", "workMode" : "remote" } ], "locationText" : "Canada", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "remoteFriendly" : true, "workSiteFlexibility" : "Remote", "rawDescription" : "Chainguard is the trusted source for open source. By delivering hardened, secure, and production-ready builds of all the open source software engineers and AI agents rely on, Chainguard helps organizations build faster, stay compliant, and eliminate risk. Our customers include Fortune 500 enterprises and global industry leaders, including Anduril, Canva, Fortinet, Hewlett Packard Enterprise, OpenAI, Snap Inc., and Snowflake. Chainguard is venture-backed by leading investors, including Amplify, IVP, Kleiner Perkins, Lightspeed Venture Partners, Mantis VC, Redpoint Ventures, Sequoia Capital, and Spark Capital. Who we are At Chainguard, we are on a mission to secure the software supply chain by default. Our team is founded by the industry's leading experts on open source software, security and cloud native development. Chainguard's product portfolio includes Chainguard Images and Chainguard Services. Customers range from Fortune 500 companies in banking, fintech, government and infrastructure to startups and SMBs. Join us as we help organizations secure their software supply chain from source to production. The role, in a nutshell Chainguard delivers the industry's most secure container images: minimal, zero-CVE, rebuilt daily from source. We're building a new team focused on automation and tooling to accelerate how we deliver images at scale. As a Senior Engineer, you'll be the technical leader for this greenfield effort. You'll design systems, build AI-powered tooling, and shape the future of our fulfillment platform. You'll work closely with a small team of engineers, guiding technical decisions and raising the bar for engineering quality. This is a high-impact role at the intersection of developer tooling, AI/agents, and supply chain security. What you'll do Architect the automation platform: Design the end-to-end system that orchestrates package creation, test generation, and image building. Own the technical vision and make decisions that will scale. Build AI-powered tooling: Develop LLM-integrated, agentic pipelines for manifest generation, test scaffolding, and validation. Design prompt architectures, evaluation loops, and quality gates. Write production Go: This is a hands on role! You'll develop CLI tools, services, and integrations alongside your team. Build quality tooling: Develop tooling and automation that improves customer reliability, including test generators, validation frameworks, and quality gates. Shape the roadmap: Collaborate with engineering leadership to identify the highest-impact problems and ensure they get solved. Participate in long-term planning for the organization. What we're looking for 5-7 years of software engineering experience, with a track record of designing and building complex systems Strong Go expertise Experience with AI/LLM integration: building systems that use language models for code generation, automation, or developer tooling. Familiarity with prompt engineering, evaluation, and guardrails Systems architecture skills: ability to design loosely-coupled, scalable systems and make pragmatic trade-offs Experience building developer tools, CLIs, or automation platforms Deep Linux and build systems knowledge: experience with package managers (apk, apt, rpm), build tools (Make, Bazel, language-specific toolchains), and containerization Container ecosystem expertise: Docker, OCI, container registries, Kubernetes Strong communication skills: ability to write clear technical documents, work autonomously, and collaborate across teams Nice to haves Contributions to open-source projects Familiarity with software supply chain security (SBOM, provenance, signing) Experience with melange, apko, or Wolfi Understanding of compliance frameworks (FedRAMP, FIPS, STIG) Base Salary Range $157,000—$184,000 USD About Us We live and breathe our company values: We are customer obsessed — We focus on delivering solutions to our customers that create value and make their lives better. We have a bias for intentional action — We prioritize, plan, try things, and fail fast. We don't take ourselves too seriously (but we do serious work) — We are solving an important problem which takes focus, but we also like to enjoy the journey. We trust each other and assume good intentions — We're transparent with decisions to empower team members to make well informed decisions. A few of the benefits we offer: Flexible & Remote-First Culture: Work remotely with team meetup opportunities, bi-annual destination summits, and a monthly stipend for coworking spaces, phone and internet costs. Our Approach to Equity: Receive stock options upon hire and promotion. Plus, you can participate in secondary offerings and have 10 years to exercise your options (yes, you read that correctly: 10 years!). 100% Covered Health Insurance: We cover 100% of your health, vision and dental insurance premiums for you and your dependents. Nothing comes out of your paycheck. ∞ Flexible Time Off: Take the time you need – to do our best work, we need to recharge and reset. 18 Weeks Paid Parental Leave: We offer 18 weeks for birthing parents and 12 weeks for non-birthing parents, with the option to use it all at once or throughout your child's first year. If your experience is close but doesn't fulfill all requirements, please apply. We're building the best team in technology and are focused on hiring \"Chainguardians\" with unique backgrounds, perspectives, and experiences. Chainguard is an equal opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. By submitting your application, you acknowledge that Chainguard will process your personal data in accordance with Chainguard's Global Candidate Privacy Notice. ©2026 Chainguard. All Rights Reserved.", "summaryDescription" : "Senior Software Engineer (Sustaining Automation) at Chainguard", "postedDate" : "2026-06-14T21:53:45.998", "createdAt" : "2026-06-14T21:53:45.998", "lastUpdated" : "2026-06-15T23:08:47.510", "ingestTimestamp" : "2026-06-14T21:53:45.998", "mongoId" : "6a2d85f174d8ee00a0c221be", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "100k-150k", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "_score" : 530.9628, "daysOld" : 1, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a307f08f292fd229c05496b", "title" : "ASIC Formal Verification Engineer, Google Cloud", "company" : "Google", "industry" : "Technology", "salary" : { "min" : 175000.0, "max" : 260000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Mid-level ASIC Formal Verification Engineer in Sunnyvale, United States, adjusted for Google's size and the technology industry." }, "location" : "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]", "locations" : [ "[Sunnyvale, CA, USA, [111 W Java Dr, Sunnyvale, CA 94089, USA], Sunnyvale, 94089, CA, US]" ], "timestamp" : "2026-06-16T12:19:05.645", "fingerprint" : "d405d26cfe117fc9081466b466a2241c70cb8bfb57ea58582bd4774031d590e1", "source" : "google", "language" : "en", "externalId" : "133721869785146054", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "remoteFriendly" : false, "summaryDescription" : "ASIC Formal Verification Engineer, Google Cloud at Google", "postedDate" : "2026-06-16T01:51:14.626", "createdAt" : "2026-06-16T01:51:14.626", "lastUpdated" : "2026-06-16T12:19:05.645", "ingestTimestamp" : "2026-06-16T01:51:14.626", "mongoId" : "6a307f08f292fd229c05496b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 175000, "salaryAnnualMax" : 260000, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.5555556, "_score" : 527.3885, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "6a2c6afa74d8ee00a090f9dd", "title" : "Packaging and Sustainability Manager", "company" : "Revance", "salary" : { "min" : 115000.0, "max" : 165000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Packaging and Sustainability Manager in Johnson City, United States, adjusted for mid-seniority and full-time employment." }, "location" : "Johnson City, TN, Remote", "locations" : [ "Johnson City", "TN", "Remote" ], "timestamp" : "2026-06-15T22:28:12.689", "fingerprint" : "9bb6107fe32d16d71810dbe0f13f72fd97dd769e5fd8669ce5f878be0b4a0798", "source" : "greenhouse", "language" : "en", "applyUrl" : "http://www.revance.com/careers/job-listings/?gh_jid=8585796002", "externalId" : "8585796002", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Johnson City", "state" : "Tennessee", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "36.3167671,-82.3529030" }, { "city" : "Nashville", "state" : "Tennessee", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "36.1622767,-86.7742984" }, { "workMode" : "remote" } ], "locationText" : "Johnson City, Tennessee, United States; Nashville, Tennessee, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 3, "experienceLevel" : "Manager", "remoteFriendly" : true, "workSiteFlexibility" : "Remote", "rawDescription" : "Summary: We are seeking a Packaging & Sustainability Manager to support the development of packaging across our portfolio. This role will be responsible for leading day-to-day packaging engineering activities while also owning packaging sustainability and ESG initiative tracking. The ideal candidate is a hands-on Packaging Engineer with 3+ years of experience in a CPG environment, who is comfortable managing multiple priorities, maintaining detailed technical and sustainability data, partnering cross-functionally, and balancing technical, cost, regulatory, and sustainability considerations in a fast-paced organization. Reports to: Sr. Packaging & Sustainability Manager Location: Remote or Johnson City TN Key Responsibilities: • Lead packaging development and execution for assigned projects from initiation through launch, ensuring alignment with product, brand, regulatory, and sustainability objectives. • Develop and maintain packaging specifications, drawings, BOMs, and technical documentation for primary, secondary, and tertiary packaging, including e-comm, retail-ready and club channel packaging formats. • Support commercialization activities including qualification planning, line trials, scale-up, and first production runs at internal and external manufacturing sites. • Develop and execute packaging test plans, including compatibility, functionality, and shelf-life testing, in partnership with external labs. • Proactively identify, troubleshoot, and resolve packaging-related issues during development and commercial production. • Partner with Supply Chain and suppliers to evaluate packaging components, materials, and cost-optimization opportunities. • Own and maintain centralized trackers for all packaging material specifications, including material type, weights, recyclability status, PCR content, and supplier attributes. • Ensure packaging data accuracy and readiness to support sustainability regulations, labeling requirements, and recyclability claims. • Support packaging sustainability initiatives, including recyclability improvements, PCR material adoption, material reduction, and supplier engagement. • Support setting packaging sustainability targets and tracking progress against goals • Assist with sustainability and ESG reporting activities (e.g., CDP Climate and Water disclosures, internal scorecards, supplier questionnaires). • Collaborate cross-functionally with Project Management, R&D, Regulatory, Quality, Marketing, Creative, Supply Chain, Operations, and external partners. • Ensure packaging solutions meet regulatory, quality, and safety requirements for applicable categories (cosmetics, OTC, etc.). Required Qualifications Bachelor’s degree in Packaging Engineering or a related technical field. • 3–5+ years of packaging engineering experience in a CPG, consumer health, beauty, OTC, or regulated products environment. • Hands-on experience with primary and secondary packaging development and commercialization. Experience supporting retail-ready, shelf-ready, or club channel packaging designs a plus. • Experience working with contract manufacturers, packaging suppliers, and external testing labs. • Experience owning packaging material specifications, trackers, or sustainability datasets preferred. • Experience supporting packaging sustainability initiatives, GHG calculations, or ESG/CDP reporting preferred. • Strong technical problem-solving and organizational skills, with the ability to manage multiple projects in parallel. • Excellent communication skills and ability to work effectively across technical and commercial teams. • Detail-oriented, proactive, and comfortable operating in a fast-paced, cross-functional environment. Ability to travel up to 30% to Jonson City TN, Nashville TN, or to our CMOs. Company Summary: Revance is a global company developing, producing, and distributing industry-leading, differentiated products across aesthetics, skincare, and therapeutics. Revance drives innovation beyond convention to offer treatment options for individuals across generations. The Company’s vision is to redefine excellence in aesthetics, skincare, and therapeutics through science-powered innovation, with an unwavering commitment to its providers, patients, and consumers. Revance’s award-winning products are the result of robust research and development, a cornerstone for the Company, driven by renowned scientists. For more information about Revance, please visit us at www.revance.com. What Revance invests in you: Competitive Compensation including base salary and annual performance bonus. Flexible PTO, holidays, and parental leave. Generous healthcare benefits, HSA match, 401k match, employer paid life and disability insurance, pet insurance, wellness discounts and much more! This section of the job description is required by the American with Disability Act (ADA). The ADA requires that job descriptions reflect the physical and mental demands required to effectively perform the essential duties of the job. The ADA prohibits employers from discriminating against a “qualified individual with a disability” in all aspects of the employment relationship. A “qualified individual with a disability” is “an individual who meets the education, experience, skill, and other job-related requirements of a position held or desired, and who, with reasonable accommodation, can perform the essential functions of a specified job.” Revance is an Equal Opportunity employer. All qualified applicants will receive consideration for employment based on merit, without regard to race, color, religion, sex, national origin, disability, protected Veteran Status, or any other characteristic protected by applicable federal, state, or local law.", "summaryDescription" : "Packaging and Sustainability Manager at Revance", "postedDate" : "2026-06-14T19:15:43.041", "createdAt" : "2026-06-14T19:15:43.041", "lastUpdated" : "2026-06-15T22:28:12.689", "ingestTimestamp" : "2026-06-14T19:15:43.041", "mongoId" : "6a2c6afa74d8ee00a090f9dd", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 115000, "salaryAnnualMax" : 165000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Mid", "dataQualityScore" : 0.8888889, "_score" : 526.23926, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Healthcare", "llmIndustryConfidence" : 0.95 }, { "id" : "694ae6e370f0b99d589b373b", "title" : "Director, Sustaining Capital Projects", "company" : "IAMGOLD", "industry" : "Manufacturing", "salary" : { "min" : 175000.0, "max" : 250000.0, "currency" : "CAD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Director of Sustaining Capital Projects in Toronto, Canada, adjusted for industry and seniority." }, "location" : "19 - Toronto Head Office", "locations" : [ "19 - Toronto Head Office", "
19 - Toronto Head Office (19 - Toronto Head Office)
150 King Street West
Suite 2200
Toronto, M5H 1J9

" ], "certifications" : [ "Project Management certification" ], "timestamp" : "2026-06-16T03:03:52.861", "fingerprint" : "7cda482e3b74a97ecf0af729ecdcdc49b6c50fc8b115bfeaa604ad638551a01e", "source" : "taleo", "language" : "en", "applyUrl" : "https://iamgold.taleo.net/careersection/ex/jobdetail.ftl?job=56845", "externalId" : "56845", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Toronto", "state" : "Ontario", "country" : "Canada", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "43.6534817,-79.3839347" } ], "locationText" : "Toronto, Ontario, Canada", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 10, "experienceMaxYears" : 15, "experienceLevel" : "Director", "technicalSkills" : "MS Office", "professionalSkills" : [ "Portfolio management" ], "hardSkillsList" : [ "Project management practices", "Budget planning", "Capital approval", "Execution monitoring", "Post-project evaluation", "Business case validation", "Project outcome validation" ], "softSkillsList" : [ "Leadership", "Problem-solving" ], "hardSkills" : [ { "name" : "Project management practices", "level" : "intermediate" }, { "name" : "Budget planning", "level" : "intermediate" }, { "name" : "Capital approval", "level" : "intermediate" }, { "name" : "Execution monitoring", "level" : "intermediate" }, { "name" : "Post-project evaluation", "level" : "intermediate" }, { "name" : "Business case validation", "level" : "intermediate" }, { "name" : "Project outcome validation", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" }, { "name" : "Problem-solving" } ], "majorSkills" : "Project management, Portfolio management, Capital projects", "majorSkillsList" : [ "Project management", "Portfolio management", "Capital projects" ], "coreResponsibilities" : "Lead and support management of sustaining capital projects, Guide site PMOs in implementing project management practices, Support full lifecycle of sustaining capital projects, Coordinate monthly Capital Request Committee meetings, Validate project outcomes against initial expectations, Present findings to senior stakeholders, Equip site teams with tools and guidance, Directly manage consultants, Collaborate with finance departments, Collaborate with technical departments, Perform regular site visits", "teamCollaboration" : "Site PMOs; Finance departments; Technical departments", "projectManagementSkills" : [ "Project management practices", "Portfolio management" ], "domainKnowledge" : "Mining operations; Industrial settings", "domainList" : [ "mining-operations", "industrial-settings" ], "domainSpecificKnowledge" : [ "Mining operations", "Industrial settings" ], "toolProficiency" : [ "Oracle", "Ecosys", "Primavera" ], "communicationSkills" : "Presenting findings", "problemSolvingSkills" : "Problem-solving", "specialRequirements" : "Regular site visits", "outcomesObjectives" : "Elevate performance and consistency", "qualificationsBasic" : "Post-secondary education in engineering, 10 to 15 years of experience in engineering, construction, or project management, Grasp of portfolio management", "qualificationsPreferred" : "Project Management certification, Bilingualism in English and French", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Empowering People – Extraordinary Performance Start Your Next Opportunity with IAMGOLD IAMGOLD is seeking a strategic and experienced Director, Sustaining Capital Projects to lead and support the management of our sustaining capital projects portfolio across our global mining operations (Westwood, Essakane, Côté Gold). This role is responsible for guiding site PMOs in implementing rigorous project management practices and processes, supporting the full lifecycle of sustaining capital projects—from budget planning and capital approval to execution monitoring and post-project evaluation. Working closely with site PMOs, the Director will ensure each project is grounded in a robust business case and supported by strong baselines. The Director will coordinate monthly Capital Request Committee (CRC) meetings and play a key role in validating project outcomes against initial expectations, presenting findings to senior stakeholders. This role will also champion project management excellence by equipping site teams with the tools, guidance, and best practices needed to elevate performance and consistency. The Director will directly manage consultants, collaborate with finance and technical departments, and perform regular site visits to maintain alignment and accountability. What You Need to Succeed We’re looking for a leader with post-secondary education in engineering and 10 to 15 years of experience in engineering, construction, or project management, ideally within mining or industrial settings, and a strong grasp of portfolio management. Project Management certification and bilingualism in English and French are assets. Success in this role requires exceptional communication, leadership, and problem-solving skills, along with proficiency in MS Office and familiarity with Oracle, Ecosys, and Primavera. We offer an attractive total rewards package that includes a competitive salary and bonus, extended health, dental and insurance benefit coverage, a health spending account, fitness & wellness subsidy, employee & family assistance program, registered pension plan with company match, employee share purchase plan with company match, TFSA & RRSP, electric vehicle subsidy, summer hours and holiday office closure. If you’re driven by impact, thrive in complex environments, and are passionate about responsible resource development, we invite you to bring your expertise to IAMGOLD and help shape the future of our capital projects. We offer an attractive total rewards package that includes a competitive salary and bonus, extended health, dental and insurance benefit coverage, a health spending account, fitness & wellness subsidy, employee & family assistance program, registered pension plan with company match, employee share purchase plan with company match, TFSA & RRSP, electric vehicle subsidy, summer hours and holiday office closure. If you’re driven by impact, thrive in complex environments, and are passionate about responsible resource development, we invite you to bring your expertise to IAMGOLD and help shape the future of our capital projects. We understand no candidate meets every qualification listed. If your experience differs but you believe you can add value to the role, we want to hear from you! We are committed to inclusivity and welcome applications from individuals of all abilities. If you need accommodation during the application process, please contact us, and we'll provide the necessary support. Canada", "summaryDescription" : "Director, Sustaining Capital Projects at IAMGOLD. Skills: Project management, Portfolio management, Capital projects. Lead and support management of sustaining capital projects. Guide site PMOs in implementing project management practices", "createdAt" : "2026-06-14T18:48:31.490", "lastUpdated" : "2026-06-16T03:03:52.861", "ingestTimestamp" : "2026-06-14T18:48:31.490", "mongoId" : "694ae6e370f0b99d589b373b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "150k-200k", "hasSalary" : false, "allSkills" : [ "Project management practices", "Budget planning", "Capital approval", "Execution monitoring", "Post-project evaluation", "Business case validation", "Project outcome validation", "Leadership", "Problem-solving", "Project management", "Portfolio management", "Capital projects", "Mining operations", "Industrial settings", "Project Management certification", "Oracle", "Ecosys", "Primavera" ], "skillCount" : 18, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Director", "dataQualityScore" : 0.8888889, "_score" : 519.75336, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Manufacturing", "llmIndustryConfidence" : 0.95 }, { "id" : "6a307f39f292fd229c0565f1", "title" : "Senior Silicon Design Verification Engineer, Google Cloud", "company" : "Google", "industry" : "Technology", "salary" : { "min" : 4500000.0, "max" : 7500000.0, "currency" : "INR", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for Senior Silicon Design Verification Engineer in Bengaluru, India, adjusted for Google's size and industry, reflecting 2024-2025 data." }, "location" : "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]", "locations" : [ "[Bengaluru, Karnataka, India, [3, Old Madras Rd, Sadanandanagar, Bennigana Halli, Bengaluru, Karnataka 560038, India], Bengaluru, 560038, KA, IN]" ], "timestamp" : "2026-06-16T14:40:36.494", "fingerprint" : "b3601dd52aea2086e71422ef7681f40d9bb0ee03ca550111c1f3d51f0fa25f0c", "source" : "google", "language" : "en", "externalId" : "111501109154980550", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Bengaluru", "state" : "Karnataka", "country" : "India", "continent" : "as", "source" : "llm", "workMode" : "onsite", "geo" : "12.9767936,77.5900820" } ], "locationText" : "Bengaluru, Karnataka, India", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "remoteFriendly" : false, "summaryDescription" : "Senior Silicon Design Verification Engineer, Google Cloud at Google", "postedDate" : "2026-06-16T01:48:30.394", "createdAt" : "2026-06-16T01:48:30.394", "lastUpdated" : "2026-06-16T14:40:36.494", "ingestTimestamp" : "2026-06-16T01:48:30.394", "mongoId" : "6a307f39f292fd229c0565f1", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryBand" : "200k+", "hasSalary" : false, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Senior", "dataQualityScore" : 0.6666667, "_score" : 518.4389, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "69ce5e1f9bc74574cb6752dd", "title" : "Structures and Mechanisms Engineer, ISS Sustaining", "company" : "Barrios", "location" : "United States-Texas-Houston", "locations" : [ "United States-Texas-Houston" ], "timestamp" : "2026-06-15T07:05:56.402", "fingerprint" : "c9bac9980820803a0de64ed836816673480ca5e34f52273d7a006bf4ae7d1d26", "source" : "taleo", "applyUrl" : "https://jacobs.taleo.net/careersection/ex/jobdetail.ftl?job=323855", "externalId" : "323855", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Houston", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite" } ], "locationText" : "Houston, Texas, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor", "experienceMinYears" : 2, "experienceMaxYears" : 5, "experienceLevel" : "Junior", "technicalSkills" : "Structures, Mechanisms, Loads and Dynamics, Pressure Systems", "professionalSkills" : [ "Structures and Mechanisms, ISS" ], "hardSkillsList" : [ "Bachelor of Science in Mechanical or Aerospace Engineering", "NASA Standards for Structures and Mechanisms", "NASA flight hardware experience" ], "softSkillsList" : [ "teamwork, creative ideas, outgoing, self-starter" ], "hardSkills" : [ { "name" : "Bachelor of Science in Mechanical or Aerospace Engineering", "level" : "intermediate" }, { "name" : "NASA Standards for Structures and Mechanisms", "level" : "intermediate" }, { "name" : "NASA flight hardware experience", "level" : "intermediate" } ], "softSkills" : [ { "name" : "teamwork, creative ideas, outgoing, self-starter" } ], "majorSkills" : "Structures, Mechanisms, ISS sustaining, hardware analysis, flight hardware experience", "majorSkillsList" : [ "Structures, Mechanisms, ISS sustaining, hardware analysis, flight hardware experience" ], "coreResponsibilities" : "Provide Subsystem Management support for ISS sustaining. Assist in review and development of hardware, analysis, operation, hazard reviews, anomaly resolution, requirements verification, re-flight assessments, and flight acceptance testing with respect to structures and mechanisms. Coordinate to close technical and programmatic issues. Review and approve vehicle verification / certification tests, analysis, and their associated documentation.", "teamCollaboration" : "As a multidiscipline team, members are encouraged to have an overall background and working knowledge of all the areas within Structures and Mechanisms. Expertise is not required, but willingness to learn and coordinate across other disciplines is highly desired.", "projectManagementSkills" : [ "Subsystem Management support" ], "toolProficiency" : [ "PC, telephone, printer" ], "communicationSkills" : "formulate presentations; present to boards", "documentationSkills" : "documentation", "continuousLearning" : "Willingness to learn and coordinate across other disciplines is highly desired.", "innovationCreativity" : "We need you to bring creative ideas and diverse backgrounds to help us envision, shape, and deliver systems that will enable the exploration of space while benefiting people here on Earth.", "problemSolvingSkills" : "anomaly resolution; system design", "specialRequirements" : "Proof of U. S. Citizenship or US Permanent Residency may be a requirement for this position. Must be able to complete a U. S. government background investigation.", "outcomesObjectives" : "Achieve great things that inspire people all over the globe. Envision, shape, and deliver systems that will enable the exploration of space while benefiting people here on Earth.", "qualificationsBasic" : "Bachelor’s degree in Engineering and a minimum of 2-5 years of experience in the field or in a related area. Bachelor of Science in Mechanical or Aerospace Engineering. Familiarity with NASA Standards for Structures and Mechanisms. Previous NASA flight hardware experience.", "qualificationsPreferred" : "Self-Starter with a willingness to learn. Some background in Structures, Mechanisms, and Loads and Dynamics.", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Are you passionate about human space exploration, understanding the origins of the universe, and working with a passionate and diverse team to make a difference? If you are, we need you! We need your talent, teamwork, and energy to help us achieve great things that inspire people all over the globe. We need you to bring creative ideas and diverse backgrounds to help us envision, shape, and deliver systems that will enable the exploration of space while benefiting people here on Earth. We are excited about what we do, and we need you on our team as we take on exciting challenges for NASA’s pursuits in deep space exploration. As NASA’s largest engineering solutions provider working together with NASA at centers across the United States. We have an exciting opportunity for a Structures and Mechanisms Engineer, ISS Sustaining to join the team with Barrios, a teammate company. The ISS Structures and Mechanisms team spans several branches within the Structural Engineering Division at NASA/JSC. Members support Structures and Fracture, Mechanisms, Loads and Dynamic, and Pressure Systems The Structures and Mechanisms Engineer, ISS Sustaining will: Provide Subsystem Management support for needed for ISS sustaining. Assist in review and development of hardware, analysis, operation, hazard reviews, anomaly resolution, requirements verification, re-flight assessments, and flight acceptance testing with respect to structures and mechanisms to name a few. Coordinate to close technical and programmatic issues. Review and approve vehicle verification / certification tests, analysis, and their associated documentation. As a multidiscipline team, members are encouraged to have an overall background and working knowledge of all the areas within Structures and Mechanisms. Expertise is not required, but willingness to learn and coordinate across other disciplines is highly desired. ISS continues to support cargo and crew vehicles visiting to the ISS . Ideally the candidate will be outgoing and a self-starter. As time allows other duties will include USDV development and other ISS visiting vehicles. Candidate should be able to formulate presentations and present to boards as appropriate. Requisition Qualifications: This position has been posted at multiple levels. Depending on the candidate's experience, requirements, and business needs, we reserve the right to consider candidates at any level for which this position has been advertised. Typically requires a bachelor’s degree in Engineering and a minimum of 2-5 years of experience in the field or in a related area. Bachelor of Science in Mechanical or Aerospace Engineering Familiarity with NASA Standards for Structures and Mechanisms Previous NASA flight hardware experience Requisition Preferences: Self-Starter with a willingness to learn Some background in Structures, Mechanisms, and Loads and Dynamics. Why Join Our Team? In addition to exciting career opportunities, we also have: Excellent personal and professional career growth 9/80 work schedule (every other Friday off), when applicable Onsite cafeteria (breakfast & lunch) Much, much more! For more information on our partnership with NASA at Johnson Space Center (JSC), please visit www.wehavespaceforyou.com Proof of U.S. Citizenship or US Permanent Residency may be a requirement for this position. Must be able to complete a U.S. government background investigation. Management has the prerogative to select at any level for which the position is advertised. Essential Functions Work Environment Generally, an office environment, but can involve inside or outside work depending on task. Physical Requirements Work may involve sitting or standing for extended periods (90% of time). May require lifting and carrying up to 25 lbs. (5% of time). Equipment and Machines Standard office equipment (PC, telephone, printer, etc.). Attendance Regular attendance in accordance with established work schedule is critical. Ability to work outside normal schedule and adjust schedule to meet peak periods and surge requirements. Other Essential Functions Professional behavior that enhances productivity and promotes teamwork and cooperation. Grooming and dress must be appropriate for the position and must not impose a safety risk/hazard to the employee or others. #JETS #JETSII United States-Texas-Houston-20331-ESCG", "summaryDescription" : "Structures and Mechanisms Engineer, ISS Sustaining at Barrios. Skills: Structures, Mechanisms, ISS sustaining, hardware analysis, flight hardware experience. Provide Subsystem Management support for ISS sustaining. Assist in review and development of hardware, analysis, operation, hazard reviews, anomaly resolution, requirements verification, re-flight assessments, and flight acceptance testing with respect to structures and mechanisms. Coordinate to close technical and programmatic issues. Revi", "createdAt" : "2026-06-14T18:48:36.932", "lastUpdated" : "2026-06-15T07:05:56.402", "ingestTimestamp" : "2026-06-14T18:48:36.932", "mongoId" : "69ce5e1f9bc74574cb6752dd", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "hasSalary" : false, "allSkills" : [ "Bachelor of Science in Mechanical or Aerospace Engineering", "NASA Standards for Structures and Mechanisms", "NASA flight hardware experience", "teamwork, creative ideas, outgoing, self-starter", "Structures, Mechanisms, ISS sustaining, hardware analysis, flight hardware experience", "Structures and Mechanisms, ISS", "Subsystem Management support", "PC, telephone, printer" ], "skillCount" : 8, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Junior", "dataQualityScore" : 0.7777778, "_score" : 513.56244, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Aerospace", "llmIndustryConfidence" : 0.98 }, { "id" : "6a210e2a74d8ee00a0af603c", "title" : "Staff Silicon Physical Design Engineer, Quantum AI", "industry" : "Technology", "salary" : { "min" : 220000.0, "max" : 320000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for a Staff Silicon Physical Design Engineer in Mountain View, USA, adjusted for lead seniority and the technology industry." }, "location" : "[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US]", "locations" : [ "[Mountain View, CA, USA, [100 Bay Vw Dr, Mountain View, CA 94043, USA], Mountain View, 94043, CA, US]", "[Goleta, CA, USA, [Goleta, CA, USA], Goleta, null, CA, US]" ], "timestamp" : "2026-06-16T11:19:47.865", "fingerprint" : "01de68b61fb9a89b022bc3366ddadfe921fdcb679067f7733500242d0a004ca5", "source" : "google", "language" : "en", "externalId" : "129450915651297990", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Mountain View", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3893889,-122.0832101" } ], "locationText" : "Mountain View, California, United States", "experienceMinYears" : 8, "experienceMaxYears" : 15, "experienceLevel" : "Staff", "summaryDescription" : "Staff Silicon Physical Design Engineer, Quantum AI", "postedDate" : "2026-06-16T01:48:20.326", "createdAt" : "2026-06-16T01:48:20.326", "lastUpdated" : "2026-06-16T11:19:47.865", "ingestTimestamp" : "2026-06-16T01:48:20.326", "mongoId" : "6a210e2a74d8ee00a0af603c", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 220000, "salaryAnnualMax" : 320000, "salaryBand" : "200k+", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Lead", "dataQualityScore" : 0.5555556, "_score" : 509.5418, "daysOld" : 0, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "69d3e6b82beec4dd3d3f7351", "title" : "ASIC II", "company" : "Annapurna Labs", "industry" : "Corporate Operations, ASIC, no business category", "salary" : { "min" : 136000.0, "max" : 184000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Austin, Texas, USA", "locations" : [ "Austin, Texas, USA" ], "timestamp" : "2026-06-15T03:14:31.273", "fingerprint" : "28e07010c7f1bb3a3c0b46f7c0fbd2c81a6eddae9ccbf1e3038e67ad9adc0e51", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10384121/apply", "externalId" : "65a6eee4-7290-4cf3-9680-a7e15287cb90", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Austin", "state" : "Texas", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "30.2711286,-97.7436995" } ], "locationText" : "Austin, Texas, United States", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "experienceMinYears" : 2, "experienceMaxYears" : 5, "experienceLevel" : "Mid", "technicalSkills" : "HSPICE, Cadence Sigrity, HFSS, Keysight ADS, SerDes, PCIe", "professionalSkills" : [ "Signal integrity", "Power integrity", "Electromagnetics" ], "hardSkillsList" : [ "Time-domain simulations", "Frequency-domain simulations", "EMIR analysis", "Transmission line theory", "High-speed interfaces", "System-level integrity", "Power delivery architectures" ], "hardSkills" : [ { "name" : "Time-domain simulations", "level" : "intermediate" }, { "name" : "Frequency-domain simulations", "level" : "intermediate" }, { "name" : "EMIR analysis", "level" : "intermediate" }, { "name" : "Transmission line theory", "level" : "intermediate" }, { "name" : "High-speed interfaces", "level" : "intermediate" }, { "name" : "System-level integrity", "level" : "intermediate" }, { "name" : "Power delivery architectures", "level" : "intermediate" } ], "majorSkills" : "Signal integrity, Power integrity, ASIC design, Machine learning ASICs", "majorSkillsList" : [ "Signal integrity", "Power integrity", "ASIC design", "Machine learning ASICs" ], "coreResponsibilities" : "Design SI/PI systems, Validate SI/PI systems, Perform simulations, Apply transmission line theory, Apply electromagnetics, Develop high-speed interfaces, Resolve SI issues, Ensure system-level integrity, Use lab equipment, Validate simulation results, Correlate simulation results, Debug prototypes, Propose innovative solutions, Document simulation outcomes, Document measurement data, Document design trade-offs, Present recommendations", "teamCollaboration" : "Cross-functionally with silicon teams; Cross-functionally with packaging teams; Cross-functionally with board design teams; Cross-functionally with validation teams", "domainKnowledge" : "Machine learning ASICs; Customized hardware platforms; AWS datacenter environments; High-speed interfaces; SoC power delivery; Large-scale compute environments", "domainList" : [ "machine-learning-asics", "customized-hardware-platforms", "aws-datacenter-environments", "high-speed-interfaces", "soc-power-delivery", "large-scale-compute-environments" ], "domainSpecificKnowledge" : [ "Machine learning ASICs", "Customized hardware platforms", "AWS datacenter environments", "High-speed interfaces", "SoC power delivery", "Large-scale compute environments" ], "toolProficiency" : [ "HSPICE", "Cadence Sigrity", "HFSS", "Keysight ADS" ], "communicationSkills" : "Present to stakeholders", "documentationSkills" : "Document simulation outcomes; Document measurement data; Document design trade-offs", "continuousLearning" : "Fostering a culture of continuous learning", "innovationCreativity" : "Proposing innovative solutions", "problemSolvingSkills" : "Resolving complex SI issues; Debugging prototypes; Tackle novel challenges", "outcomesObjectives" : "Meet stringent performance requirements", "qualificationsBasic" : "Bachelor's degree or foreign equivalent, 2 years of experience, 1 year experience using time domain and frequency domain tools, 1 year experience with PCB, Package, interposers, and Silicon, 1 year experience in Transmission line theory and Electromagnetics", "qualificationsPreferred" : "Please see job description and the position requirements above", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "MULTIPLE POSITIONS AVAILABLE Employer: ANNAPURNA LABS (U.S.) INC. Offered Position: ASIC II Job Location: Austin, Texas Job Number: AMZ9679283 Position Responsibilities: Design and validate signal and power integrity (SI/PI) systems for next generation machine learning ASICs and customized hardware platforms optimized for AWS datacenter environments. Perform both time-domain and frequency-domain simulations using tools such as HSPICE, Cadence Sigrity, HFSS, and Keysight ADS, including 3D/2.5D EMIR analysis. Apply transmission line theory and electromagnetics to develop high-speed interfaces like SerDes and PCIe, resolving complex SI issues across digital systems. Collaborate cross-functionally with silicon, packaging, board design, and validation teams to ensure system-level integrity across PCB, interposers, and advanced SoC power delivery architectures using die-level capacitors (DTC, IPD). Use high-speed lab equipment to validate and correlate simulation results, while debugging prototypes to meet stringent performance requirements. Tackle novel challenges in interconnects and power delivery for large-scale compute environments by proposing innovative, high-impact solutions. Document simulation outcomes, measurement data, and design trade-offs, presenting clear recommendations to both technical and non-technical stakeholders while fostering a culture of continuous learning and engineering excellence Position Requirements: Bachelor's degree or foreign equivalent degree in Electrical or Computer Engineering or related field and two years of experience in the job offered or related occupation. Must have one year of experience in the following skills: (1) using time domain and frequency domain tools: Hspice, Sigrity, HFSS, or Microwave Studio; (2) with PCB, Package, interposers (COWOS) and Silicon Technologies; (3) in Transmission line theory and Electromagnetics and its application in SerDes, Single-ended signal and parallel bus interfaces. Amazon.com is an Equal Opportunity-Affirmative Action Employer – Minority / Female / Disability / Veteran / Gender Identity / Sexual Orientation. 40 hours / week, 8:00am-5:00pm, Salary Range $136,000/year to $184,000/year. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, visit: https://www.aboutamazon.com/workplace/employee-benefits.#0000 Basic Qualifications: Position Requirements: Bachelor's degree or foreign equivalent degree in Electrical or Computer Engineering or related field and two years of experience in the job offered or related occupation. Must have one year of experience in the following skills: (1) using time domain and frequency domain tools: Hspice, Sigrity, HFSS, or Microwave Studio; (2) with PCB, Package, interposers (COWOS) and Silicon Technologies; (3) in Transmission line theory and Electromagnetics and its application in SerDes, Single-ended signal and parallel bus interfaces.#0000 Preferred Qualifications: Please see job description and the position requirements above. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "ASIC II at Annapurna Labs. Skills: Signal integrity, Power integrity, ASIC design, Machine learning ASICs. Design SI/PI systems. Validate SI/PI systems", "postedDate" : "2026-06-13T08:19:28.950", "createdAt" : "2026-06-13T08:19:28.950", "lastUpdated" : "2026-06-15T03:14:31.273", "ingestTimestamp" : "2026-06-13T08:19:28.950", "mongoId" : "69d3e6b82beec4dd3d3f7351", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10384121/apply", "salaryAnnualMin" : 136000, "salaryAnnualMax" : 184000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ "Time-domain simulations", "Frequency-domain simulations", "EMIR analysis", "Transmission line theory", "High-speed interfaces", "System-level integrity", "Power delivery architectures", "Signal integrity", "Power integrity", "ASIC design", "Machine learning ASICs", "Electromagnetics", "Customized hardware platforms", "AWS datacenter environments", "SoC power delivery", "Large-scale compute environments", "HSPICE", "Cadence Sigrity", "HFSS", "Keysight ADS" ], "skillCount" : 20, "jobCategory" : "operations", "dataQualityScore" : 1.0, "_score" : 507.94662, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a2c7b5d74d8ee00a0949547", "title" : "Distinguished Engineer, ASIC (CONTRACT)", "company" : "Butterfly Network", "industry" : "Manufacturing", "salary" : { "min" : 300000.0, "max" : 500000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for an Executive-level Distinguished Engineer in the Technology industry in Burlington, United States, adjusted for company size and contract employment type." }, "location" : "Burlington, Massachusetts, United States", "locations" : [ "Burlington", "Massachusetts", "United States", "New York", "New York", "United States", "Other", "United States - Remote" ], "timestamp" : "2026-06-15T08:13:21.122", "fingerprint" : "339add01e543196359cc5de6cc19b3b42dd2b110aad9b78929e415ea5b70e30b", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://www.butterflynetwork.com/careers?gh_jid=7753260003", "externalId" : "7753260003", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Burlington", "state" : "Massachusetts", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "hybrid", "geo" : "42.5048167,-71.1956111" } ], "locationText" : "Burlington, Massachusetts, United States", "employmentType" : "CONTRACT", "minimumEducation" : "BS/MS/PhD", "experienceMinYears" : 8, "experienceMaxYears" : 12, "experienceLevel" : "Senior", "technicalSkills" : "SystemVerilog, Verilog, DSP, AI, SRAM, IP integration", "professionalSkills" : [ "Architecture", "Tradeoffs", "Implementation", "Verification", "Signoff", "Handoff", "Integration", "Data paths", "Interfaces", "Pipelines", "Compute", "Accelerators", "Fabrics" ], "hardSkillsList" : [ "Digital IC design", "ASIC design", "SoC design", "RTL design", "Timing closure", "Power-aware design", "PPA analysis", "Digital signal processing", "High-speed interface design", "System-on-a-chip logic", "Data path design", "Control logic design", "State machine design", "Streaming interface design", "Memory hierarchy design", "Hardware-firmware interface design", "Register map design", "Control path design", "Status path design", "Data plane design", "Compute pipeline design", "Beamforming pipeline design", "AI accelerator design", "MPU integration", "EFPGA fabric integration" ], "hardSkills" : [ { "name" : "Digital IC design", "level" : "intermediate" }, { "name" : "ASIC design", "level" : "intermediate" }, { "name" : "SoC design", "level" : "intermediate" }, { "name" : "RTL design", "level" : "intermediate" }, { "name" : "Timing closure", "level" : "intermediate" }, { "name" : "Power-aware design", "level" : "intermediate" }, { "name" : "PPA analysis", "level" : "intermediate" }, { "name" : "Digital signal processing", "level" : "intermediate" }, { "name" : "High-speed interface design", "level" : "intermediate" }, { "name" : "System-on-a-chip logic", "level" : "intermediate" }, { "name" : "Data path design", "level" : "intermediate" }, { "name" : "Control logic design", "level" : "intermediate" }, { "name" : "State machine design", "level" : "intermediate" }, { "name" : "Streaming interface design", "level" : "intermediate" }, { "name" : "Memory hierarchy design", "level" : "intermediate" }, { "name" : "Hardware-firmware interface design", "level" : "intermediate" }, { "name" : "Register map design", "level" : "intermediate" }, { "name" : "Control path design", "level" : "intermediate" }, { "name" : "Status path design", "level" : "intermediate" }, { "name" : "Data plane design", "level" : "intermediate" }, { "name" : "Compute pipeline design", "level" : "intermediate" }, { "name" : "Beamforming pipeline design", "level" : "intermediate" }, { "name" : "AI accelerator design", "level" : "intermediate" }, { "name" : "MPU integration", "level" : "intermediate" }, { "name" : "EFPGA fabric integration", "level" : "intermediate" } ], "majorSkills" : "Digital ASIC Design, RTL Implementation, Verification Signoff, System-on-a-Chip", "majorSkillsList" : [ "Digital ASIC Design", "RTL Implementation", "Verification Signoff", "System-on-a-Chip" ], "coreResponsibilities" : "Design digital signal processing logic, Implement digital signal processing logic, Verify digital signal processing logic, Design high speed interface logic, Implement high speed interface logic, Verify high speed interface logic, Design system-on-a-chip logic, Implement system-on-a-chip logic, Verify system-on-a-chip logic, Own complex digital IC subsystems, Perform PPA tradeoffs, Implement RTL, Achieve verification signoff, Perform tapeout handoff, Architect sustained high-throughput datapaths, Design buffering, Design arbitration, Design backpressure, Perform bandwidth budgeting, Design SRAM/memory hierarchy, Collaborate with verification teams, Validate complex digital architectures, Resolve functional issues, Work cross-functionally with analog teams, Work cross-functionally with systems teams, Work cross-functionally with packaging/board teams, Close chip-level requirements, Close integration details, Define hardware-firmware interfaces, Define register maps, Define control/status paths, Define data-plane contracts, Implement compute-intensive digital pipelines, Design AI accelerators, Integrate AI accelerators, Integrate MPUs, Integrate eFPGA fabrics", "teamCollaboration" : "Cross-functional teams; Verification teams; Analog teams; Systems teams; Packaging/board teams", "domainKnowledge" : "Ultrasound-on-Chip technology; Point-of-care ultrasound; Medical imaging; Ultrasound systems; Beamforming pipelines; Sensor data acquisition; AI accelerators; MPUs; eFPGA fabrics", "domainList" : [ "ultrasound-on-chip-technology", "point-of-care-ultrasound", "medical-imaging", "ultrasound-systems", "beamforming-pipelines", "sensor-data-acquisition", "ai-accelerators", "mpus", "efpga-fabrics" ], "domainSpecificKnowledge" : [ "Ultrasound-on-Chip technology", "Point-of-care ultrasound", "Medical imaging", "Ultrasound systems", "Beamforming pipelines", "Sensor data acquisition", "AI accelerators", "MPUs", "eFPGA fabrics" ], "documentationSkills" : "Register maps", "innovationCreativity" : "Innovation", "problemSolvingSkills" : "Problem-solvers; Resolve functional issues", "qualificationsBasic" : "BS/MS/PhD in EE/CE/CS, 8-12+ years digital IC/ASIC/SoC design, Hands-on RTL ownership, Digital IC implementation understanding, Timing closure implications, Clock/reset domain architecture, Power-aware design, PPA tradeoffs, Own complex digital IC subsystems, RTL implementation, Verification signoff, Tapeout handoff, SystemVerilog/Verilog RTL skills, Silicon-proven digital architectures, Pipelined datapatths, Control logic, State machines, High-throughput streaming interfaces, Architect sustained high-throughput datapaths, Buffering, Arbitration, Backpressure, Bandwidth budgeting, SRAM/memory hierarchy design, Advanced technology nodes (28nm or smaller), Timing closure challenges, Integration of third-party IP, Collaborate with verification teams, Validate complex digital architectures, Resolve functional issues, Cross-functionally with analog teams, Cross-functionally with systems teams, Cross-functionally with packaging/board teams, Close chip-level requirements, Close integration details, Hardware-firmware interfaces, Register maps, Control/status paths, Data-plane contracts", "qualificationsPreferred" : "Experience implementing compute-intensive digital pipelines, DSP pipelines, Beamforming pipelines, AI pipelines, MAC-heavy/vector datapaths, Exposure to medical imaging systems, Exposure to ultrasound systems, Exposure to beamforming pipelines, Exposure to sensor data acquisition architectures, Designing programmable digital compute blocks, Integrating programmable digital compute blocks, AI accelerators, MPUs, EFPGA fabrics, Instruction/control interfaces, Memory hierarchy, Data movement, PPA tradeoffs", "workSiteFlexibility" : "Hybrid", "rawDescription" : "Company Description Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with its proprietary Ultrasound-on-Chip™ semiconductor technology and software solutions. Butterfly first proved its technology in the point-of-care ultrasound market – commercializing the world’s first single-probe, whole-body portable ultrasound device, which is now on its best-selling, third-generation: Butterfly iQ3™. The Company combines its advanced hardware with cloud software and AI, an enterprise workflow solution (Compass AI™) and other offerings to drive adoption of affordable, accessible ultrasound. Butterfly also enables third-party development of imaging AI apps through Butterfly Garden™, its software development kit and AI partnership initiative. In addition to its medical imaging products, Butterfly Embedded™ is the Company’s Ultrasound-on-Chip™ licensing and co-development program designed to enable a new wave of ultrasound-enabled technologies across non-competitive healthcare markets and beyond. Through Butterfly Embedded™, partners can build and scale novel ultrasound applications powered by Butterfly’s proprietary semiconductor chip and software platform. Butterfly’s innovations have been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions and Fast Company’s World Changing Ideas, among other achievements. We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let’s build something extraordinary together! Job Description The role of the Distinguished Engineer, Digital ASIC Designer offers the opportunity to work within the heart of the product development team to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products. Qualifications Baseline skills/experiences/attributes: BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience. 8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership. Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs. Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design. Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces. Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP. Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff. Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts). Ideally, you also have these skills/experiences/attributes (but it’s ok if you don’t!): Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths). Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures. Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs. Values Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in… Patient-Centric Innovators: Our mission is THE mission. Empowered to Impact: Every voice matters. One Team, One Goal: Unity fuels progress. Growth Champions: We embrace challenges. Action-Oriented Achievers: We follow through, every time. Location Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers. For this role, location will depend on candidate qualifications and experience. This role may be based out of one of our U. S. offices, including: SF Bay Area Burlington, MA For this temporary role, we are only considering candidates who are legally authorized to work in the United States and who do not now or in the future require sponsorship or transfer for employment visa status. Butterfly network does not accept agency resumes for this temporary position. Butterfly Network Inc. is an E-Verify Company and is an equal opportunity employer regardless of race, color, ancestry, religion, gender, national origin, sexual orientation, age, citizenship, marital status, disability or Veteran status. All your information will be kept confidential according to EEO guidelines. Butterfly requires security adherence responsibilities from all employees. These include: adhering to all company security policies and procedures, utilize provided company assets securely, and complete all required security awareness training programs. Safeguarding company data and systems from unauthorized access, modification, or", "summaryDescription" : "Distinguished Engineer, ASIC (CONTRACT) at Butterfly Network. Skills: Digital ASIC Design, RTL Implementation, Verification Signoff, System-on-a-Chip. Design digital signal processing logic. Implement digital signal processing logic", "postedDate" : "2026-06-13T20:32:43.377", "createdAt" : "2026-06-13T20:32:43.377", "lastUpdated" : "2026-06-15T08:13:21.122", "ingestTimestamp" : "2026-06-13T20:32:43.377", "mongoId" : "6a2c7b5d74d8ee00a0949547", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 300000, "salaryAnnualMax" : 500000, "salaryBand" : "200k+", "hasSalary" : true, "allSkills" : [ "Digital IC design", "ASIC design", "SoC design", "RTL design", "Timing closure", "Power-aware design", "PPA analysis", "Digital signal processing", "High-speed interface design", "System-on-a-chip logic", "Data path design", "Control logic design", "State machine design", "Streaming interface design", "Memory hierarchy design", "Hardware-firmware interface design", "Register map design", "Control path design", "Status path design", "Data plane design", "Compute pipeline design", "Beamforming pipeline design", "AI accelerator design", "MPU integration", "EFPGA fabric integration", "Digital ASIC Design", "RTL Implementation", "Verification Signoff", "System-on-a-Chip", "Architecture", "Tradeoffs", "Implementation", "Verification", "Signoff", "Handoff", "Integration", "Data paths", "Interfaces", "Pipelines", "Compute", "Accelerators", "Fabrics", "Ultrasound-on-Chip technology", "Point-of-care ultrasound", "Medical imaging", "Ultrasound systems", "Beamforming pipelines", "Sensor data acquisition", "AI accelerators", "MPUs", "eFPGA fabrics" ], "skillCount" : 51, "jobCategory" : "engineering", "jobSubcategory" : "software", "seniorityLevel" : "Executive", "dataQualityScore" : 1.0, "_score" : 507.233, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.98 }, { "id" : "6a09f2101663d49372a83a5e", "title" : "Manager, ASIC Sustaining Engineering, Silicon Operations", "company" : "Amazon Kuiper Manufacturing Enterprises LLC", "industry" : "Project/Program/Product Management--Non-Tech, Technical Program Management, alexa and amazon devices", "salary" : { "min" : 171000.0, "max" : 231400.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Sunnyvale, California, USA", "locations" : [ "Sunnyvale, California, USA" ], "timestamp" : "2026-06-15T03:06:56.467", "fingerprint" : "c81d6478084586ece72974c3f9681b2051c7d7a4c6ae21d445dec5a130aa9482", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.jobs/jobs/10420679/apply", "externalId" : "511400cf-be53-4ac0-a542-2d403154fd48", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Sunnyvale", "state" : "California", "country" : "United States", "continent" : "na", "source" : "llm", "workMode" : "onsite", "geo" : "37.3688301,-122.0363490" } ], "locationText" : "Sunnyvale, California, United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceLevel" : "Manager", "technicalSkills" : "Software development", "professionalSkills" : [ "Product management", "Program management", "Process building", "Release coordination", "Scope management", "Schedule management", "Quality management", "Risk management", "Path management" ], "hardSkillsList" : [ "Statistical analysis", "Data analysis", "Failure analysis", "Process optimization", "Yield improvement", "Root cause analysis", "Electrical failure analysis", "Physical failure analysis", "Design rule review", "Layout review", "DFM", "Yield characterization" ], "softSkillsList" : [ "Leadership" ], "hardSkills" : [ { "name" : "Statistical analysis", "level" : "intermediate" }, { "name" : "Data analysis", "level" : "intermediate" }, { "name" : "Failure analysis", "level" : "intermediate" }, { "name" : "Process optimization", "level" : "intermediate" }, { "name" : "Yield improvement", "level" : "intermediate" }, { "name" : "Root cause analysis", "level" : "intermediate" }, { "name" : "Electrical failure analysis", "level" : "intermediate" }, { "name" : "Physical failure analysis", "level" : "intermediate" }, { "name" : "Design rule review", "level" : "intermediate" }, { "name" : "Layout review", "level" : "intermediate" }, { "name" : "DFM", "level" : "intermediate" }, { "name" : "Yield characterization", "level" : "intermediate" } ], "softSkills" : [ { "name" : "Leadership" } ], "majorSkills" : "ASIC Sustaining Engineering, Silicon Operations, Yield Improvement, Root Cause Analysis", "majorSkillsList" : [ "ASIC Sustaining Engineering", "Silicon Operations", "Yield Improvement", "Root Cause Analysis" ], "coreResponsibilities" : "Improve yield to meet target, Improve yield to beat target, Root Cause Analysis for yield excursions, Identify yield limiters, Identify yield trends, Conduct failure analysis, Identify source of yield excursions, Prevent yield excursions, Design experiments, Execute experiments, Optimize manufacturing processes, Reduce particle contamination, Implement solutions, Maintain production lines, Troubleshoot production lines, Install inspection equipment, Qualify inspection equipment, Maintain inspection equipment, Create specifications, Maintain specifications, Create process documentation, Maintain process documentation, Create best-known methods, Maintain best-known methods, Lead team to identify root cause, Analyze CP test bin, Analyze data log, Identify failure mode, Work with supplier, Define corrective actions, Define solutions, Trace action implementation, Verify action effectiveness, Support early-stage design, Help product tape-out, Review design rules, Assess design rules, Review layout, Enlarge manufacturing window, Identify device sweet spot, Identify best yield process condition, Identify best performance process condition", "teamCollaboration" : "Cross functional teams; Process engineers; Equipment engineers; Design engineers; Supplier collaboration", "projectManagementSkills" : [ "Scope management", "Schedule management", "Budget management", "Quality management", "Risk management", "Critical path management" ], "domainKnowledge" : "Wafer fabrication; Assembly; Test; Electrical test; In-line inspection; Particle contamination; Chip performance; Chip quality; Manufacturing processes; Product design; Manufacturing window; Process condition", "domainList" : [ "wafer-fabrication", "assembly", "test", "electrical-test", "in-line-inspection", "particle-contamination", "chip-performance", "chip-quality", "manufacturing-processes", "product-design", "manufacturing-window", "process-condition" ], "domainSpecificKnowledge" : [ "Wafer fabrication", "Assembly", "Test", "Electrical test", "In-line inspection", "Particle contamination", "Chip performance", "Chip quality", "Manufacturing processes", "Product design", "Manufacturing window", "Process condition" ], "toolProficiency" : [ "Statistical tools", "Data analysis tools", "DOE" ], "communicationSkills" : "Communicate effectively; Communicate respectfully", "documentationSkills" : "Process documentation; Best-known methods", "problemSolvingSkills" : "Root cause analysis; Failure analysis; Troubleshooting", "specialRequirements" : "Work safely, Work cooperatively, Adhere to standards, Adhere to laws, Adhere to policies, Exercise sound judgment, Manage stress, Exhibit trustworthiness, Exhibit professionalism, Safeguard business operations, Safeguard company reputation", "outcomesObjectives" : "Meet target yield; Beat target yield; Ensure Si success", "qualificationsBasic" : "5+ years technical product management, 7+ years working with engineering teams, 3+ years software development, 5+ years TPM with software engineering, Manage programs cross functional teams, Build processes, Coordinate release schedules", "qualificationsPreferred" : "5+ years project management disciplines, Manage projects cross functional teams, Build sustainable processes, Coordinate release schedules, Define KPIs/SLAs, Report to senior leadership", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "The ASIC Sustaining Engineer has the responsibility for Yield improvement to meet or beat target and Root Cause Analysis for Yield excursions across Wafer, Assembly and Test. Use statistical tools and data analysis to identify yield limiters and trends in electrical test and in-line inspection data. Conduct failure analysis (FA) on defective wafers and devices to identify the source of, or prevent, yield excursions. Design and execute experiments (DOE) to optimize manufacturing processes and reduce particle contamination. Partner with process, equipment, and design engineers to implement solutions to improve, maintain, or troubleshoot production lines. Install, qualify, and maintain in-line defect inspection and review equipment. Create and maintain specifications, process documentation, and best-known methods Key job responsibilities Lead team to identify root cause for chip performance / yield / quality issues. Analyze CP test bin / data log to identify failure mode. Electrical failure analysis and physical failure analysis to locate suspect process stage Work with appropriate supplier to define corrective actions / solutions. Trace action implementation to verify effectiveness. Product early-stage design support to help product tape-out smoothly and Si success: Design rule review & assessment for robust product design Layout review or DFM to enlarge manufacturing window Yield window characterization and device sweet spot identification for the best yield / performance process condition. Basic Qualifications: - 5+ years of technical product or program management experience - 7+ years of working directly with engineering teams experience - 3+ years of software development experience - 5+ years of technical program management working directly with software engineering teams experience - Experience managing programs across cross functional teams, building processes and coordinating release schedules Preferred Qualifications: - 5+ years of project management disciplines including scope, schedule, budget, quality, along with risk and critical path management experience - Experience managing projects across cross functional teams, building sustainable processes and coordinating release schedules - Experience defining KPI's/SLA's used to drive multi-million dollar businesses and reporting to senior leadership Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, CA, Sunnyvale - 171,000.00 - 231,400.00 USD annually USA, WA, Bellevue - 148,700.00 - 201,200.00 USD annually", "summaryDescription" : "Manager, ASIC Sustaining Engineering, Silicon Operations at Amazon Kuiper Manufacturing Enterprises LLC. Skills: ASIC Sustaining Engineering, Silicon Operations, Yield Improvement, Root Cause Analysis. Improve yield to meet target. Improve yield to beat target", "postedDate" : "2026-05-15T00:00:00.000", "createdAt" : "2026-06-13T07:39:16.265", "lastUpdated" : "2026-06-15T03:06:56.467", "ingestTimestamp" : "2026-06-13T07:39:16.265", "mongoId" : "6a09f2101663d49372a83a5e", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.jobs/jobs/10420679/apply", "salaryAnnualMin" : 171000, "salaryAnnualMax" : 231400, "salaryBand" : "150k-200k", "hasSalary" : true, "allSkills" : [ "Statistical analysis", "Data analysis", "Failure analysis", "Process optimization", "Yield improvement", "Root cause analysis", "Electrical failure analysis", "Physical failure analysis", "Design rule review", "Layout review", "DFM", "Yield characterization", "Leadership", "ASIC Sustaining Engineering", "Silicon Operations", "Yield Improvement", "Root Cause Analysis", "Product management", "Program management", "Process building", "Release coordination", "Scope management", "Schedule management", "Quality management", "Risk management", "Path management", "Budget management", "Critical path management", "Wafer fabrication", "Assembly", "Test", "Electrical test", "In-line inspection", "Particle contamination", "Chip performance", "Chip quality", "Manufacturing processes", "Product design", "Manufacturing window", "Process condition", "Statistical tools", "Data analysis tools", "DOE" ], "skillCount" : 43, "jobCategory" : "project-management", "dataQualityScore" : 1.0, "_score" : 506.72327, "daysOld" : 31, "hasLocation" : true, "hasGeo" : true }, { "id" : "6a307629f292fd229c016b4b", "title" : "Senior Environmental Sustainability & ESG Manager", "company" : "Twilio", "salary" : { "min" : 141520.0, "max" : 208000.0, "currency" : "USD", "frequency" : "yearly", "is_estimated" : false }, "location" : "Remote - US", "locations" : [ "Remote - US" ], "timestamp" : "2026-06-16T12:13:28.483", "fingerprint" : "09cb9ee91bc1d8680f441c993d8c2d2f48810b6460c04a5859322093ee5779e8", "source" : "greenhouse", "language" : "en", "applyUrl" : "https://job-boards.greenhouse.io/twilio/jobs/8008030", "externalId" : "8008030", "industryFunction" : { }, "structuredLocations" : [ { "country" : "United States", "continent" : "na", "workMode" : "remote" } ], "locationText" : "United States", "employmentType" : "FULL_TIME", "experienceMinYears" : 5, "experienceMaxYears" : 10, "experienceLevel" : "Senior", "remoteFriendly" : true, "workSiteFlexibility" : "Remote", "rawDescription" : "Who we are At Twilio, we’re shaping the future of communications, all from the comfort of our homes. We deliver innovative solutions to hundreds of thousands of businesses and empower millions of developers worldwide to craft personalized customer experiences. Our dedication to remote-first work, and strong culture of connection and global inclusion means that no matter your location, you’re part of a vibrant team with diverse experiences making a global impact each day. As we continue to revolutionize how the world interacts, we’re acquiring new skills and experiences that make work feel truly rewarding. Your career at Twilio is in your hands. We use Artificial Intelligence (AI) to help make our hiring process efficient. That said, every hiring decision is made by real Twilions! . See yourself at Twilio Join the team as Twilio’s next Senior Environmental Sustainability design and execute implementation pathways to achieve targets, which could include internal behavior or process changes, market-based instruments (e.g., SAFc, VPPA), high-quality carbon offsets, supplier-based sustainability initiatives. In partnership with the VP, Social advanced degree or certifications a plus. Location This role will be remote, but is not eligible to be hired in CA, CT, NJ, NY, PA, WA. Travel We prioritize connection and opportunities to build relationships with our customers and each other. For this role, you may be required to travel occasionally to participate in project or team in-person meetings. What We Offer Working at Twilio offers many benefits, including competitive pay, generous time off, ample parental and wellness leave, healthcare, a retirement savings program, and much more. Offerings vary by location. Compensation *Please note this role is open to candidates outside of California, Colorado, Hawaii, Illinois, Maryland, Massachusetts, Minnesota, New Jersey, New York, Vermont, Washington D.C., and Washington State. The information below is provided for candidates hired in those locations only. The estimated pay ranges for this role are as follows: Based in Colorado, Hawaii, Illinois, Maryland, Massachusetts, Minnesota, Vermont or Washington D. C. : $141,520 - $176,900. Based in New York, New Jersey, Washington State, or California (outside of the San Francisco Bay area): $149,840 - $187,300. Based in the San Francisco Bay area, California: $166,400 - $208,000. This role may be eligible to participate in Twilio’s equity plan and corporate bonus plan. All roles are generally eligible for the following benefits: health care insurance, 401(k) retirement account, paid sick time, paid personal time off, paid parental leave. The successful candidate’s starting salary will be determined based on permissible, non-discriminatory factors such as skills, experience, and geographic location. Application deadline information Applications for this role are intended to be accepted until July 31, 2026, but may change based on business needs. Twilio thinks big. Do you? We like to solve problems, take initiative, pitch in when needed, and are always up for trying new things. That's why we seek out colleagues who embody our values — something we call Twilio Magic. Additionally, we empower employees to build positive change in their communities by supporting their volunteering and donation efforts. So, if you're ready to unleash your full potential, do your best work, and be the best version of yourself, apply now! If this role isn't what you're looking for, please consider other open positions. Twilio is proud to be an equal opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Additionally, Twilio participates in the E-Verify program in certain locations, as required by law.", "summaryDescription" : "Senior Environmental Sustainability & ESG Manager at Twilio", "postedDate" : "2026-06-16T01:17:46.523", "createdAt" : "2026-06-16T01:17:46.523", "lastUpdated" : "2026-06-16T12:13:28.483", "ingestTimestamp" : "2026-06-16T01:17:46.523", "mongoId" : "6a307629f292fd229c016b4b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "salaryAnnualMin" : 141520, "salaryAnnualMax" : 208000, "salaryBand" : "100k-150k", "hasSalary" : true, "allSkills" : [ ], "skillCount" : 0, "jobCategory" : "operations", "jobSubcategory" : "general", "seniorityLevel" : "Senior", "dataQualityScore" : 0.8888889, "_score" : 505.90424, "daysOld" : 0, "hasLocation" : true, "hasGeo" : false, "llmIndustry" : "Technology", "llmIndustryConfidence" : 0.95 }, { "id" : "69e1043a2beec4dd3def1c5b", "title" : "ASIC Design Engineer", "company" : "Evi Technologies Limited", "industry" : "Hardware Development, ASIC, alexa and amazon devices", "salary" : { "min" : 65000.0, "max" : 95000.0, "currency" : "GBP", "frequency" : "yearly", "is_estimated" : true, "estimation_basis" : "Market baseline for an ASIC Design Engineer in Cambridge, UK, adjusted for mid-seniority and the technology industry." }, "location" : "Cambridge, England, GBR", "locations" : [ "Cambridge, England, GBR" ], "timestamp" : "2026-06-15T02:56:51.677", "fingerprint" : "34a2ccfd7306b7e13ea6a2f2e805c488ebd16b9a288d976e64e361718686c768", "source" : "amazon", "language" : "en", "applyUrl" : "https://account.amazon.com/jobs/10387315/apply", "externalId" : "29cc8e76-1163-4a7e-9409-2533ed995736", "industryFunction" : { }, "structuredLocations" : [ { "city" : "Cambridge", "state" : "England", "country" : "United Kingdom", "continent" : "eu", "source" : "llm", "workMode" : "onsite", "geo" : "52.1975846,0.1391537" } ], "locationText" : "Cambridge, England, United Kingdom", "employmentType" : "FULL_TIME", "minimumEducation" : "Bachelor's", "technicalSkills" : "System Verilog, Verilog, Python, Perl", "professionalSkills" : [ "Micro-architecture specs", "Power analysis", "Performance analysis", "Area estimation" ], "hardSkillsList" : [ "RTL design", "DFT", "UPF" ], "hardSkills" : [ { "name" : "RTL design", "level" : "intermediate" }, { "name" : "DFT", "level" : "intermediate" }, { "name" : "UPF", "level" : "intermediate" } ], "majorSkills" : "ASIC Design, RTL, Verification", "majorSkillsList" : [ "ASIC Design", "RTL", "Verification" ], "coreResponsibilities" : "Write micro-architecture specs, Solicit feedback, Link to KPIs, Execute on design specifications, Deliver high quality RTL, Evaluate 3rd party IP blocks, Estimate power, Estimate performance, Estimate area, Ensure quality, Run front-end tools, Track results, Work with pre-silicon verification teams, Assist in defining test-plans, Assist in defining test-benches, Work with post-silicon validation teams, Define test-plans, Execute test-plans", "teamCollaboration" : "Vertically integrated team; Pre-silicon verification teams; Post-silicon validation teams", "domainKnowledge" : "Battery powered devices; SoCs; AI; Video processing; Low power communications; CMOS fabrication", "domainList" : [ "battery-powered-devices", "socs", "ai", "video-processing", "low-power-communications", "cmos-fabrication" ], "domainSpecificKnowledge" : [ "Battery powered devices", "SoCs", "AI", "Video processing", "Low power communications", "CMOS fabrication" ], "toolProficiency" : [ "Lint", "CDC", "RDC", "STA", "Synthesis" ], "documentationSkills" : "Micro-architecture specs", "innovationCreativity" : "Innovators; Invent; Simplify; Build", "problemSolvingSkills" : "Debugging; Design problems", "qualificationsBasic" : "Experience identifying bugs, Debugging skills, Experience with front-end design tools, Lint, CDC, RDC, Ability to write micro-architectural specs, System Verilog, Verilog", "qualificationsPreferred" : "Bachelor's degree in Electrical or Communications Engineering, Experience with industry standard tools, Scripting languages for automation, Python, Perl, Experience with hardware-software interfaces, Using formal verification tools", "remoteFriendly" : false, "workSiteFlexibility" : "Onsite", "rawDescription" : "Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Write micro-architecture specs and solicit feedback/link to KPIs from architecture team - Execute on design specifications to deliver high quality RTL - Evaluate 3rd party IP blocks - Estimate power, performance, and area for significant IPs early in design cycle - Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon verification teams to assist in defining test-plans/test-benches - Work with post-silicon validation teams to define and execute on test-plans Basic Qualifications: - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills - Experience with front-end design tools (Lint, CDC, RDC and lint) - Ability to write detailed micro-architectural specs which work through the design problems before coding (System Verilog, Verilog). Preferred Qualifications: - Bachelor's degree in Electrical or Communications Engineering or a related field - Experience with industry standard tools and scripting languages (Python or Perl) for automation - Experience with hardware-software interfaces - Using formal verification tools to enhance RTL quality before testing. Amazon is an equal opportunities employer. We believe passionately that employing a diverse workforce is central to our success. We make recruiting decisions based on your experience and skills. We value your passion to discover, invent, simplify and build. Protecting your privacy and the security of your data is a longstanding top priority for Amazon. Please consult our Privacy Notice ( https://www.amazon.jobs/en/privacy_page ) to know more about how we collect, use and transfer the personal data of our candidates. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "summaryDescription" : "ASIC Design Engineer at Evi Technologies Limited. Skills: ASIC Design, RTL, Verification. Write micro-architecture specs. Solicit feedback", "postedDate" : "2026-06-13T06:05:56.897", "createdAt" : "2026-06-13T06:05:56.897", "lastUpdated" : "2026-06-15T02:56:51.677", "ingestTimestamp" : "2026-06-13T06:05:56.897", "mongoId" : "69e1043a2beec4dd3def1c5b", "processingStatus" : "llm_updated", "llmProcessingStatus" : true, "sourceUrl" : "https://account.amazon.com/jobs/10387315/apply", "salaryBand" : "50k-75k", "hasSalary" : false, "allSkills" : [ "RTL design", "DFT", "UPF", "ASIC Design", "RTL", "Verification", "Micro-architecture specs", "Power analysis", "Performance analysis", "Area estimation", "Battery powered devices", "SoCs", "AI", "Video processing", "Low power communications", "CMOS fabrication", "Lint", "CDC", "RDC", "STA", "Synthesis" ], "skillCount" : 21, "jobCategory" : "other", "dataQualityScore" : 0.8888889, "_score" : 504.3197, "daysOld" : 1, "hasLocation" : true, "hasGeo" : true, "llmIndustry" : "Technology" } ], "status" : 200, "message" : "OK", "pagination" : { "page" : 0, "limit" : 50, "totalCount" : 197850, "totalPages" : 3957, "hasNext" : true, "hasPrevious" : false } }

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