Asic Fpga Design Engineering Mid Level Manager
Jobs
Active Asic Fpga Design Engineering Mid Level Manager roles are indexed directly from company ATS systems — Greenhouse, Lever, Workday, Ashby, and 15+ others. Advertised salaries average $267k/year based on live listings. 62% of roles are remote-friendly. These listings don't come from other job boards — they're pulled from source, so many won't appear on LinkedIn, Indeed, or Glassdoor.
Open Roles
0
Avg Salary
$267k
Remote-Friendly
62%
Added This Week
46
FPGA Design Engineer II
HPR
Senior FPGA Design Engineer
Lynk
Junior ASIC Design Engineer
Astera Labs
ASIC Digital Design Engineer II, Silicon Engineering
Lead FPGA Design Engineer
Neurophos
FPGA Design Engineer
Velmenni
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Mid-Level Instructional Designer
INFUSE
Senior Engineer, ASIC development Engineering (ASIC, SOC Validation)
Sandisk
Senior Engineer, ASIC development Engineering (ASIC, SOC Validation)
Sandisk
ASIC Sustaining Engineering Manager
Amazon Kuiper Manufacturing Enterprises LLC
Mid-level iOS Developer
CI&T
Manager, ASIC Sustaining Engineering, Silicon Operations
Amazon Kuiper Manufacturing Enterprises LLC
Mid-level Developer
Lexlegis AI
ASIC Design Verification Technical Lead, TPU
ASIC Design Verification Engineer, TPU Cloud
Sr FPGA Designer
Intuitive
Sr FPGA Designer
Intuitive
ASIC Design Engineer
Evi Technologies Limited
Mechanical Engineer Manager, Design Engineering, DC Design Engineering
Amazon Corporate Services Pty Ltd
Senior ASIC Design Engineer
Amazon Technologies, Inc.
Mid-Level Electrical Advisor
Strategic Mission Critical
Mid-Level Mechanical Advisor
Strategic Mission Critical
Mid-Level Electrical Engineer
Strategic Mission Critical
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Common Questions
- How many Asic Fpga Design Engineering Mid Level Manager jobs are available?
- JobsGlitch lists active Asic Fpga Design Engineering Mid Level Manager jobs sourced daily from Greenhouse, Lever, Ashby, Workday, and other top ATS platforms.
- What skills are required for Asic Fpga Design Engineering Mid Level Manager roles?
- The most in-demand skills for Asic Fpga Design Engineering Mid Level Manager roles are Firmware development, ASIC Design, Post-silicon validation, FPGA Design, Synthesis. Requirements vary by seniority and company.
- What is the average salary for a Asic Fpga Design Engineering Mid Level Manager?
- The average salary for Asic Fpga Design Engineering Mid Level Manager roles on JobsGlitch is approximately $267k/year. Compensation varies by location, seniority, and company.
- Are there remote Asic Fpga Design Engineering Mid Level Manager jobs?
- Yes — 62% of Asic Fpga Design Engineering Mid Level Manager jobs on JobsGlitch are remote-friendly. Browse remote Asic Fpga Design Engineering Mid Level Manager jobs at jobsglitch.com/jobs/remote/asic-fpga-design-engineering-mid-level-manager.