HPR

FinTech

FPGADesignEngineerII

$129–166k Needham, Massachusetts, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Mid candidates.

The Brief

“FPGA Design Engineer II at HPR. Skills: FPGA Design, RTL Design, Digital Logic Design, Networking Protocols. Design compute systems. Develop compute systems”

Industry & Context.

FinTech
Problems you'll solve

Problem solving; Debugging

Eligibility Requirements

On-site 5 days per week

What They're Looking For.

Must Have

BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related, 3+ years of experience in digital logic design for FPGAs or ASICs, SystemVerilog or VHDL proficiency, Deep understanding of computer architecture, Deep understanding of digital design concepts, Experience with industry-standard simulation tools, Experience with industry-standard debugging tools, Comfortable working in a Linux environment, Problem solving skills, Debugging skills, Communication skills

Nice to Have

SystemVerilog proficiency, Experience with Xilinx FPGAs, Experience with Altera FPGAs, Familiarity with FPGA architecture, Familiarity with advanced design techniques, Familiarity with optimizations for synthesis, Familiarity with optimizations for timing closure, In-depth knowledge of networking protocols, Experience with high-speed interfaces, Familiarity with C programming, Familiarity with Python scripting, Familiarity with Perl scripting

What You'll Do.

Design compute systems

Develop compute systems

Optimize compute systems

Maintain compute systems

Design networking systems

Develop networking systems

Optimize networking systems

Maintain networking systems

Own RTL design process

Synthesize RTL design

Implement FPGA designs

Partner with verification engineers

Lead junior engineers

Mentor junior engineers

Promote continuous learning

Promote collaboration

Contribute to improving development processes

Contribute to improving development tools

Contribute to improving development methodologies

How You'll Work.

Team & Collaboration

Design verification engineers; Junior engineers

Full Job Description

HPR is a leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1 financial institutions to monitor and execute trades rapidly and efficiently. As we continue to innovate and grow, we’re searching for a forward-thinking FPGA Design Engineer to help us build the future of capital markets infrastructure. As an FPGA Design Engineer at HPR, you will: Design, develop, optimize, and maintain high-performance FPGA compute and networking systems used in electronic trading Own the RTL design process from specification and coding through synthesis and FPGA implementation Partner with design verification engineers to review and execute comprehensive test plans Lead and mentor junior engineers, promoting our culture of continuous learning and collaboration Contribute to improving our development processes, tools, and methodologies Required Qualifications BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related 3+ years of experience in digital logic design for FPGAs or ASICs Proficiency in SystemVerilog (preferred) or VHDL Deep understanding of computer architecture and digital design concepts Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi) Comfortable working in a Linux environment Strong problem solving, debugging, and communication skills Desired Qualifications Experience working with Xilinx and/or Altera FPGAs Familiarity with FPGA architecture and advanced design techniques, including optimizations for synthesis and timing closure In-depth knowledge of networking protocols (IP, TCP, UDP) Experience with high-speed interfaces (PCIe, Ethernet, and/or DDR) Familiarity with C programming and scripting in Python and/or Perl Compensation: In compliance with Massachusetts law, the anticipated annual base salary range for this position is $129,000 to $166,000. Please note that th

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