Marvell
Semiconductor
StaffEngineer,ASICDesign/ImplementationLEC/STA/PowerAnalysis
“Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis at Marvell. Skills: ASIC Design, STA, Timing Constraints, Power Analysis. Develop and validate timing constraints. Collaborate with Architecture, RTL, DFT, and Analog teams”
What You'll Achieve.
meeting performance, power and area goals
Industry & Context.
Excellent problem-solving skills; ability to analyze and debug complex issues
Access to technology and/or software subject to U.S. export control laws and regulations, Eligible to access export-controlled information
What They're Looking For.
Must Have
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience, Minimum of 1 year of industry experience in ASIC timing and STA, understanding of ASIC design flows, from RTL to GDSII, Knowledge and hands-on experience with STA methodologies and implementation, Proficiency in using STA tools, Proficiency in scripting languages (e.g., Tcl, Perl), Experience with high-complexity silicon in advanced technology nodes, understanding of timing constraint development for hierarchical designs, understanding of timing ECO creation, understanding of final timing signoff, Proven track record of delivering successful designs on time and meeting performance, power and area goals, Excellent problem-solving skills, attention to detail, ability to analyze and debug complex issues, communication and collaboration skills to work effectively within cross-functional teams
Nice to Have
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields, experience with deep technology nodes such as 5nm/4nm, preferably TSMC N4/N5, Familiarity with physical design and timing optimization techniques and strategies to achieve deterministic timing closure
What You'll Do.
Develop and validate timing constraints
Collaborate with Architecture
Own and contribute to STA tasks
Perform static timing analysis (STA)
Define and implement timing signoff methodologies
Resolve or find workarounds for tool issues
Conduct post-route timing checks
Automate STA related processes/flow
Create QoR dashboards
Ensure compliance with timing signoff checklists
Document best practices and lessons learned
How You'll Work.
Team & Collaboration
Collaborate with Architecture, RTL, DFT, and Analog teams; communication and collaboration skills to work effectively within cross-functional teams
Communication Scope
communication and collaboration skills
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