Sandisk
Technology
Technologist,ASICDevelopmentEngineering(STA,Sign-Off)
Neural analysis suggests this role is
optimal for mid candidates.
“Technologist, ASIC Development Engineering (STA, Sign-Off) at Sandisk. Skills: Static Timing Analysis, Timing signoff, STA methodology. Lead STA engineers. Observe ASIC timing signoff”
What You'll Achieve.
Deliver excellence timing closure; Enable consistent timing closure; Enable scalable timing closure; Optimize timing performance; Improve design performance
Industry & Context.
Mitigate timing violations; Improve design performance
What They're Looking For.
Must Have
Bachelor's or Master's degree, 13 years of experience, Proven leadership experience, Complete timing signoff ownership, Expert-level knowledge STA tools, Deep understanding timing concepts, Scripting expertise, Experience with automation frameworks, Exceptional leadership skills, People management skills, Excellent communication skills, Influence skills
Nice to Have
Experience with advanced process nodes
What You'll Do.
Observe ASIC timing signoff
Foster technical growth
Build high-performing organization
Deliver excellence timing closure
Architect STA methodology
Establish best practices
Establish signoff frameworks
Establish quality metrics
Enable scalable timing closure
Work with IP & Design
Develop timing constraints
Review timing constraints
Develop advanced STA methodologies
Implement advanced STA strategies
Meet timing closure requirements
Collaborate with cross-functional teams
Ensure seamless integration
Optimize timing performance
Conduct timing analysis
Identify critical paths
Develop strategies mitigate violations
Improve design performance
Stay abreast industry trends
Incorporate best practices
Prepare timing reports
Present technical documentation
Foster culture innovation
Foster culture collaboration
Foster culture continuous improvement
How You'll Work.
Team & Collaboration
Cross-functional teams; Design; Verification; Physical design; DFT
Communication Scope
Technical documentation; Timing reports
Full Job Description
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Position Overview: We are seeking an exceptionally skilled and strategic Technologist for our Static Timing Analysis (STA) function. The successful candidate will serve as a technical leader and subject matter expert, guiding a team of talented engineers and driving innovation in timing closure methodologies for our most complex semiconductor designs. This role demands deep expertise in STA, proven leadership in cross-functional collaboration, architectural thinking, and the ability to influence technical direction across multiple projects and organizations. Key Responsibilities: - Lead a team of talented STA engineers , observe complete ownership of ASIC timing signoff across , fostering technical growth, and building a high-performing organization capable of delivering excellence in timing closure for complex semiconductor designs. - Architect and define organization-wide STA metho
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