Astera Labs
AI infrastructure
TechnicalLeadDesignVerificationEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Technical Lead Design Verification Engineer at Astera Labs. Skills: System Verilog, UVM, C++, Python. contribute to functional verification. responsible for full life cycle of verification”
What You'll Achieve.
closing coverage; high quality tape-out
Industry & Context.
code breaker; problem-solving skills; debugging; bug and coverage hunting; debug failures; identify verification holes
Authorized to work in the US
What They're Looking For.
Must Have
academic and technical background in electrical engineering, Bachelor's in EE, ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications, Knowledge of industry-standard simulators, Knowledge of revision control systems, Knowledge of regression systems, Professional attitude, ability to prioritize a dynamic list of multiple tasks, work with minimal guidance and supervision, Entrepreneurial, open-minded behavior, can-do attitude, Think and act fast with the customer in mind, Authorized to work in the US, start immediately, full verification lifecycle based on System Verilog/UVM/C/C++, mix and deploy hybrid techniques, directed and constrained random, different ways to bug and coverage hunting, work independently to develop test-plans, develop related test-sequences to generate stimuli, work collaboratively with RTL designers to debug failures, Identify and write all types of coverage measures, Close coverage to identify verification holes
Nice to Have
Masters, Experience with System Verilog, Experience with C, Experience with C++, Experience with Python, Experience with other scripting languages, Experience in formal methods, Working experience with scripting tools (Perl/Python) to automate verification infrastructure, Prior experience using Verification IPs from 3rd party vendors, one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, Experience with directed test based methodologies, cache verification, formal methods
What You'll Do.
contribute to functional verification
responsible for full life cycle of verification
planning to writing tests
collect and closing coverage
work with software and system validation teams
come up with test plans
executing them in emulation platforms
develop related test-sequences
work collaboratively with RTL designers
Identify and write all types of coverage measures
Close coverage to identify verification holes
How You'll Work.
Team & Collaboration
collaborating with hyperscalers; collaborating with ecosystem partners; work with the software and system validation teams; work collaboratively with RTL designers
Process & Methodology
prioritize a dynamic list of multiple tasks
Full Job Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms. Basic qualifications Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred. ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and a
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