Nxp

Semiconductor

TechnicalDirector,SoCArchitect

Pune, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Director candidates.

The Brief

“Technical Director, SoC Architect at Nxp. Skills: SoC Architecture, Microarchitecture, Low-power design, Performance optimization. Define MCU SoC architectures. Drive architecture evolution”

What You'll Achieve.

Deliver competitive, production ready architectures; Enable scalable MCU products; Reduce program risk

Industry & Context.

Semiconductor

What They're Looking For.

Must Have

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, Proven experience in MCU SoC architecture, microarchitecture, RTL design, physical design, understanding of microprocessor and microcontroller architectures, CPU cores, interconnects, memory management, bus protocols, peripheral integration, Experience in low-power design, performance optimization, Familiarity with Ethernet, USB, SPI, I3C protocols, collaboration skills across silicon, hardware, and software teams

Nice to Have

Experience with ARM Cortex‑M architectures, Background in power and performance modeling, HW/SW co-design, debugging, Knowledge of functional safety and security standards, Familiarity with Wi‑Fi integration, networking protocols, secure wireless communication

What You'll Do.

Define MCU SoC architectures

Drive architecture evolution

Design multi-core compute architectures

Optimize SRAM hierarchy

Optimize interconnect bandwidth

Define security architecture

Integrate secure boot

Integrate root-of-trust

Integrate cryptographic acceleration

Ensure functional safety

Ensure lifecycle requirements

Ensure seamless integration

Optimize performance per watt

Support performance estimation

Support power estimation

Develop architecture specifications

Develop best practices

Develop technical documentation

How You'll Work.

Team & Collaboration

Work closely with SoC design teams; Work with system architects; Work with IP owners; Work with software architects; Collaborate with hardware teams; Collaborate with firmware teams; Collaborate with IP teams; Collaboration skills across silicon, hardware, and software teams

Full Job Description

**Role Overview** As an MCU SoC Architect, you will define and drive the architecture of next-generation microcontrollers. You will lead architectural decisions that balance real‑time determinism, performance, power efficiency, safety, and security, enabling scalable MCU products across industrial, automotive, and IoT markets. You will work closely with SoC design teams, system architects, IP owners, software architects, and product planning to deliver competitive, production ready architectures. This role requires deep expertise across MCU architectures, SoC integration, clock/reset/power design, memory subsystems, and microarchitectural trade‑offs, with a strong focus on real‑time and low‑power constraints. Join our team to build high‑performance, power‑efficient, and secure MCU architectures at NXP. **Key Responsibilities** * **Architecture Definition:** Lead the definition and evolution of MCU SoC architectures aligned with product strategy, market trends, and industry standards. * **Microarchitecture & Compute: **Design scalable and efficient multi-core compute architectures optimizing for TCMs, SRAM hierarchy, DMA, interconnect bandwidth. * **Security Architecture:** Define and integrate secure boot, root‑of‑trust, isolation, and cryptographic acceleration. Ensure architectures support functional safety and lifecycle requirements. * **SoC Integration:** Collaborate with hardware, firmware, and IP teams to ensure seamless integration of processing, memory, power management, peripherals, and interconnect subsystems. Good understanding of Analog IPs (ADC, DAC, PLL, SERDES etc.) will be required. * **Performance & Power Optimization: **Lead architectural strategies to optimize performance per watt. Balance frequency, voltage, memory, and power states to meet RT and MCX power envelopes. Support early performance and power estimation to reduce program risk. * **Technical Leadership & Documentation: **Develop architecture specifications, best practices, and technical

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