StaffSTAEngineer

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ## **Position Overview** We are seeking a highly skilled **Staff STA Engineer** to drive full‑chip timing closure across complex **SoC** and **analog/mixed‑signal (AMS)** integration projects. The ideal candidate will have deep expertise in static timing methodology, asynchronous clock domain interactions, analog–digital interface timing, and signoff flows. This role collaborates closely with **SoC digital design, physical design, analog IP designers, EDA vendors** , and cross‑functional engineering teams to ensure robust timing closure, silicon predictability, and first‑silicon success. ## **Key Responsibilities** ### **Static Timing Analysis & Signoff** * Own full‑chip **STA signoff** , including constraints development, timing setup, analysis, debugging, and closure at multiple PVT corners. * Develop, validate, and maintain **SDC constraints** , including false paths, multi‑cycle paths, generated clocks, and mode/corner definitions. * Perform timing correlation and optimization across **synthesis, APR (P &R)**, and signoff tools. * Analyze and resolve complex timing issues such as **cross‑clock domain timing** , hold/setup violations, and on‑chip variation. ### **Collaboration with SoC & Analog Teams** * Work closely with **SoC designers** to interpret timing architecture, pipeline strategies, clocking schemes, and interface timing budgets. * Partner with **analog/mixed‑signal design teams** to model analog–digital boundaries, including: * IO pad timing * PLL, DLL, ADC/DAC timing behavior * Level shifters, isolation cells * Custom timing arcs and Liberty model generation * Validate timing assumptions between analog and digital components and ensure signoff ali