Micron Technology
Semiconductor
StaffSoCDFTEngineer,HBM
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff SoC DFT Engineer, HBM at Micron Technology. Skills: SoC DFT, HBM, ASIC design. Own SoC-level DFT architecture. Own DFT implementation”
What You'll Achieve.
Enable manufacturability; Enable quality; Enable successful silicon bring-up
Industry & Context.
Problem-solving skills
What They're Looking For.
Must Have
7+ years SoC design experience, Bachelor's degree in EE/CE or related, Hands-on SoC DFT architecture experience, Experience with scan insertion, Experience with MBIST/LBIST concepts, Experience with boundary scan (JTAG), Experience with ATPG, Experience with full RTL-to-GDS flows, Experience collaborating with synthesis teams, Experience collaborating with STA teams, Experience collaborating with physical design teams, Proficiency with EDA tools (Siemens, Synopsys, Cadence)
Nice to Have
Experience with large, complex SoCs, RTL debugging skills, Design analysis skills, Problem-solving skills, Experience with Python scripting, Experience with Tcl scripting, Experience with Perl scripting, Ability to communicate clearly, Ability to collaborate effectively, Familiarity with DRAM, Familiarity with HBM, Familiarity with JEDEC specifications
What You'll Do.
Own SoC-level DFT architecture
Own DFT implementation
Define DFT architecture early
Drive DFT architecture alignment
Implement DFT logic at block level
Implement DFT logic at subsystem level
Implement DFT logic at full-chip level
Partner with RTL design teams
Partner with SoC integration teams
Collaborate with physical design teams
Optimize DFT solutions
Work with verification teams
Work with product engineering teams
Work with probe teams
Work with manufacturing teams
Ensure diagnosability
Ensure smooth pre-silicon debug
Ensure smooth post-silicon bring-up
Partner with CAD teams
Partner with methodology teams
Standardize DFT flows
Contribute to technical reviews
Drive innovation for future HBM generations
How You'll Work.
Team & Collaboration
Cross-group technical reviews; Global cross-functional teams
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. You will join an inclusive, innovation‑driven team focused on building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. Job Description ### Responsibilities will include, but are not limited to: * Own SoC‑level design for test (DFT) architecture and implementation, including scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST) where applicable, boundary scan (Joint Test Action Group, JTAG), and test access architectures for HBM base‑die designs. * Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. * Implement and integrate DFT logic at block, subsystem, and full‑chip levels while partnering closely with register‑transfer level (RTL) design and SoC integration teams. * Execute and sign off DFT flows, including linting, clock‑domain crossing (CDC) checks, DFT rule checks, automatic test pattern generation (ATPG) readiness, and coverage closure. * Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and design rule check/layout versus schematic (DRC/LVS) signoff. * Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, smooth pre‑silicon debug, and post‑silicon bring‑up. * Partner with computer‑aided design (CA
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