Astera Labs
Technology
Staff/PrincipalPhysicalDesignEngineer-SoCEMIRExpert
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff/ Principal Physical Design Engineer - SoC EMIR Expert at Astera Labs. Skills: SoC EMIR, Power integrity, Reliability targets. Take responsibility on IR drop analysis. Take responsibility on signal electromigration”
Industry & Context.
Root cause analysis
What They're Looking For.
Must Have
Bachelor's or Master's degree, 10+ years of hands-on experience, Proficiency in EMIR tools, Deep understanding of EM/IR challenges, Deep understanding of Place & Route flows, Ability to define EMIR methodologies, Capability to identify issues early
Nice to Have
Familiarity with thermal analysis tools, Experience with sign-off criteria, Good understanding of timing, Good understanding of packaging, Understanding of ESD, Understanding of latch-up, Reliability knowledge
What You'll Do.
Take responsibility on IR drop analysis
Take responsibility on signal electromigration
Take responsibility on power electromigration
Collaborate closely with Physical Design team
Insure a full power integrity
Be responsible on IR architecture
Partner with Package Design engineers
Perform Chip-Package co-analysis
Understand root-cause analysis for voltage drop violations
Understand risks for voltage drop
Be responsible for any IR related issues
Go-to person for any IR related issues
How You'll Work.
Team & Collaboration
Physical Design team; Package Design engineers
Full Job Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments. Key Responsibilities Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip Collaborate closely with Physical Design team to insure a full power integrity Be respon
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