Astera Labs
Technology
Staff/PrincipalArchitect
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff/ Principal Architect at Astera Labs. Skills: Connectivity solutions, AI infrastructure, PCIe architecture, High-speed networking. Define system architecture. Define chip-level architecture”
Industry & Context.
Problem-solving skills; Evaluate complex tradeoffs
What They're Looking For.
Must Have
10+ years semiconductor architecture, 10+ years ASIC design, 10+ years system engineering, PCIe architecture (Gen4/5/6+), Networking and Ethernet design, High-speed, low-latency data paths, SoC architecture and integration, Full chip development lifecycle, Analytical and problem-solving skills, Evaluate complex tradeoffs
Nice to Have
CXL experience, NVLink experience, UALink experience, Advanced interconnect protocols, AI/ML infrastructure background, Data center systems background, Hyperscaler environments background, SerDes-based systems experience, High-speed PHY integration, Networking stacks familiarity, Switching familiarity, RDMA technologies familiarity, Performance modeling tools knowledge, Architectural simulators knowledge, Power/performance optimization techniques, Drive architecture from concept to silicon
What You'll Do.
Define system architecture
Define chip-level architecture
Drive high-speed connectivity products
Lead PCIe interconnects architecture
Lead networking protocols architecture
Lead Ethernet subsystems architecture
Analyze system requirements
Translate requirements to architectures
Drive tradeoff analysis
Collaborate with cross-functional teams
Define micro-architecture specifications
Ensure alignment across teams
Contribute to standard-based protocols
Contribute to custom protocols
Support performance modeling
Support architectural validation
Work closely with customers
Work closely with partners
Build technical leadership
How You'll Work.
Team & Collaboration
Cross-functional teams; RTL teams; Physical Design teams; Firmware teams; Validation teams; Product Engineering teams; Customers and partners
Full Job Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview We are seeking an experienced Staff/ Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems. This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscal
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