Analog Devices
Semiconductor
StaffPhysicalVerificationEngineer
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“Staff Physical Verification Engineer at Analog Devices. Skills: Physical verification, DRC/LVS/PERC signoff, Advanced process nodes. Own full-chip and block-level physical verification signoff. Drive tape-out readiness”
What You'll Achieve.
Deliver clean GDS; Converge to zero/signoff-acceptable errors
Industry & Context.
Problem-solving skills; Debug skills; Root-cause analysis methodologies
10% travel
What They're Looking For.
Must Have
Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field, 8-12 years of experience in physical verification for complex ASIC/SoC designs, Several successful production tape-outs as signoff owner, Proven experience owning DRC/LVS/PERC signoff for at least one 5 nm (or sub-7 nm) production tape-out in a FinFET process, Deep hands-on expertise with industry-standard PV tools, Hands-on experience with Cadence Virtuoso-PV tool integration, Experience with advanced process nodes (5 nm and below), Proven track record in driving full-chip PV signoff, Solid scripting skills in Python, Perl, Tcl, or Unix shell, Experience with PERC-based reliability flows for ESD, EOS, LUP and current-density-based checks, Understanding of physical design and its interaction with PV signoff, Excellent problem-solving skills, Excellent debug skills, Excellent communication skills, Demonstrated ability to lead cross-functional technical closure
Nice to Have
Experience with FinFET process, Experience with digital-on-top, mixed-signal, or multi-voltage SoCs, Experience with hierarchical flows and IP integration, Familiarity with DFM/DFY checks, Familiarity with density/fill strategies, Familiarity with pattern-matching-driven rule decks
What You'll Do.
Own full-chip and block-level physical verification signoff
Drive tape-out readiness
Converge to zero/signoff-acceptable errors
and optimize PV flows and scripts
Define and enhance PERC and reliability rule checks
Own the floorplanning and power grid planning
Minimize PV iterations
Avoid late-stage violations
Own debugging of complex DRC/LVS/PERC violations
Partner with CAD teams to validate and qualify
Validate fill/DFM flows
Mentor junior engineers on PV best practices
Guide senior engineers on PV best practices
Mentor on root-cause analysis methodologies
Guide on signoff criteria
Act as primary technical interface to foundry
Act as primary technical interface to EDA vendors
Address PV and reliability issues
Address methodology improvements
How You'll Work.
Team & Collaboration
Working with Place-n-route teams; Working with analog/mixed-signal teams; Working with timing analysis teams; Working with CAD teams; Collaboration with reliability teams; Collaboration with I/O teams; Collaboration with analog teams; Cross-functional technical closure
Communication Scope
Communication skills
Process & Methodology
Manage PV schedules
Full Job Description
**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). **Role** We are seeking a Staff Physical Verification Engineer to own full-chip signoff for advanced SoC/ASIC designs, with end-to-end responsibility from block-level checks to final tape-out. You will lead methodologies and execution for DRC, LVS, PERC and related reliability checks, working closely with Place-n-route, analog/mixed-signal, timing analysis and CAD teams to ensure first-time-right silicon. **Key Responsibilities** \- Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs. \- Drive tape-out readiness: manage PV schedules, track violations, converge to zero/signoff-acceptable errors, and deliver clean GDS. \- Develop, maintain, and optimize PV flows and scripts (e.g., Calibre, ICV) for performance, robustness, and ease of use. \- Define and enhance PERC and reliability rule checks (ESD, EOS, EM-related constraints, point-to-point resistance, high current-density paths) in collaboration with reliability, I/O, and analog teams. \- Own the floorplanning and power grid planning to minimize PV iterations and avoid late-stage violations. \- Own debugging of complex DRC/LVS/PERC violations, including corner-case connectivity, device
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