Analog Devices
Semiconductor
StaffPhysicalDesignEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff Physical Design Engineer at Analog Devices. Skills: Physical Design, SoC Implementation, Technical Leadership. Own end-to-end physical implementation. Drive timing closure”
What You'll Achieve.
Achieve high-quality delivery; Achieve on-time delivery; Meet PPA targets; Meet quality targets
Industry & Context.
Problem-solving; Debugging; Scalable solutions; Automated solutions
10% travel
What They're Looking For.
Must Have
8-12+ years physical design experience, Hands-on PNR and signoff tools expertise, Closing challenging blocks/subsystems success, Floorplanning and partitioning strategies knowledge, Power grid and PDN methodology knowledge, Advanced clock tree/mesh design knowledge, STA constraints knowledge, Physical verification and reliability checks knowledge
What You'll Do.
Own end-to-end physical implementation
Address signal integrity
Perform physical verification
Define PNR strategies
Define IO ring/PG structures
Define integration guidelines
Perform in-depth analysis
Debug timing failures
Propose robust solutions
Propose scalable solutions
Develop physical design methodologies
Maintain physical design methodologies
Enhance physical design methodologies
Develop clock structure scripts
Develop exception handling scripts
Develop signoff automation scripts
Identify flow improvement opportunities
Identify standardization opportunities
Reduce turnaround time
Evaluate EDA tool features
Provide technical direction
Define quality expectations
Mentor junior engineers
Review implementation choices
Give actionable feedback
Act as technical reference
Work with packaging teams
Converge on architectures
Converge on constraints
Communicate trade-offs
Shape mitigation plans
Participate in design reviews
Participate in signoff reviews
Represent physical design status
Represent physical design risks
Represent physical design recommendations
How You'll Work.
Team & Collaboration
Cross-functional teams; CAD/enablement teams; RTL design teams; STA teams; DFT teams; CAD teams; Packaging teams; Project leads; Managers
Communication Scope
Explain technical issues; Explain options
Full Job Description
**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). **Role Overview** The Staff Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery. **Key Responsibilities** **Technical Ownership** Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm). Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets. Define and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs. Perform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions. **Methodology and Automation** Develop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation). Proactively identify opportunities for flow improvements and standardization to reduce turnaround
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