Micron Technology
Technology
StafflayoutEngineer–DPGLayout
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff layout Engineer – DPG Layout at Micron Technology. Skills: Layout implementation, AI automation, Physical verification. Own development and physical implementation. Own block-level and full-chip layout”
What You'll Achieve.
On-time delivery of layouts; Predictable quality; Risk mitigation plans; Improve yield
Industry & Context.
Physical verification; Debug; Layout optimization; Yield improvement
What They're Looking For.
Must Have
6+ years analog/custom layout design, Advanced CMOS technology nodes experience, Cadence Virtuoso (VLE/VXL) expertise, Calibre DRC/LVS expertise, Verification closure ownership, Analog block layout experience, Memory layouts experience, DRAM, SRAM, CAM, OTP understanding, Analog layout fundamentals understanding, Matching and symmetry knowledge, EM, latch-up, coupling, crosstalk knowledge, IR-drop, shielding, guard-ring knowledge, Parasitic effects knowledge, Interpret design intent and constraints, Translate intent into manufacturable layouts, AI-driven automation development experience, AI-assisted methodologies development experience, Complex layout workflows scaling experience, Physical verification problem-solving skills, Layout optimization problem-solving skills, Yield improvement problem-solving skills, B. Tech in Electronics, ECE, or VLSI
Nice to Have
M. Tech in VLSI Design, Microelectronics, or EE
What You'll Do.
Own development and physical implementation
Own block-level and full-chip layout
Lead layout implementation using AI-assisted workflows
Apply copilot-based assistants
Apply agentic AI flows
Apply rule-aware automation
Accelerate optimization
Automate layout verification activities
Perform layout verification activities
Drive on-time delivery of layouts
Develop AI-enabled methodologies
Deploy AI-enabled methodologies
Automate floorplanning
Automate parasitic estimation
Automate layout consistency checks
Automate best-practice enforcement
Eliminate repetitive layout tasks
Demonstrate technical leadership
Guide engineers in Analog layout fundamentals
Guide engineers in Automation-first approach
Guide engineers in Design-for-quality
Guide engineers in design-for-yield
Mentor engineers in Analog layout fundamentals
Mentor engineers in Automation-first approach
Mentor engineers in Design-for-quality
Mentor engineers in design-for-yield
Collaborate with Design teams
Collaborate with CAD teams
Collaborate with Verification teams
Collaborate with Reliability teams
Collaborate with Program Management teams
Communicate technical risks
Communicate schedule impacts
Communicate optimization opportunities
Drive continuous improvement
Identify manual bottlenecks
Convert bottlenecks into automated flows
How You'll Work.
Team & Collaboration
Design teams; CAD teams; Verification teams; Reliability teams; Program Management teams
Process & Methodology
Planning, Delegation, Execution
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description **Role and Responsibilities** * Own the development and physical implementation of critical analog, mixed‑signal, and custom digital blocks, including block‑level and full‑chip layout ownership. * Lead layout implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization. * Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks. * Drive on‑time delivery of blocks and partition‑level layouts with predictable quality and risk prediction/mitigation plans. * Develop and deploy AI‑enabled methodologies for Semi-automated floorplanning, parasitic estimation, layout consistency checks and best‑practice enforcement, repetitive layout task elimination via SKILL, Python, TCL or agent‑based flows. * Demonstrate technical leadership in planning, area and cycle‑time estimation, delegation and execution. * Guide and mentor engineers in Analog layout fundamentals, Automation‑first approach, Design‑for‑quality and design‑for‑yield practices * Collaborate closely with Design, CAD, Verification, Reliability, and Program Management teams, clearly communicating technical risks, schedule impacts and any optimization opportunities. * Drive continuous improvement by identifying manual bottlenecks and converting them into scalable automated flows. **Job Requirements** * 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes. * Strong expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands‑on ownership of verification closure. * Pro
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