Micron Technology
Semiconductor
StaffHBMDesignArchitect-DFT
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff HBM Design Architect - DFT at Micron Technology. Skills: HBM Design, DFT Architecture, Memory Products. Define DFT architectures. Implement DFT architectures”
What You'll Achieve.
Ensure quality; Ensure yield; Ensure performance
Industry & Context.
Debug; Failure analysis
What They're Looking For.
Must Have
Bachelor's or Master's degree in EE or CE, Knowledge of scan, MBIST, JTAG, boundary scan, Experience with wafer probe and final test flows, 5+ years of experience in DRAM or ASIC DFT
Nice to Have
Experience with HBM, DRAM, or advanced memory, Knowledge of TSV-based 3D integration, Knowledge of stacked-die test challenges, Hands-on experience with at-speed test, Hands-on experience with advanced DFT techniques, Exposure to DFT security features, Exposure to custom customer test interfaces
What You'll Do.
Define DFT architectures
Implement DFT architectures
Develop DFT strategies
Architect test access mechanisms
Enable silicon observability
How You'll Work.
Team & Collaboration
Design teams; Verification teams; Layout teams; Test teams; Manufacturing teams
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. **Responsibilities:** * Define and implement end-to-end DFT architectures for HBM base die and DRAM die * Develop DFT strategies for stacked-die, cube-level, and system-level test flows * Architect test access mechanisms supporting wafer probe through final test * Enable silicon observability for yield learning, debug, and failure analysis * Collaborate across design, verification, layout, test, and manufacturing teams **Minimum Qualifications:** * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field * Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts * Experience with wafer probe and final test semiconductor flows * 5+ years of experience in DRAM or ASIC DFT design or verification **Preferred Qualifications:** * Experience with HBM, DRAM, or advanced memory products * Knowledge of TSV-based 3D integration and stacked-die test challenges * Hands-on experience with at-speed test or advanced DFT techniques * Exposure to D
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