Micron Technology
Technology
StaffEngineer-StandardCellDesign
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff Engineer - Standard Cell Design at Micron Technology. Skills: Standard Cell Design, CMOS Circuit Design, AI-based automation. Design standard cells for new DRAM products. Maintain standard cells for new DRAM products”
What You'll Achieve.
Improve work efficiency; Help data analysis; Improve stdcells design productivity; Improve stdcells char productivity
Industry & Context.
Identify stdcells design pain points; Identify stdcells char pain points
What They're Looking For.
Must Have
7+ years of relevant experience, Bachelor's or Post Graduate Degree in Electronics Engineering or related engineering field, Good understanding of CMOS circuit design, Good knowledge of CMOS device physics and layout, Experience in total stdcells flow from DTCO development/ spec definition till lib release, RTL/GDS flow setup, Block level timing analysis, ICC2 experience, Finefet & planner experience required, Experience in Standard Cell design, layout and verification, Experience in Skill, TCL, Perl, Python to do test bench automation and data analysis, Experience using AI-assisted tools to improve stdcells design & char productivity
Nice to Have
Synopsys EDA flow preferred, Experience in any characterization tools (Siliconsmart/Liberate) and Cadence Virtuoso preferred, Experience in Primetime, Solido Analytics, Familiar with analog/digital simulation tools, Previous work experience in DRAM memory related fields or analog blocks is a plus
What You'll Do.
Design standard cells for new DRAM products
Maintain standard cells for new DRAM products
Collaborate with DTCO team to develop stdcells architecture
Characterize standard cells
Analyze quality of characterized liberty models
Develop automation test bench
Develop automation flow
Develop automation tools
Improve work efficiency
Co-work with international colleagues
Develop new flows for stdcells design
Develop new tools for stdcells design
Identify stdcells design pain points
Identify stdcells char pain points
Deploy scalable solutions using AI-based automation
How You'll Work.
Team & Collaboration
DTCO team; International colleagues; Cross-functional teams
Communication Scope
Interpersonal skills; Communication skills
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Responsibilities** * Design and maintain standard cells for new DRAM products on new technology * Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies * Characterization and modeling of Standard cells to provide timing/power model * Quality Analysis of characterized liberty models in terms of performance, Power and Functionality * Develop automation test bench/flow/tools to improve the work efficiency and help data analysis * Co-work with international colleagues on developing new flows and tools for stdcells design * Ability to identify stdcells design & char pain points suitable for **AI-based automation** and collaborate with cross‑functional teams to deploy scalable solutions. **Requirements** * Good understanding of CMOS circuit design * Good knowledge of CMOS device physics and layout * Experience in total stdcells flow from DTCO development/ spec definition till lib release * RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow * Finefet & planner experience required. * Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. * Experience in Primetime, Solido Analytics * Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision * Experience in Standard Cell design, layout and verification * Experience in Skill, TCL, Perl, Python to do test bench automation and data analysis * Previous work experience in DRAM memory related fields or analog blocks is a plus * Good interpersonal & communication skills and ability to work well in a team * Experience using **AI-assisted tools** to improve stdcells des
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