OLIX
AI
StaffEngineer(HeterogeneousIII-V/SiliconIntegration)
Neural analysis suggests this role is
optimal for Lead candidates.
“Staff Engineer (Heterogeneous III-V / Silicon Integration) at OLIX. Skills: III-V VCSEL arrays, Silicon integration, Epitaxial design, Heterogeneous integration. Drive integration strategy. End-to-end development”
What You'll Achieve.
ensure integrated arrays deliver required bandwidth density, power efficiency, and yield; yield ramps; SPC
Industry & Context.
Solve scaling problems specific to large arrays
£24k annual Living-Local Bonus if residence is within 20 minutes of the office, Visa Sponsorship, Relocation support
What They're Looking For.
Must Have
7+ years in compound-semiconductor optoelectronics, Degree in Physics, EE, Materials Science, or related, Solid understanding of III-V materials systems (GaAs/AlGaAs, InP-based) and their Si integration constraints, Hands-on with one or more III-V/Si integration approaches: wafer bonding, micro-transfer printing, flip-chip on PIC, or direct epi of III-V on Si, Working knowledge of MBE/MOCVD and how epi design choices propagate into integration yield, Familiarity with high-speed modulation, bandwidth limitations, and electrical parasitics in heterogeneously integrated systems, Experience working with external foundries, epi suppliers, or integration partners, Able to interpret SEM, AFM, TEM, and bonded-interface characterisation data, cross-functional collaboration
Nice to Have
Silicon photonic platforms and CMOS process flows, Reliability standards for datacom / compute-class optical interconnect (Telcordia, JEDEC), Integrating lasers with custom driver ASICs at die or wafer level, Yield optimisation, SPC, and DoE for integrated optoelectronic processes, Thermal management and thermo-mechanical stress in dense laser arrays on dissimilar substrates, Python
What You'll Do.
Drive integration strategy
End-to-end development
Define and optimise epitaxial designs
Develop and qualify bonding processes
Partner with modelling
Characterise integrated devices
Solve scaling problems
Interface with packaging
Establish reliability methodologies
Contribute to roadmaps
Support transfer to manufacturing
How You'll Work.
Team & Collaboration
working closely with ASIC, electronics, packaging, and system architecture teams; cross-functional collaboration; speak to silicon, packaging, and ASIC teams
Communication Scope
speak to silicon, packaging, and ASIC teams in their own language
Full Job Description
ABOUT OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance. THE ROLE We are seeking highly skilled and motivated Staff Engineer to lead heterogeneous integration of III-V VCSEL arrays with silicon for our DX-1 accelerator. The role spans epitaxial design through to wafer/die-level integration with silicon substrates and driver ICs, taking large-format VCSEL arrays from process development into volume production. Covers device physics, integration process development, and system-level co-design, working closely with ASIC, electronics, packaging, and system architecture teams to ensure integrated arrays deliver the required bandwidth density, power efficiency, and yield. RESPONSIBILITIES - Drive integration strategy for III-V VCSEL arrays onto silicon (flip-chip, micro-transfer printing, wafer/die bonding, direct epitaxy) - End-to-end development of large-format VCSEL arrays from epi structure through to integrated, tested modules - Define and optimise epitaxial designs (quantum wells, DBRs, oxide/current confinement) with III-V/Si integration as a first-class constraintSpecify wafer growth, fab, and integration flows with external epi houses, III-V foundries, and silicon partners - Develop and qualify bonding, micro-transfer printing, alignment, and underfill processes at array scalePartner with modelling on thermal and thermo-mechanical
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