Samsung Semiconductor
Semiconductor
StaffEngineer,FPGA
“Staff Engineer, FPGA at Samsung Semiconductor. Skills: FPGA, RTL Design, SystemVerilog, Verilog, CXL, PCIe, AMBA, Cache Coherency. Develop and optimize RTL (SystemVerilog/Verilog) IPs for CXL Type-2 FPGAs. Focus on the CXL. cache controller, command queues and DMA management”
What You'll Achieve.
Design and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance; Ensure that our platforms are always equipped to handle the most demanding workloads of the future; Revolutionize the way AI/ML applications are deployed and executed; Contribute to the advancement of AGI in an affordable and sustainable manner
Industry & Context.
Solving the complex system-level challenges posed by the growing demands of future AI/ML workloads; Analytical and troubleshooting skills to resolve complex hardware bottlenecks
Daily onsite presence at our San Jose, CA office / U. S. headquarters in alignment with our Flexible Work policy
What They're Looking For.
Must Have
Bachelor's with 10+ years, or Master's with 8+ years, or PhD's with 5+ years of industry experience, BS/MS in Electrical Engineering, Computer Engineering, or related field with 3-5+ years of industry experience in FPGA development, Expertise in SystemVerilog, Verilog, Knowledge of computer architecture, Knowledge of memory coherency, Knowledge of data structures fundamentals, Deep understanding of AMBA (AXI/AXIS), Deep understanding of PCIe, Deep understanding of CXL. cache protocols, Deep understanding of CXL Type-1/2 devices
Nice to Have
Portfolio in high-performance digital design, Prior experience in designing coherent memory systems, Prior experience in control path design for accelerators
What You'll Do.
Develop and optimize RTL (SystemVerilog/Verilog) IPs for CXL Type-2 FPGAs
Focus on the CXL. cache controller
command queues and DMA management
cache-line-granular command queue interfaces
Implement hardware mechanisms to maintain coherent access between host CPU and FPGA
Optimize RTL to meet strict latency and bandwidth requirements
Manage memory access patterns and improve the pipeline for high-speed operations
Collaborate with software engineers to integrate with kernel drivers and user-space libraries
Debug complex RTL-to-Host issues in a laboratory environment
Develop SystemVerilog testbenches and simulation models to verify protocol compliance and functional correctness
How You'll Work.
Team & Collaboration
Collaborate closely with both hardware and software engineers; Collaborate with software engineers to integrate with kernel drivers and user-space libraries; Ability to thrive in a collaborative, multi-disciplinary environment
Communication Scope
Excellent verbal and written communication skills
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