Butterfly Network
Healthcare
StaffEngineer,DigitalASICDesign(CONTRACT)
“Staff Engineer, Digital ASIC Design (CONTRACT) at Butterfly Network. Skills: Digital ASIC Design, RTL Design, SoC Design, Verification Closure. Design RTL for large SoCs. Develop low-power RTL”
Industry & Context.
Root-cause issues; Troubleshooting
What They're Looking For.
Must Have
BS/MS/PhD in EE/CE, 8+ years digital IC/ASIC/SoC design, Hands-on RTL ownership, Major-IP or full-chip tapeout cycle, IP/subsystem ownership, Micro-architecture and RTL implementation, Verification closure and tapeout support, RTL skills in SystemVerilog/Verilog, Pipelined datapaths, Control logic/state machines, High-throughput streaming interfaces, Sustained high-throughput datapaths, Buffering/FIFOs, Arbitration/ack/pressure, Bandwidth budgeting, SRAM/memory interface considerations, Silicon-level design constraints, Clock/reset architecture, CDC/RDC risk mitigation, Power-aware design, PPA tradeoffs, Collaboration with verification, Functional closure through signoff, Bit-accurate reference models, Python for reference models, Validate fixed-point behavior, End-to-end checking, Post-silicon bring-up/debug, Silicon correlation, Root-cause issues and deliver fixes, Cross-functional communication, Close hardware–firmware interfaces, Register maps, Control/status paths, Data-plane contracts
Nice to Have
Compute-intensive DSP pipelines, Beamforming, Filtering, Noise reduction, MAC-heavy datapaths, Fixed-point design discipline, Ultrasound systems, Medical imaging systems, Sensor data acquisition pipelines, Image-quality KPIs, Advanced-node experience (28nm or smaller), Timing sensitivity, Third-party IP integration, Programmable compute subsystems integration, MPU/accelerator integration, Control interfaces, Memory/bandwidth tradeoffs
What You'll Do.
Design RTL for large SoCs
Develop low-power RTL
Implement signal processing algorithms in RTL
Optimize signal processing algorithms in RTL
Integrate embedded processor cores
Develop high bandwidth on chip data paths
Support post-silicon bring-up/debug
Support silicon correlation
Close hardware–firmware interfaces
Define control/status paths
Define data-plane contracts
How You'll Work.
Team & Collaboration
Collaboration with verification; Cross-functional communication; Partnering with firmware; Partnering with validation; Stakeholder communication
Communication Scope
Cross-functional communication
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