Tenstorrent
AI technology
StaffEngineer,CPUCoreVerification
Neural analysis suggests this role is
optimal for Staff candidates.
“Staff Engineer, CPU Core Verification at Tenstorrent. Skills: CPU core verification, RISC-V CPU microarchitecture, UVM, C/C++ based stimulus, debug. Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components”
Industry & Context.
solving hard problems; debug simulation and emulation regressions; identify and resolve issues efficiently
eligibility to access U. S. export-controlled technology, compliance with U. S. export laws (EAR), citizenship/permanent residency status or ability to obtain prior license approval from the U. S. Commerce Department or applicable federal agency
What They're Looking For.
Must Have
8+ years in CPU verification or closely related digital design, Knowledge of high‑performance out‑of‑order CPU microarchitecture in depth, Comfortable with RTL, waveforms, logs, and complex debug scenarios, Ability to communicate clearly across design, DV, emulation, and post‑silicon teams
What You'll Do.
Plan and drive functional verification for CPU core features and complex microarchitectural scenarios
and C/C++ based stimulus
and un-core components
Debug simulation and emulation regressions using RTL understanding
and logs to identify and resolve issues efficiently
Build and enhance coverage models
and debug infrastructure to improve verification quality and coverage closure
Collaborate with design
and test teams to support bring-up and delivery of robust CPU cores and clusters
How You'll Work.
Team & Collaboration
Communicate clearly across design, DV, emulation, and post‑silicon teams; Collaborate with design, validation, and test teams to support bring-up and delivery of robust CPU cores and clusters
Communication Scope
communicate clearly across design, DV, emulation, and post‑silicon teams
Process & Methodology
Plan and drive functional verification
Full Job Description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and test teams to support
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