Micron Technology
Technology
StaffEngineer,ASICSTA
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff Engineer, ASIC STA at Micron Technology. Skills: ASIC STA, Synthesis, Timing closure, Low power design. Perform block level low power aware floorplanning. Perform placement”
Industry & Context.
Timing closure; Resolving Constraint Conflicts; Low power Intent verification
What They're Looking For.
Must Have
8-14 years relevant experience, Good understanding of overall design Flow RTL to GDS, Hands on Experience on Constraints Generation, timing closure, Hand on Synthesis & STA Experience on Lower node Technologies, Hands on Experience on Equivalent Checks, Good knowledge on Timing Budgets, Experience on multi voltage designs using CPF/UPF, Hands on experience on power analysis using PTPX, Good understanding of VHDL / Verilog Constructs
Nice to Have
Formal verification experience, Digital electronics experience, Microprocessors experience
What You'll Do.
Perform block level low power aware floorplanning
Perform clock tree synthesis
Perform RC extraction
Perform STA timing closure
Perform tape out activities
Synthesize blocks/chips to achieve best PPA
Generate Constraints & Timing closure for Block and
Resolve Timing Convergence & Constraint Conflicts
Work on low power Intent
Verify low power intent
Perform Logical equivalence checks
Perform Low Power Checks
Perform Early RTL analysis for Clocking
Provide suggestions to Designer on improvements
Support Verification team to enable GLS
How You'll Work.
Team & Collaboration
Interaction with Design teams; Interaction with DFT teams; Interaction with IP&PD teams
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.** # **_Role:_** The team member will typically work on processors, controller architectures or ASICs for Enterprise SSD Group. Should be proficient in block level low power aware floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tape out activities. Requirements _**Skills Required**_ * 8-14 years of relevant experience in Synthesis/STA * Good understanding of overall design Flow RTL to GDS. * Hands on Experience on Constraints Generation, timing closure of full chip on Hierarchical Designs * Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools. * Hands on Experience on Equivalent Checks with Synopsys / Cadence Tools. * Good knowledge on Timing Budgets. * Knowledge on Perl / TCL / Python scripting language * Experience on multi voltage designs using CPF/UPF. * Hands on experience on power analysis using PTPX * Good understanding of VHDL / Verilog Constructs. _**Responsibilities**_ * Responsible for Block/ Chip Tile Synthesis to achieve the best PPA. * Constraint Generation & Timing closure for Block and Full Chip SOC for complex hierarchical Designs for all the Modes. * Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts . * Able
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