Micron Technology
Technology
StaffEngineer,ASICPhysicalDesign
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff Engineer, ASIC Physical Design at Micron Technology. Skills: Physical Design, ASIC, STA Timing Closure, Physical Verification. Work on processors. Work on controller architectures”
Industry & Context.
Analytical skills; Problem-solving skills
What They're Looking For.
Must Have
8 years physical design implementation, APR flow development, PPA analysis, STA closure at block, Physical verification closure, DRC/LVS/Antenna closure, Closing IR issues, Fundamentals of digital electronics, Fundamentals of microprocessors, English language proficiency
Nice to Have
Masters degree, Strong verbal communication skills, Cadence PnR tools, Formal verification experience
What You'll Do.
Work on controller architectures
Perform block level low power aware floorplanning
Perform clock tree synthesis
Perform RC extraction
Perform STA timing closure
Perform tape out activities
How You'll Work.
Team & Collaboration
Good collaboration; Interpersonal skills
Communication Scope
English language proficiency
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.** # **_Role:_** The team member will typically work on processors, controller architectures or ASICs for Enterprise SSD Group. Should be proficient in block level low power aware floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tape out activities. Requirements * **Minimum of 8 years** of hands-on physical design implementation experience along with APR flow development and PPA analysis * STA closure at block * Experience in Advanced process technology nodes (5nm/3nm preferred) * Experience with Cadence layout tools (**Innovus, Tempus** , etc..) * Hands on work experience in Physical verification closure (DRC/LVS/Antenna) with **Caliber tool** * Experience in closing all the IR issues within the block based on feedback * Should be strong in fundamentals of digital electronics and microprocessors * Should have very good analytical skills * Required soft skills – English language proficiency, Good collaboration and interpersonal skills. Good analytical and Problem-solving skills along with strong ownership, commitment and time management. * Bachelor’s or Masters with a relevant education is in the field of electronics and computer architecture **Preferred Skills:** ·Strong verbal communication skills ·Cadence Pn
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