E-Space
Tech / AI / Software
StaffDVEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff DV Engineer at E-Space. Skills: Verilog, SystemVerilog, UVM, Digital Design Verification. verify our custom ASICs for satellite and wireless telephony. write tests within an existing UVM verification environment”
What You'll Achieve.
make connectivity from space universally accessible, secure and actionable; enable hyper-scaled deployments of Internet of Things (IoT) solutions and services; fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems; deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life; create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet
Industry & Context.
Ability to debug RTL simulations independently
extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals, candidates who do not hold work authorization for the location of this role
What They're Looking For.
Must Have
Proficiency in Verilog and SystemVerilog, Experience writing tests within an existing UVM verification environment, Solid understanding of UVM architecture and methodology, Ability to write C/C++ code for verification purposes, Some scripting experience in Perl or Python, Ability to contribute to and help write test plans, Experience writing and maintaining verification tests, Ability to debug RTL simulations independently, Experience leading design verification efforts at the block level, Experience driving code coverage closure on assigned blocks, 6+ years of design verification experience in the semiconductor industry
Nice to Have
VHDL is valuable, AI assistance to accelerate work
What You'll Do.
verify our custom ASICs for satellite and wireless telephony
write tests within an existing UVM verification environment
write C/C++ code for verification purposes
scripting experience in Perl or Python
contribute to and help write test plans
write and maintain verification tests
debug RTL simulations independently
lead design verification efforts at the block level
drive code coverage closure on assigned blocks
How You'll Work.
Team & Collaboration
Experience leading design verification efforts at the block level
Full Job Description
## Description Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work. ## Requirements HDL & Verification Methodology · Strong proficiency in Verilog and SystemVerilog · Experience writing tests within an existing UVM verification environment · Solid understanding of UVM architecture and methodology Programming & Scripting · Ability to write C/C++ code for verification purposes · Some scripting experience in Perl or Python Verification Planning & Execution · Ability to contribute to and help write test plans · Experience writing and maintaining verification tests · Ability to debug RTL simulations independently Leadership · Experience leading design verification efforts at the block level · Experience driving code coverage closure on assigned blocks ## What you bring to this role 6+ years of design verification experience in the semiconductor industry ## Additional Information This is a full time, exempt position, based out of our Saratoga office. The target base pay for this position is $120,000 - $220,000 annually. The total compensation packaged will be determined by various
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