Renesas Electronics
Technology
StaffDFTEngineer
Neural analysis suggests this role is
optimal for mid candidates.
“Staff DFT Engineer at Renesas Electronics”
Industry & Context.
Full Job Description
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. We are looking for a digital design engineer with DFT capabilities ## Qualifications 1. Experience: 5+ years of hands-on experience in DFT architecture and implementation for SoC/ASIC. 2. Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST. 3. Experience in creating and implementing hierarchical DFT architecture in complex SoC. 4. Experience in Low-Power DFT and MBIST. 5. Experience in test time and test coverage analysis for scan and MBIST patterns. 6. Experience in working with test engineering team to bring up production test program. 7. Extensive knowledge of timing concepts and constraint development. 8. Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environm
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