Analog Devices
Semiconductor
StaffDFTEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff DFT Engineer at Analog Devices. Skills: DFT strategy, SoC execution, ATPG, Test quality. Own DFT strategy for complex SoCs. Define DFT architecture”
What You'll Achieve.
Achieve high fault coverage; Minimize pattern count; Improve yield; Improve test robustness
Industry & Context.
Problem-solving; Troubleshoot; Resolve complex DFT issues
10% travel
What They're Looking For.
Must Have
7+ years of hands-on experience in DFT, Bachelor's or Master’s degree in Electrical/Electronics Engineering, Proven experience in leading DFT teams, Demonstrated expertise in developing DFT architecture, team management and leadership experience
Nice to Have
Experience with high-volume production test, Exposure to safety-critical applications, Experience with on-chip debug, Prior experience mentoring or leading small DFT teams
What You'll Do.
Own DFT strategy for complex SoCs
Define DFT architecture
Define scan strategies
Define compression strategies
Define LBIST strategies
Define MBIST strategies
Define boundary scan strategies
Define test access strategies
Drive testability requirements
Balance coverage tradeoffs
Balance test time tradeoffs
Balance power tradeoffs
Balance area tradeoffs
Balance schedule tradeoffs
Execute scan insertion
Lead test compression
Execute test compression
Lead pattern optimization
Execute pattern optimization
Generate ATPG patterns
Analyze ATPG patterns
Optimize ATPG patterns
Achieve high fault coverage
Minimize pattern count
Review fault coverage reports
Sign off fault coverage reports
Review pattern volume
Sign off pattern volume
Diagnose coverage holes
Drive methodology fixes
Support first silicon bring-up
Support failure analysis
Debug tester-related failures
Collaborate with ATE teams
Collaborate with manufacturing teams
Improve test robustness
Drive ECOs for DFT issues
Act as DFT technical lead
Guide junior DFT engineers
Review junior DFT engineers work
Guide senior DFT engineers
Review senior DFT engineers work
Define best practices
Define reusable DFT methodologies
Provide technical direction
Conduct design reviews
Work closely with RTL designers
Work closely with Physical Design
Work closely with Functional Verification
Work closely with Product Engineering
Work closely with Manufacturing
Communicate DFT requirements
Communicate DFT risks
How You'll Work.
Team & Collaboration
Cross-functional teams; Cross-functional collaboration; Team-oriented environments
Communication Scope
Communicate requirements; Communicate risks
Full Job Description
**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). We are seeking a **Staff DFT Engineer** who can **own and drive the complete DFT strategy for complex SoCs** from architecture through production silicon. This role requires deep hands-on expertise, strong technical judgment, and the ability to **lead and mentor junior engineers** while collaborating cross-functionally with design, PD, validation, and manufacturing teams. The ideal candidate operates independently, makes architecture-level decisions, and is accountable for **test quality, coverage, and silicon readiness**. **Responsibilities:** **DFT Architecture & Planning** * Own DFT architecture definition at chip and subsystem level * Define scan, compression, LBIST, MBIST, boundary scan, and test access strategies * Drive testability requirements early in the RTL design phase * Balance coverage, test time, power, area, and schedule tradeoffs **DFT Implementation (End-to-End Ownership)** * Lead and execute: * Scan insertion, stitching, and DRC closure * ATPG (stuck-at, transition, path delay) * Test compression and pattern optimization * Own DFT signoff including coverage, IR drop, power, and timing impacts * Debug and resolve DFT issues across RTL, synthesis, P&R, and gate-level stages **ATPG & Test Quality** * Genera
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