Analog Devices

semiconductor

StaffDFTEngineer

$0–0k Bangalore, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Lead candidates.

The Brief

“Staff DFT Engineer at Analog Devices. Skills: DFT Architecture, ATPG, SoC DFT. Own DFT architecture definition. Define scan, compression, LBIST, MBIST strategies”

Industry & Context.

semiconductor
Problems you'll solve

Excellent problem-solving skills; Troubleshoot and resolve complex DFT issues efficiently

Eligibility Requirements

Travel: Yes, 10% of the time, Export licensing review process may apply

What They're Looking For.

Must Have

Proven experience in leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up, Demonstrated expertise in developing DFT architecture from scratch for complex SoC designs, team management and leadership experience with a track record of mentoring and growing engineering talent, 7+ years of hands-on experience in DFT methodologies and industry-standard test techniques, Deep knowledge and hands-on experience with: Logic BIST (LBIST), Deep knowledge and hands-on experience with: Automatic Test Pattern Generation (ATPG), Deep knowledge and hands-on experience with: DFT Rule Checks (DFT DRC), Deep knowledge and hands-on experience with: Scan chain compression and stitching, Deep knowledge and hands-on experience with: Low-power DFT techniques and constraints, Deep knowledge and hands-on experience with: Memory BIST (MBIST) including repair mechanisms, Deep knowledge and hands-on experience with: Boundary Scan (IEEE 1149.1), Deep knowledge and hands-on experience with: Analog DFT strategies, Deep knowledge and hands-on experience with: JTAG architecture and TAP integration, Deep knowledge and hands-on experience with: DFT-specific STA constraints, Proficient in using industry-standard DFT EDA tools, including cadence, Siemens, scripting and automation skills using Perl, Tcl, and/or Python, Solid understanding of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow, Excellent problem-solving skills, with the ability to troubleshoot and resolve complex DFT issues efficiently, communication and interpersonal skills, capable of working effectively in cross-functional and team-oriented environments

Nice to Have

Experience with high-volume production test, ATE bring-up, and test cost optimization, Exposure to safety-critical applications (automotive, industrial) and standards (e. g. , ISO 26262) from a test/reliability standpoint, Experience with on-chip debug, trace, and design-for-debug features, Scripting skills in Python/Tcl/Perl for DFT automation, log analysis, and flow integration, Prior experience mentoring or leading small DFT teams or task forces

What You'll Do.

Own DFT architecture definition

Drive testability requirements

Lead and execute scan insertion

Lead and execute ATPG

Lead and execute test compression

Debug and resolve DFT issues

optimize ATPG patterns

Achieve high fault coverage

Review fault coverage reports

Review pattern volume and test time

Diagnose coverage holes

Support first silicon bring-up

Support failure analysis

Collaborate with ATE and manufacturing

Drive ECOs for DFT issues

Act as DFT technical lead

Guide and review junior engineers

Define best practices

Define reusable DFT methodologies

Provide technical direction

Conduct design reviews

How You'll Work.

Team & Collaboration

Collaborating cross-functionally with design, PD, validation, and manufacturing teams; Work closely with RTL designers; Work closely with Physical design (PD); Work closely with Functional verification; Work closely with Product engineering and manufacturing; Communicate DFT requirements and risks clearly to stakeholders; Work effectively in cross-functional and team-oriented environments

Communication Scope

Communicate DFT requirements and risks clearly to stakeholders; Excellent communication and interpersonal skills

Full Job Description

**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). We are seeking a **Staff DFT Engineer** who can **own and drive the complete DFT strategy for complex SoCs** from architecture through production silicon. This role requires deep hands-on expertise, strong technical judgment, and the ability to **lead and mentor junior engineers** while collaborating cross-functionally with design, PD, validation, and manufacturing teams. The ideal candidate operates independently, makes architecture-level decisions, and is accountable for **test quality, coverage, and silicon readiness**. **Responsibilities:** **DFT Architecture & Planning** * Own DFT architecture definition at chip and subsystem level * Define scan, compression, LBIST, MBIST, boundary scan, and test access strategies * Drive testability requirements early in the RTL design phase * Balance coverage, test time, power, area, and schedule tradeoffs **DFT Implementation (End-to-End Ownership)** * Lead and execute: * Scan insertion, stitching, and DRC closure * ATPG (stuck-at, transition, path delay) * Test compression and pattern optimization * Own DFT signoff including coverage, IR drop, power, and timing impacts * Debug and resolve DFT issues across RTL, synthesis, P&R, and gate-level stages **ATPG & Test Quality** * Genera

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