Micron Technology
Semiconductor
StaffDesignVerificationEngineer,HBMArchitecture
Neural analysis suggests this role is
optimal for Senior candidates.
“Staff Design Verification Engineer, HBM Architecture at Micron Technology. Skills: HBM Architecture, Design Verification, Memory Solutions. Deliver verification plans. Deliver architecture collateral”
Industry & Context.
Analyze bottlenecks; Identify root causes
What They're Looking For.
Must Have
Bachelor's degree or higher, 7+ years verification engineering experience, 5+ years digital, analog, or mixed-signal verification, 4+ years custom design verification or RTL design verification, Define and drive verification strategies, Verbal and written communication skills
Nice to Have
Master's degree or equivalent experience, 9+ years verification engineering roles, One or more patents, trade secrets, or publications, 4+ years memory products using JEDEC specifications, Hands-on experience building verification flows
What You'll Do.
Deliver verification plans
Deliver architecture collateral
Develop turnkey solutions
Drive co-verification
Mentor early-career engineers
Build verification methodology improvements
Build GenAI applications
Debug pre-silicon issues
Debug post-silicon issues
Explore new architectures
Conduct feasibility analyses
How You'll Work.
Team & Collaboration
Multi-functional team; Design Engineering; Product Engineering; Business Units; External customer teams
Communication Scope
Verbal communication; Written communication
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Staff Verification Architect and shape modular, scalable verification solutions for next-generation HBM DRAM products across multiple customer platforms! You will be part of a highly multi-functional team of technical domain experts. You will collaborate closely with Design Engineering, Product Engineering, Business Units, and external customer teams to ensure our future HBM roadmap is successful. You will apply your thorough understanding of testbench architecture, custom and SoC verification methodologies, and 2.5D & 3D package integration to analyze bottlenecks and propose innovative solutions targeting scalability, quality, and verification cycle time. ## Responsibilities: * Deliver high-quality, on-time verification plans and architecture collateral across IP-level and SoC-level verification, and develop turnkey solutions for future designs based on look-ahead information from customers and the architecture team * Drive co-verification through direct customer interactions, and mentor early-career engineers to strengthen team capability and technical growth * Build verification methodology improvements and GenAI applications with a roadmap aligned to HBM design cycles, improving verification schedules
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