Company
Sr.StaffVerificationEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Sr. Staff Verification Engineer. Skills: SystemVerilog, UVM, digital IC verification, mixed-signal ICs verification, RTL verification, AMS verification, constrained-random verification, coverage closure. Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits.. Create and maintain detailed test plans, coverage models, and verification environments.”
What You'll Achieve.
Drive coverage closure; Improve verification scalability and portability from project to project
Industry & Context.
analytical; synthesis; problem solving skills; Debug complex simulation failures and identify root causes in design or verification environments.
What They're Looking For.
Must Have
8+ years of industry experience in integrated circuit design verification (DV), B. S. or M. S. in Electrical or Computer Engineering, analytical, synthesis and problem solving skills, In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals., Proficiency in SystemVerilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens), Demonstration of technical leadership, Experience with standard hardware protocols (I2C, I3C, SPI, MIPI), Independent, self-motivated, rigorous, innovating, team player and able to follow through, Excellent verbal and written communication skills
Nice to Have
Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application, Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL, Experience with consumer and/or ITA market circuit developments
What You'll Do.
develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks
and full integrated circuits.
Create and maintain detailed test plans
and verification environments.
Drive coverage closure including functional
and assertion-based coverage.
Generate technical documentation and drive verification reviews.
Design and implement complex testbenches using SystemVerilog and UVM methodology.
Perform block and chip-level register-transfer level (RTL)
gate-level and analog/mixed-signal (AMS) verification.
Develop directed test cases
constrained-random verification environments and reusable verification components.
Debug complex simulation failures and identify root causes in design or verification environments.
Improve verification scalability and portability from project to project by environment enhancement and tools automation.
Generate and manage continuous integration
Report to remote verification & design teams.
Mentor junior verification engineers.
Interface with system
analog and cross functional teams.
Drive adoption of advanced verification methodologies
best practices and tool evaluation.
Technical support to silicon lab evaluation
product and application engineers.
How You'll Work.
Team & Collaboration
Work closely with design teams to understand micro-architecture and functional specifications.; Report to remote verification & design teams.; Interface with system, digital hardware, embedded firmware, analog and cross functional teams.; Technical support to silicon lab evaluation, test, product and application engineers.
Communication Scope
Excellent verbal and written communication skills
Full Job Description
**Responsibilities:** * Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%) * Design and implement complex testbenches using SystemVerilog and UVM methodology. Perform block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Debug complex simulation failures and identify root causes in design or verification environments. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Generate and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (30%) * Report to remote verification & design teams. Mentor junior verification engineers. (20%) * Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%) * Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%) * Technical support to silicon lab evaluation, test, product and application engineers. (5%) **Minimum Qualifications:** * 8+ years of industry experience in integrated circuit design verification (DV) * B.S. or M.S. in Electrical or Computer Engineering * Strong analytical, synthesis and problem solving skills * In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals,
Applying for this Sr. Staff Verification Engineer role?
Most applicants get filtered before a human reads their resume. See if yours makes the cut.
How to Apply on Workday
- Workday has a multi-step form — save your progress after every section.
- "Apply With LinkedIn" can fail or lose data; manual entry is more reliable.
- Watch for the "Submit for Review" final step — hitting "Save" alone does not submit.
- Job requisition numbers are useful when following up with HR by email.
ANONYMOUS · UNFILTERED
What do employees actually say about this company?
Real rants from real employees. Read before you apply.