SpaceX

Internet

Sr.SOC/ASICPhysicalDesignEngineer(SiliconEngineering)

$170–230k Austin, Texas, United States
The Brief

“Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX. Skills: Physical Design, ASIC Implementation, Signoff Closure. Perform partition synthesis. Perform physical implementation steps”

What You'll Achieve.

deliver cutting-edge solutions; expand the performance and capabilities of the Starlink network

Industry & Context.

Internet
Problems you'll solve

Resolve design/timing/congestion and flow issues; identify potential solutions

Eligibility Requirements

Ability to work extended hours and weekends as needed

What They're Looking For.

Must Have

Bachelor's degree in electrical engineering, computer engineering or computer science, 5+ years of ASIC and/or physical design flow development experience in industry

Nice to Have

experience in ASIC/SOC RTL2GDSII physical design and signoff flows, experience with industry standard EDA tools, Knowledge of deep sub-micron FinFET and CMOS solid state physics, Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries, Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic, Familiar with CMOS analog circuit and physical design, Knowledge of DFT/Scan/MBIST/LBIST, understanding of their impact on physical design flows, Good scripting skills, Self-driven individual, can-do attitude, willing to learn, ability to work in a dynamic group environment

What You'll Do.

Perform partition synthesis

Perform physical implementation steps

Develop physical design methodologies

Improve physical design methodologies

Develop automation scripts

Improve automation scripts

Collaborate with ASIC design team

Drive architectural feasibility studies

Develop timing targets

Develop power targets

Explore RTL tradeoffs

Explore design tradeoffs

Resolve design issues

Resolve timing issues

Resolve congestion issues

Identify potential solutions

Run signoff closure issues

Debug signoff closure issues

Fix signoff closure issues

How You'll Work.

Team & Collaboration

work alongside world-class cross-disciplinary teams; Closely collaborate with the ASIC design team

Free ATS check

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