SpaceX
Internet
Sr.SOC/ASICPhysicalDesignEngineer(SiliconEngineering)
“Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX. Skills: Physical Design, ASIC, EDA tools, scripting. Perform partition synthesis. Perform physical implementation steps”
What You'll Achieve.
deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network
Industry & Context.
Resolve design/timing/congestion issues; identify potential solutions
Ability to work extended hours and weekends as needed to meet critical project milestones, U. S. citizen or national, U. S. lawful, permanent resident (aka green card holder), Refugee under 8 U. S. C. § 1157, Asylee under 8 U. S. C. § 1158, eligible to obtain the required authorizations from the U. S. Department of State
What They're Looking For.
Must Have
Bachelor's degree in electrical engineering, computer engineering or computer science, 5+ years of ASIC and/or physical design flow development experience in industry
Nice to Have
experience in ASIC/SOC RTL2GDSII physical design and signoff flows, experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms, Knowledge of deep sub-micron FinFET and CMOS solid state physics, Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries, Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic, Familiar with CMOS analog circuit and physical design, Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows, Good scripting skills (cshash, Perl, Python, TCL, Makefile etc.)
What You'll Do.
Perform partition synthesis
Perform physical implementation steps
Develop/improve physical design methodologies
Develop automation scripts
Collaborate with ASIC design team
Drive architectural feasibility studies
power and area targets
Explore RTL/design tradeoffs
Resolve design/timing/congestion issues
Identify potential solutions
Run signoff closure issues
Debug signoff closure issues
Fix signoff closure issues
How You'll Work.
Team & Collaboration
Closely collaborate with the ASIC design team; work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation)
Applying for this Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) role?
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