Cadence
SrPrincipalVerificationEngineer
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“Sr Principal Verification Engineer at Cadence. Skills: UVM, SystemVerilog, Verification, Protocols. scheduling verification environments. designing verification environments”
What You'll Achieve.
maintain high product quality
Industry & Context.
debugging design/verification problems; individual and independent R&D skills
What They're Looking For.
Must Have
BS/MS degree EE or CS, 5-7 + years of experience in relevant experience, scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory such as SDRAM (LPDDRx, DDRx, HBMx), DFI PHY, UFS, and complex storage memory models for use on hardware-based verification products, analyze customer & vendor protocol requirements and execute on highly complex verification projects from requirements through delivery to post-delivery support, analyze product-wide feature requirements and execute on their verification, integrate additional related tools and processes—including coverage, reporting, and regressing—to build a robust team-level verification structure and competence, Electrical, Electronics or Computer Science Engineer, expert understanding of HDLs and HVLs such as Verilog and SystemVerilog, Solid experience in simulation using these languages, expert working knowledge of EDA tools (Cadence/ Others), focus towards debugging design/verification problems using these tools, Deep experience with UVM, SystemVerilog, and C++, solid, deep experience on multiple protocols such as UFS Unipro and MPHY, SDRAM, Ethernet, PCIe, USB3/4, MIPI etc, Functional Verification of complex digital systems, e. g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog, Functional Verification of complex protocol-based blocks—e. g. UFS / Unipro/ MPHY verification—with a Hardware Verification Language (HVL) like SystemVerilog, designing and implementing complex functional verification environments, process automation with scripting
Nice to Have
Verification experience using Cadence simulation and/or emulation products, Experience in memory sub-system or controller verification and operation
What You'll Do.
scheduling verification environments
designing verification environments
developing verification environments
supporting verification environments
analyze customer protocol requirements
execute complex verification projects
analyze product feature requirements
execute verification of features
integrate tools and processes
build verification structure
enhance product verification
demonstrate product quality
Updating test environments
enhancing test environments
maintaining test environments
supporting test environments
Supporting product regression
product release preparation
How You'll Work.
Team & Collaboration
establish close, collaborative working relationships with team colleagues, peers, customers, vendors, and management; Work effectively across functions and geographies; Participate in team evaluate and recommend process improvements
Communication Scope
English verbal and written skills
Full Job Description
## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** **_Qualifications_** Minimal qualification requires BS/MS degree EE or CS with _[ 5-7 + years (T4) ] _of experience in relevant experience. As a _[Principal Verification Engineer (T4) ]_ you will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory such as SDRAM (LPDDRx, DDRx, HBMx), DFI PHY, UFS, and complex storage memory models for use on hardware-based verification products. · Must analyze customer & vendor protocol requirements and execute on highly complex verification projects from requirements through delivery to post-delivery support. · Must analyze product-wide feature requirements and execute on their verification. · Must integrate additional related tools and processes—including coverage, reporting, and regressing—to build a robust team-level verification structure and competence. Additional responsibilities include the following: · Researching tools, languages, methodologies and prototype processes to enhance product verification as well as to demonstrate product quality. · Updating, enhancing, maintaining, and supporting existing system level UVM test environments for memory model products. · Supporting product (IP Library) regression, OS compliance, process automation, and product release preparation as needed. **_Job Responsibilities & Skills: _[Principal Verification Engineer (T4) ]__** · Candidate must be an Electrical, Electronics or Computer Science Engineer with expert understanding of HDLs and HVLs such as Verilog and SystemVerilog. · Solid experience in simulation/emulation using these languages. He/ she should have expert working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools. · Deep experience with UVM, SystemVerilog, and C++. · Must have so
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